W. Wesley Peterson
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William Wesley Peterson (April 22, 1924 – May 6, 2009) was an American mathematician and computer scientist. He was best known for designing the cyclic redundancy check (CRC),[1] for which research he was awarded the Japan Prize in 1999.[2]
Biography
Peterson was born on April 22, 1924, in Muskegon, Michigan and earned his Ph.D. in 1954 from the University of Michigan.[2][3] Peterson was a professor of Information and Computer Sciences at the University of Hawaii at Manoa, joining the faculty in 1964.[4] He started work at IBM in 1954.[4] He authored the publication of algebraic coding theory Error Correcting Codes in 1961. He co-authored a number of books on the topic of error correcting codes, including the revised 2nd edition of Error Correcting Codes[5] (co-authored with Edward J. Weldon). In the early 1950s, he contributed significantly to the development of signal detection theory through participation in the IRE Professional Group on Information Theory.[6] He has also done research and published in the fields of programming languages,[7] systems programming, and networks. As well as the Japan Prize in 1999,[2][8] he was awarded the Claude E. Shannon Award in 1981,[4] and the IEEE Centennial Medal in 1984.[4] In 2007, two years before Peterson's death, Intel added crc32 to the SSE4.2 instruction set of the x86-64 architecture.[9]
Peterson finished 16th in the 2005 Honolulu Marathon for males ages 80 to 84.[10] He died on May 6, 2009, in Honolulu, Hawaii survived by five children from two different marriages, his wife, and several grandchildren.[3]
References
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- ↑ Script error: No such module "Citation/CS1". – The original paper on CRCs
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- ↑ a b c d The Newsletter of the Colleges of Arts & Sciences at the University of Hawaii at Manoa, Summer 1999, Volume 5, Number One Retrieved November 24, 2011
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External links
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