Tick–tock model

From Wikipedia, the free encyclopedia
Jump to navigation Jump to search

Template:Short description Tick–tock was a production model adopted in 2007 by chip manufacturer Intel. Under this model, every new process technology was first used to manufacture a die shrink of a proven microarchitecture (tick), followed by a new microarchitecture on the now-proven process (tock). It was replaced by the process–architecture–optimization model, which was announced in 2016 and is like a tick–tock cycle followed by an optimization phase. More generally, tick–tock is an engineering model which refreshes one half of a binary system each release cycle.

History

Every "tick" represented a shrinking of the process technology of the previous microarchitecture (with minor changes, commonly to the caches, and rarely introducing new instructions, as with Broadwell in late 2014) and every "tock" designated a new microarchitecture.[1] These occurred roughly every year to 18 months.[1]

Due to the slowing rate of process improvements, in 2014 Intel created a "tock refresh" of a tock in the form of a smaller update to the microarchitecture[2] not considered a new generation in and of itself. In March 2016, Intel announced in a Form 10-K report that it would always do this in future, deprecating the tick–tock cycle in favor of a three-step process–architecture–optimization model, under which three generations of processors are produced under a single manufacturing process, with the third generation out of three focusing on optimization.[3]

After introducing the Skylake architecture on a 14 nm process in 2015, its first optimization was Kaby Lake in 2016. Intel then announced a second optimization, Coffee Lake, in 2017[4] making a total of four generations at 14 nm[5] before the Palm Cove die shrink to 10 nm in 2018.

Roadmap

Pentium 4 / Core / Xeon Roadmap

Template:Mw-datatable

Pentium 4 / Core / Xeon Roadmap
Change
(step) 		Fabri­cation
process 		Micro-
architecture 		Code names
for step 		Intel
Generation
Desktop/Mobile 		Intel
Generation
Xeon 		Intel Microcode
shortcut(s)
Desktop/WS[6][7] 		Intel Microcode
shortcut(s)
Xeon/Server 		ReleaseScript error: No such module "String".date Processors
8P/4P Server 4P/2P Server/WS Embedded Xeon 1P Xeon Enthusiast/WS Desktop Mobile
Tick
(new fabrica-
tion process) 		65 nm P6, NetBurst Yonah (P6),
Presler (NetBurst),
Cedar Mill (NetBurst) 		— 1995-11-1 (P6),
2000-11-20 (NetBurst) 		— — — Presler (NetBurst) Cedar Mill (NetBurst) Yonah (P6)
Tock
(new micro-
architecture) 		Core Merom[8] 2006-07-27[9][10] Tigerton Woodcrest
Clovertown 		Kentsfield Conroe Merom
Tick 45 nm Penryn 2007-11-11[11] Dunnington Harpertown Yorkfield Wolfdale Penryn
Tock Nehalem Nehalem 1 — NHM[12] — 2008-11-17[13] Beckton Gainestown Lynnfield Bloomfield Lynnfield Clarksfield
Tick 32 nm Westmere 1 WSM[12] 2010-01-04[14][15] Westmere-EX Westmere-EP — Gulftown Clarkdale Arrandale
Tock Sandy Bridge Sandy Bridge 2 1 (E3/E5) SNB JKT (Jaketown) 2011-01-09[16] Skipped[17] Sandy Bridge-EP Gladden Sandy Bridge Sandy Bridge-E Sandy Bridge Sandy Bridge-M
Tick 22 nm[18] Ivy Bridge 3 2 (E3/E5/E7) IVB IVT (Ivytown) 2012-04-29 Ivy Bridge-EX[19] Ivy Bridge-EP[19] Gladden Ivy Bridge Ivy Bridge-E[20] Ivy Bridge Ivy Bridge-M
Tock Haswell Haswell 4 3 (E3/E5/E7) HSW, CRW (Crystal Well)
with Iris Pro[21][22] 		HSX 2013-06-02 Haswell-EX Haswell-EP — Haswell-DT Haswell-E Haswell-DT[23] Haswell-MB (notebooks)
Haswell-LP (ultrabooks)[23]
Refresh Haswell Refresh,
Devil's Canyon[24] 		— — 2014-05-11,
2014-06-02 		colspan="5" rowspan="1" align="center" Template:Unreleased Devil's Canyon rowspan="1" align="center" Template:Unreleased
Tick (Process) 14 nm[18] Broadwell[25] 5 4 (E3/E5/E7) BDW BDX 2014-09-05 Broadwell-EX[26] Broadwell-EP[26] Broadwell-DE Broadwell-DT Broadwell-E Broadwell-DT Broadwell-H
Broadwell-U
Broadwell-Y
Tock (Architecture) Skylake[25] Skylake[25] 6 5 (E3)
1 (SP)
W-2100
W-31xx 		SKL
SKL-S
SKL-X
SKL-H
SKL-U
SKL-Y
SKL-D
SKL-DT 		SKX 2015-08-05[27] Skylake-SP Skylake-DE Skylake-D/DT/H Skylake-X Skylake Skylake-H
Skylake-U
Skylake-Y
Optimization
(Refresh)
[3][28][29][30] 		Kaby Lake[31] 7 6 (E3) KBL — 2017-01-03[32] colspan="3" Template:Unreleased Kaby Lake-DT/H
cores: 4 (4/8) 		Kaby Lake-X[33] Kaby Lake Kaby Lake-H
Kaby Lake-U
Kaby Lake-Y
Kaby Lake R[34][35] 8 — KBL-R 2017-08-21[35] colspan="6" Template:Unreleased Kaby Lake R
Coffee Lake 8[36] E-2100 CFL
CFL-S
CFL-E
CFL-H
CFL-U 		2017-10-05[37] colspan="2" Template:Unreleased Coffee Lake-H Coffee Lake-S WS (Coffee Lake-E) Template:Unreleased Coffee Lake-S Coffee Lake-H
Coffee Lake-U
Whiskey Lake,
Amber Lake[38] 		8 — WHL
AML 		2018-08-28[38] colspan="6" Template:Unreleased Whiskey Lake-U
Amber Lake-Y
Skylake (Skylake-X Refresh) 9 ? 2018-10-08[39] colspan="4" Template:Unreleased Skylake X colspan="2" Template:Unreleased
Coffee Lake (Coffee Lake Refresh) 9[36] E-2200 CFL-R
CFL-ER
CFL-HR 		— 2018-10-08,[40] 2019-04-23[41] colspan="3" Template:Unreleased Coffee Lake-S WS (Coffee Lake-ER) Template:Unreleased Coffee Lake-R Coffee Lake-H Refresh
Cascade Lake 10 2 (SP)
W-2200
W-3200 		CSL CXL 2019-04-02[42] Cascade Lake-SP Cascade Lake-AP — Cascade Lake-W
Cascade Lake-X 		colspan="2" Template:Unreleased
Comet Lake,[43] Amber Lake 10 — CML
AML 		— 2019-08-21[43] colspan="4" rowspan="1" align="center" Template:Unreleased Comet Lake-W Comet Lake-S Comet Lake-H
Comet Lake-U
Amber Lake-Y
Cascade Lake (Cascade Lake Refresh) — 2 (SP) — ? 2020-02-24[44] Cascade Lake R colspan="5" Template:Unreleased
Cooper Lake — 3 (SP) — CPL
CPL-SP 		2020-06-18[45] Cooper Lake-SP colspan="6" Template:Unreleased
Architecture Cypress Cove[46] Rocket Lake[46] 11 E-2300 RKL — 2021-03-30[47] — Rocket Lake-E Rocket Lake-W Rocket Lake-S —
Process 10 nm Palm Cove Cannon Lake 8 — CNL 2018-05-16[48] colspan="6" Template:Unreleased Cannon Lake-U
Architecture Sunny Cove Ice Lake[49] 10 3 (SP) ICL ICX[50]
ICL-SP[50] 		2019-08-01[51] — Ice Lake-SP (2021-04-06)[50] Ice Lake-D (April 2021) — Ice Lake-U
Ice Lake-Y
Optimization[30] Willow Cove Tiger Lake[30] 11 — TGL — 2020-09-02[52] colspan="6" Template:Unreleased Tiger Lake-H35
Tiger Lake-UP3
Tiger Lake-UP4
Architecture Intel 7 Golden Cove Alder Lake 12 ADL 2021-11-04 colspan="5" align="center" Template:Unreleased Alder Lake-S Alder Lake-HX
Alder Lake-H
Alder Lake-P
Alder Lake-U
Sapphire Rapids[53] — 4 (SP)
W-2400
W-3400 		— SPR 2023-01-10 Sapphire Rapids-SP Sapphire Rapids-HBM
Sapphire Rapids-SP 		— Sapphire Rapids-WS colspan="2" align="center" Template:Unreleased
Optimization Raptor Cove Raptor Lake 13 — RPL — 2022-10-20 colspan="5" align="center" Template:Unreleased Raptor Lake-S Raptor Lake-HX
Raptor Lake-H
Raptor Lake-P
Raptor Lake-U
Raptor Lake[54] (Raptor Lake Refresh) 14 E-2400 RPL-R 2023-10-17 colspan="3" Template:Unreleased Raptor Lake-E — Raptor Lake-S Refresh —
— 2024-01-08 Mobile processors refreshed Raptor Lake-HX Refresh
Core Series 1 Raptor Lake-U Refresh
Emerald Rapids — Xeon 5
(SP) 		— EMR 2023-12-14 Emerald Rapids-SP colspan="5" align="center" Template:Unreleased
Tick Intel 4[55] Redwood Cove Meteor Lake[56] Core Ultra (Series 1) — MTL — 2023-12-14 colspan="5" Template:Unreleased Meteor Lake-S
Meteor Lake-PS 		Meteor Lake-H
Meteor Lake-U
Tick Intel 3 Granite Rapids[57] — Xeon 6 (SP) — GNR 2024-09-24[58] — Granite Rapids-AP — rowspan="3" colspan="4" Template:Unreleased
2025 Q1[58][59] Granite Rapids-SP
2025[60] — Granite Rapids-D
Tick Intel 20A Lion Cove Arrow Lake[61] 15 (informally)
Core Ultra 200S
Core Ultra (Series 2) 		— ARL — 2024-10-03 rowspan="2" colspan="5" align="center" Template:Unreleased Arrow Lake-S
Arrow Lake-SK 		—
Core Ultra 200H
Core Ultra 200HX
Intel Core Ultra H & HX Series[62] 		2025 Q1[62] Arrow Lake-R
Arrow Lake-K
Arrow Lake-KF 		Arrow Lake-HX
Arrow Lake-H
Tick Intel 18A Lunar Lake Core Ultra 200V
Core Ultra (Series 2) 		— LNL — 2024-09-03 colspan="6" align="center" Template:Unreleased Lunar Lake-V
Lunar Lake-MX
Change
(step) 		Fabri­cation
process 		Micro-
architecture 		Code names
for step 		Intel
Generation
Desktop 		Intel
Generation
Xeon 		Intel Microcode
shortcut(s)
Desktop/WS[6][7] 		Intel Microcode
shortcut(s)
Xeon/Server 		ReleaseScript error: No such module "String".date 8P/4P Server 4P/2P Server/WS Embedded Xeon 1P Xeon Enthusiast/WS Desktop Mobile
Processors

Atom roadmap

Script error: No such module "anchor".

With Silvermont Intel tried to start Tick-Tock in Atom architecture but problems with the 10 nm process prevented it.

In the table below instead of Tick-Tock steps Process-Architecture-Optimization are used. There is no official confirmation that Intel uses Process-Architecture-Optimization for Atom, but it enables us to understand what changes happened in each generation.

Template:Mw-datatable

Atom roadmap[63]
Change Fabri­cation
process 		Micro-
architecture
(Abbr.)[12] 		Code names
for step 		Release
date 		Processors/SoCs
MID, Smartphone Tablet Netbook Nettop Embedded Server CE
Process / Architecture 45 nm Bonnell (BNL) Bonnell 2008 Silverthorne — Diamondville — — —
Optimization Bonnell 2010 Lincroft Pineview Tunnel Creek
Stellarton 		— Sodaville
Groveland
Process 32 nm Saltwell 2011 Medfield (Penwell & Lexington) & Clover Trail+ (Cloverview) Clover Trail (Cloverview) Cedar Trail (Cedarview) — Centerton & Briarwood Berryville
Process / Architecture 22 nm Silvermont (SLM) Silvermont 2013 Merrifield (Tangier)[64] & Moorefield (Anniedale)[65] & Slayton Bay Trail-T
(Valleyview) 		Bay Trail-M
(Valleyview) 		Bay Trail-D
(Valleyview) 		Bay Trail-I
(Valleyview) 		Avoton
Rangeley 		Template:Unk
Process 14 nm[63] Airmont 2014 Binghamton & Riverton Cherry Trail-T (Cherryview)[66] Braswell[67] Denverton
Template:Cancelled 		Template:Unk
Architecture Goldmont[68]
(GLM) 		Goldmont 2016 Broxton Template:Cancelled Broxton Template:Cancelled
Apollo Lake 		Apollo Lake Apollo Lake Template:Unk Denverton Template:Unk
Architecture Goldmont Plus
(GLM+, GLP) 		Goldmont Plus 2017 Template:Unk Gemini Lake Gemini Lake Gemini Lake Template:Unk Template:Unk Template:Unk
Optimization Goldmont Plus 2019 Template:Unk Gemini Lake Refresh Gemini Lake Refresh Gemini Lake Refresh Template:Unk Template:Unk Template:Unk
Process / Architecture 10 nm Tremont Tremont 2020 Template:Unk Jasper Lake Jasper Lake Jasper Lake Elkhart Lake Snow Ridge Template:Unk
Architecture Intel 7 Gracemont Gracemont 2021 Template:Unk Template:Unk Alder Lake & Raptor Lake (hybrid) Template:Unk Template:Unk
Process / Architecture Intel 4 Crestmont Crestmont 2023 Template:Unk Template:Unk Meteor Lake[69] (hybrid) Sierra Forest-SP
Sierra Forest-AP 		Template:Unk

Note: There is further the Xeon Phi. It has up to now undergone four development steps with a current top model that got the code name Knights Landing (shortcut: KNL;[12] the predecessor code names all had the leading term Knights in their name) that is derived from the Silvermont architecture as used for the Intel Atom series but realized in a shrunk 14 nm (FinFET) technology.[70] In 2018, Intel announced that Knights Landing and all further Xeon Phi CPU models were discontinued.[71] However, Intel's Sierra Forest and subsequent Atom-based Xeon CPUs are likely a spiritual successor to Xeon Phi.

Both

Template:Intel processor roadmap Script error: No such module "Navbox".

See also

References

<templatestyles src="Reflist/styles.css" />

  1. ↑ a b Script error: No such module "citation/CS1".
  2. ↑ Script error: No such module "citation/CS1".
  3. ↑ a b Script error: No such module "citation/CS1".
  4. ↑ Template:Cite tweet
  5. ↑ Script error: No such module "citation/CS1".
  6. ↑ a b Intel Releases Linux CPU Microcodes To fix Meltdown & Spectre Bugs by Lawrence Abrams on January 11, 2018
  7. ↑ a b Linux* Processor Microcode Data File Version 20180312 on 3/12/2018
  8. ↑ Script error: No such module "citation/CS1".
  9. ↑ Script error: No such module "citation/CS1".
  10. ↑ Script error: No such module "citation/CS1".
  11. ↑ Script error: No such module "citation/CS1".
  12. ↑ a b c d Script error: No such module "citation/CS1".
  13. ↑ Script error: No such module "citation/CS1".
  14. ↑ Script error: No such module "citation/CS1".
  15. ↑ Script error: No such module "citation/CS1".
  16. ↑ Script error: No such module "citation/CS1".
  17. ↑ Script error: No such module "citation/CS1".
  18. ↑ a b Script error: No such module "citation/CS1".
  19. ↑ a b Script error: No such module "citation/CS1".
  20. ↑ Script error: No such module "citation/CS1".
  21. ↑ Products formerly Crystal Well at Intel web page
  22. ↑ What is Crystalwell? by Matt Egan on OCT 31, 2013 at macworld.com
  23. ↑ a b Script error: No such module "citation/CS1".
  24. ↑ Script error: No such module "citation/CS1".
  25. ↑ a b c Script error: No such module "citation/CS1".
  26. ↑ a b Script error: No such module "citation/CS1".
  27. ↑ Script error: No such module "citation/CS1".
  28. ↑ Script error: No such module "citation/CS1".
  29. ↑ Script error: No such module "citation/CS1".
  30. ↑ a b c Script error: No such module "citation/CS1".
  31. ↑ Script error: No such module "citation/CS1".
  32. ↑ Script error: No such module "citation/CS1".
  33. ↑ Script error: No such module "citation/CS1".
  34. ↑ Products formerly Kaby Lake R
  35. ↑ a b Script error: No such module "citation/CS1".
  36. ↑ a b Script error: No such module "citation/CS1".
  37. ↑ Script error: No such module "citation/CS1".
  38. ↑ a b Script error: No such module "citation/CS1".
  39. ↑ Script error: No such module "citation/CS1".
  40. ↑ Script error: No such module "citation/CS1".
  41. ↑ Script error: No such module "citation/CS1".
  42. ↑ Script error: No such module "citation/CS1".
  43. ↑ a b Script error: No such module "citation/CS1".
  44. ↑ Script error: No such module "citation/CS1".
  45. ↑ Script error: No such module "citation/CS1".
  46. ↑ a b Script error: No such module "citation/CS1".
  47. ↑ Script error: No such module "citation/CS1".
  48. ↑ Script error: No such module "citation/CS1".
  49. ↑ Script error: No such module "citation/CS1".
  50. ↑ a b c Script error: No such module "citation/CS1".
  51. ↑ Script error: No such module "citation/CS1".
  52. ↑ Script error: No such module "citation/CS1".
  53. ↑ Script error: No such module "citation/CS1".
  54. ↑ Script error: No such module "citation/CS1".
  55. ↑ Script error: No such module "citation/CS1".
  56. ↑ Script error: No such module "citation/CS1".
  57. ↑ Script error: No such module "citation/CS1".
  58. ↑ a b Script error: No such module "citation/CS1".
  59. ↑ Script error: No such module "citation/CS1".
  60. ↑ Script error: No such module "citation/CS1".
  61. ↑ Script error: No such module "citation/CS1".
  62. ↑ a b Script error: No such module "citation/CS1".
  63. ↑ a b Script error: No such module "citation/CS1".
  64. ↑ Script error: No such module "citation/CS1".
  65. ↑ Script error: No such module "citation/CS1".
  66. ↑ Script error: No such module "citation/CS1".
  67. ↑ Script error: No such module "citation/CS1".
  68. ↑ Script error: No such module "citation/CS1".
  69. ↑ Script error: No such module "citation/CS1".
  70. ↑ Intel veröffentlicht Xeon Phi mit bis zu 7 Teraflops
  71. ↑ Script error: No such module "citation/CS1".

Script error: No such module "Check for unknown parameters".

External links

fr:Intel#Stratégies tic-tac et processus-architecture-optimisation

Retrieved from "http://debianws.lexgopc.com/wiki143/index.php?title=Tick–tock_model&oldid=6098813"