Successive-approximation ADC

File:SA ADC block diagram.png

Successive-approximation ADC block diagram showing digital-to-analog converter (DAC), end of conversion indicator (EOC), successive-approximation register (SAR), sample and hold circuit (S/H), input voltage (V_in) and reference voltage (V_ref)

A successive-approximation ADC (or SAR ADC) is a type of analog-to-digital converter (ADC) that digitizes each sample from a continuous analog waveform using a binary search through all possible quantization levels.

History

The SAR ADC was first used for experimental pulse-code modulation (PCM) by Bell Labs in the 1940s. In 1954, Bernard Gordon introduced the first commercial vacuum tube SAR ADC, converting 50,000 11-bit samples per second.

Algorithm

The successive-approximation analog-to-digital converter circuit typically contains four chief subcircuits:

1. A sample-and-hold circuit that acquires the input voltage V_in.
2. An analog voltage comparator that compares V_in to the output of a digital-to-analog converter (DAC).
3. A successive-approximation register that is updated by results of the comparator to provide the DAC with a digital code whose accuracy increases each successive iteration.
4. A DAC that supplies the comparator with an analog voltage relative to the reference voltage V_ref (which corresponds to the full-scale range of the ADC) and proportional to the digital code of the SAR.

File:4-bit Successive Approximation DAC.gif

Animation of a 4-bit successive-approximation ADC with V_ref = 5 V

The successive-approximation register is initialized with 1 in the most significant bit (MSB) and zeroes in the lower bits. The register's code is fed into the DAC, which provides an analog equivalent of its digital code (initially Template:SfracV_ref) to the comparator for comparison with the sampled input voltage. If this analog voltage exceeds V_in, then the comparator causes the SAR to reset this bit; otherwise, the bit is left as 1. Then the next bit is set to 1 and the same test is done, continuing this binary search until every bit in the SAR has been tested. The resulting code is the digital approximated output of the sampled input voltage.

The algorithm's objective for the n^th iteration is to approximately digitize the input voltage to an accuracy of 1⁄2ⁿ relative to the reference voltage. To show this mathematically, the normalized input voltage is represented as x in [−1, 1] by letting V_in = xV_ref. The algorithm starts with an initial approximation of x₀ = 0 and during each iteration i produces the following approximation:

i^th approximation: x_i = x_i−1 − Template:Sfrac

where the binary signum function sgn mathematically represents the comparison of the previous iteration's approximation x_i-1 with the normalized input voltage x:

$$sgn(x_{i-1}-x)=\{\begin{array}{ll}+1& \text{if }{x}_{i-1}\ge x,\\ -1& \text{if }{x}_{i-1}<x.\end{array}$$

It follows using mathematical induction that the approximation of the n^th iteration theoretically has a bounded accuracy of: |x_n − x| ≤ Template:Sfrac.

Inaccuracies in non-ideal analog circuits

When implemented as a real analog circuit, circuit inaccuracies and noise may cause the binary search algorithm to incorrectly remove values it believes V_in cannot be, so a successive-approximation ADC might not output the closest value. It is very important for the DAC to accurately produce all 2ⁿ analog values for comparison against the unknown V_in in order to produce a best match estimate. The maximal error can easily exceed several LSBs, especially as the error between the actual and ideal 2ⁿ becomes large. Manufacturers may characterize the accuracy using an effective number of bits (ENOB) smaller than the actual number of output bits.

since 2001Template:Dated maintenance category (articles), the component-matching limitations of the DAC generally limited the linearity to about 12 bits in practical designs and mandated some form of trimming or calibration to achieve the necessary linearity for more than 12 bits. And since kT/C noise is inversely proportional to capacitance, low noise demands a large input capacitance (which costs chip area and requires a more powerful drive buffer), which has motivated proposals around noise cancellation. For comparison, for a V_ref of 5 V, the least significant bit of a 16-bit converter corresponds to 76 µV, which is around the 64 µVrms noise of a 1 pF (large for on-chip) capacitor at room temperature. since 2012Template:Dated maintenance category (articles), SAR ADCs are limited to 18 bits, while delta-sigma ADCs (which can be 24 bits) are better suited if more than 16 bits are needed. SAR ADCs are commonly found on microcontrollers because they are easy to integrate into a mixed-signal process, but suffer from inaccuracies from the internal reference voltage resistor ladder and clock and signal noise from the rest of the microcontroller, so external ADC chips may provide better accuracy.

Successive approximation animation

Operation of successive-approximation ADC as input voltage falls from 5 to 0 V. Iterations on the x axis, starting with the initial state at notch 1. Voltages on the y axis.

Examples

Example 1: The steps to converting an analog input to 9-bit digital, using successive-approximation, are shown here for all voltages from 5 V to 0 V in 0.1 V iterations. Since the reference voltage is 5 V, when the input voltage is also 5 V, all bits are set. As the voltage is decreased to 4.9 V, only some of the least significant bits are cleared. The MSB will remain set until the input is one half the reference voltage, 2.5 V.

The binary weights assigned to each bit, starting with the MSB, are 2.5, 1.25, 0.625, 0.3125, 0.15625, 0.078125, 0.0390625, 0.01953125, 0.009765625. All of these add up to 4.990234375, meaning binary 111111111, or one LSB less than 5.

When the analog input is being compared to the internal DAC output, it effectively is being compared to each of these binary weights, starting with the 2.5 V and either keeping it or clearing it as a result. Then by adding the next weight to the previous result, comparing again, and repeating until all the bits and their weights have been compared to the input, the result, a binary number representing the analog input, is found.

Example 2: The working of a 4-bit successive-approximation ADC is illustrated below. The MSB is initially set to 1 whereas the remaining digits are set to zero. If the input voltage is lower than the value stored in the register, on the next clock cycle, the register changes its value to that illustrated in the figure by following the green line. If the input voltage is higher, then on the next clock cycle, the register changes its value to that illustrated in the figure by following the red line. The simplified structure of this type of ADC that acts on 2ⁿ volts range can be expressed as an algorithm:

1. Initialize register with MSB set to 1 and all other values set to zero.
2. In the n^th clock cycle, if voltage is higher than digital equivalent voltage of the number in register, the (n+1)^th digit from the left is set to 1. If the voltage were lower than digital equivalent voltage, then n^th digit from left is set to zero and the next digit is set to 1. To perform a conversion, an N-bit ADC requires N such clock cycles excluding the initial state.

The successive-approximation ADC can be alternatively explained by first uniformly assigning each digital output to corresponding ranges as shown. It can be seen that the algorithm essentially divides the voltage range into two regions and checks which of the two regions the input voltage belongs to. Successive steps involve taking the identified region from before and further dividing the region into two and continuing identification. This occurs until all possible choices of digital representations are exhausted, leaving behind an identified region that corresponds to only one of the digital representations.

Variants

• Counter type ADC: The D to A converter can be easily turned around to provide the inverse function A to D conversion. The principle is to adjust the DAC's input code until the DAC's output comes within ±1⁄2 LSB to the analog input which is to be converted to binary digital form.
• Servo tracking ADC: It is an improved version of a counting ADC. The circuit consists of an up-down counter with the comparator controlling the direction of the count. The analog output of the DAC is compared with the analog input. If the input is greater than the DAC output signal, the output of the comparator goes high and the counter is caused to count up. The tracking ADC has the advantage of being simple. The disadvantage, however, is the time needed to stabilize as a new conversion value is directly proportional to the rate at which the analog signal changes.

Charge-redistribution successive-approximation ADC

File:ChargeScalingDAC.png

Switched capacitor array acting as the DAC for an N-bit charge-redistribution SAR ADC, fed into a ground-referenced comparator.

One of the most common SAR ADC implementations uses a charge-scaling DAC consisting of an array of individually-switched capacitors sized in powers of two and an additional duplicate of the smallest capacitor, for a total of N+1 capacitors for N bits. Thus if the largest capacitance is C, then the array's total capacitance is 2C. The switched capacitor array acts as both the sample-and-hold element and the DAC. Redistributing their charge will adjust their net voltage, which is fed into the negative input of a comparator (whose positive input is always grounded) to perform the binary search using the following steps:

File:CAPadc.png

3 bit capacitive ADC, using V_ref = 5V. The bottom left transient simulation uses V_in ≅ 3.5V or about .7 of V_ref, resulting in an answer of 5⁄8 (101 in binary), representing 3.125V or 0.625 of V_ref. "PESE" is the voltage on the array, and its remaining final voltage is the conversion's residual error.

1. Discharge: The capacitors are discharged. (Note, discharging to comparator's offset voltage will automatically provide offset cancellation.)
2. Sampling: The capacitors are switched to the input signal V_in. After a brief sampling period, the capacitors will hold a charge equal to their respective capacitance times V_in (and minus the offset voltage upon each of them), so the array holds a total charge of 2C·V_in.
3. Hold: The capacitors are then switched to ground. This provides the comparator's negative input with a voltage of −V_in.
4. Conversion: the actual conversion process proceeds with the following steps in each iteration, starting with the largest capacitor as the test capacitor for the MSB, and then testing each next smaller capacitor in order for each bit of lower significance:
   1. Redistribution: The current test capacitor is switched to V_ref. The test capacitor forms a charge divider with the remainder of the array whose ratio depends on the capacitor's relative size. In the first iteration, the ratio is 1:1, so the comparator's negative input becomes −V_in + V_ref⁄2. On the i^th iteration, the ratio will be 1:2ⁱ⁻¹, so the i^th iteration of this redistribution step effectively adds V_ref⁄2ⁱ to the voltage.
   2. Comparison: The comparator's output determines the bit's value for to the current test capacitor. In the first iteration, if V_in is greater than V_ref⁄2, then the comparator will output a digital 1 and otherwise output a digital 0.
   3. Update Switch: A digital 0 result will leave the current test capacitor connected to V_ref for subsequent iterations, while a digital 1 result will switch the capacitor back to ground. Thus, each i^th iteration may or may not add V_ref⁄2ⁱ to the comparator's negative input voltage. For instance, the voltage at the end of the first iteration will be −V_in + MSB·V_ref⁄2.
5. End Of Conversion: After all capacitors are tested in the same manner, the comparator's negative input voltage will have converged as close as possible (given the resolution of the DAC) to the comparator's offset voltage.

See also

• Quantization noise
• Digital-to-analog converter

Further reading

• CMOS Circuit Design, Layout, and Simulation, 3rd Edition; R. J. Baker; Wiley-IEEE; 1208 pages; 2010; Template:ISBN
• Data Conversion Handbook; Analog Devices; Newnes; 976 pages; 2004; Template:ISBN

External links

• Understanding SAR ADCs: Their Architecture and Comparison with Other ADCs - Maxim
• Choose the right A/D converter for your application - TI