Search results

...emory]]. The SX-6 processor is a single chip implementation containing a [[vector processor]] unit and a [[scalar processor]] fabricated in a 0.15 μm [[CMOS] ...vector pipeline units each with seventy-two 256-word vector registers. The vector unit performs add/shift, multiply, divide and logical operations. The scala ...

...ef> It originally referred to the replacement of [[Vector processor|vector supercomputers]] built with bipolar technology by [[Massively parallel (computing)|Massive [[Category:Supercomputers]] ...

{{Short description|Series of supercomputers}} ...1982, the FACOM VP were the first of the three initial Japanese commercial supercomputers, followed by the Hitachi [[HITAC S-810]] in August 1982 and the NEC [[NEC S ...

...m in a compact node module and uses an enhanced version of the single chip vector processor that was introduced with the [[NEC SX-6|SX-6]]. The NEC SX-8 pro ...r performance 35.2 GFLOPS (10% frequency increase and double the number of vector operations) and can address up to 256 GB of memory in a single node (up fro ...

...1995 by the VPP300, a [[massively parallel]] supercomputer with up to 256 vector processors. ...r]]-based vector processor for performance. For additional performance the vector units supported a special multiply-and-add instruction that could retire tw ...

...ay Y-MP]] architecture. Compared to the Y-MP, the C90 processor had a dual vector pipeline and a faster 4.1 ns clock cycle (244 MHz), which togethe [[Category:Vector supercomputers]] ...

...ped in 1995, and featured a 2.2 ns (450 MHz) clock cycle and two-wide vector pipes, for a peak speed of 1.8 [[gigaflops]] per processor; the high clock [[Category:Vector supercomputers]] ...

...s CVC, pronounced "Civic" like the [[Honda]] car of the period, for [[Cray Vector Compiler]]. ...Cray-1 architecture-dependent without extensive rework when larger memory supercomputers like the Cray-2 and the Cray Y-MP came into use. CTSS has its final breaths ...

...g]] and small-scale [[multiprocessing]]. As [[scientific computing]] using vector processors became more popular, the need for lower-cost systems that might [[Category:Vector supercomputers| ]] ...

| supported_platforms = [[NEC SX]] supercomputers ...10.1109/SC.1996.5 |chapter-url=http://www.ai.mit.edu/projects/aries/papers/vector/hammond.pdf |access-date=25 August 2018}}</ref> ...

{{Short description|Series of supercomputers for earth sciences}} ...'Earth Simulator''' ('''ES''')|地球シミュレータ|Chikyū Shimyurēta}} is a series of supercomputers deployed at [[Japan Agency for Marine-Earth Science and Technology]] Yokoha ...

| industry = Supercomputers ...was a company that developed, manufactured and marketed [[Vector processor|vector]] [[minisupercomputer]]s and [[supercomputer]]s for small-to-medium-sized b ...

...ly a shrunk and sped-up version of the Cray-3, consisting of a number of [[vector processors]] attached to a fast memory. The Cray-3 supported from four to s [[Category:Vector supercomputers]] ...

{{Short description|Series of supercomputers by NEC}} '''NEC SX''' describes a series of [[Vector processor|vector]] [[supercomputer]]s designed, manufactured, and marketed by [[NEC]]. This ...

...em is also referred to as '''Velocity Engine''' by Apple and '''VMX''' ('''Vector Multimedia Extension''') by IBM and P.A. Semi. Both VMX/AltiVec and [[Streaming SIMD Extensions|SSE]] feature 128-bit vector registers that can represent sixteen 8-bit signed or unsigned chars, eight ...

...omplete Cray-3 CPU, allowing the machine as a whole to use either SIMD or vector instructions depending on the particulars of the problem. ...emained was the selection of a processor. Since the Cray-3 already had a [[vector processor]] for heavy computing, the SIMD processors themselves could be co ...

...g in the Cray-1 would demarcate the ASC (and STAR-100) as first-generation vector processors, with the Cray-1 belonging in the second. ...esults every cycle, depending on the number of vector lanes installed. The vector lanes were also used for scalar instructions, and each lane could keep up t ...

...pport, by [[DARPA]], of competitors [[Intel]] for their hypercube Personal SuperComputers ([[Intel iPSC|iPSC]]) and the [[Thinking Machines Corporation|Thinking Mach ...anufacturer of [[SIMD]] supercomputers (as opposed to [[vector processor | vector machines]]). In this approach, a collection of [[Arithmetic logic unit|ALU] ...

...s|BLAS]] (Basic Linear Algebra Subprograms) libraries for performing basic vector and matrix operations. ...(benchmark)|HPL]] (High Performance Linpack) is used to benchmark and rank supercomputers for the [[TOP500]] list. ...

...y be shared-memory or local-memory [[multiprocessor]]s, [[Vector processor|vector]] [[supercomputer]]s, specialized [[CPU|graphics engines]], or [[Scalar pro ...