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  • * [[Interrupt descriptor table]], a memory structure of x86 microprocessors * [[Interactive data transformation]], a form of data transformation via a visual interface intended for analysts and business users with limited te ...
    1 KB (160 words) - 20:26, 16 February 2023
  • ...ion|Central processing unit designed by Centaur Technology and sold by VIA Technologies}}{{Infobox CPU | manuf1 = VIA Technologies ...
    9 KB (1,221 words) - 20:38, 21 December 2024
  • ...ed by [[VIA Technologies]], still producing compatible low-end devices for VIA * [[Cyrix]] – acquired by [[National Semiconductor]], later acquired by [[VIA Technologies]], eventually shut down ...
    11 KB (1,409 words) - 09:10, 7 October 2024
  • {{Short description|Family of x86 central processing units for personal computers}} | manuf1 = VIA ...
    11 KB (1,624 words) - 02:38, 9 May 2025
  • ...of the [[Socket 7]] [[Zero insertion force|ZIF]] socket specification for x86 processors. It was released in May 1998.<ref>{{cite web|last1=Torres|first1 ...otherboards lingered, and though an internal program by [[VIA Technologies|VIA]] to raise standards for their chipsets had begun to show results in the [[ ...
    4 KB (526 words) - 21:38, 19 May 2025
  • {{Short description|Series of x86-compatible processor}} | arch = [[x86-16]], [[IA-32]] ...
    8 KB (1,036 words) - 19:55, 20 June 2025
  • ...command register. These registers were accessed by variants of the [[MOV (x86 instruction)|MOV]] instruction. A test register may either be the source op ...test registers and/or associated opcodes were supported in the following [[x86]] processors: ...
    10 KB (1,531 words) - 23:26, 1 January 2025
  • {{Short description|Cyrix x86 microprocessor}} |arch = [[x86-16]], [[IA-32]] ...
    13 KB (1,848 words) - 02:34, 9 May 2025
  • ...Integrated Systems|SiS]], [[Nvidia|NVIDIA]] and from AMD subsidiary [[ATI Technologies|ATI]]. The initiative also includes platforms succeeding the ''Kite Refresh |align="center" | '''[[List of AMD Sempron microprocessors#Mobile Sempron "Keene" (Socket S1, F2, 90 nm, Low power)|Mobile Sempron]]'' ...
    21 KB (2,667 words) - 20:22, 17 July 2024
  • | arch = [[x86-16]], [[IA-32]] ...discontinued [[CPU electrical consumption|low-power]] [[Socket 7]]-based [[x86]] [[central processing unit|processor]] that was designed by [[Centaur Tech ...
    15 KB (2,053 words) - 23:55, 4 May 2025
  • ...of 1984 was the [[New Enhanced AT|NEAT chipset]] developed by [[Chips and Technologies]] for the [[Intel 80286]] CPU. In [[x86]]-based personal computers, the term ''chipset'' often refers to a specific ...
    12 KB (1,724 words) - 11:19, 10 June 2025
  • ...otorola 68000 series|68000]] families; the Intel [[8080]], [[iAPX 432]], [[x86]] and [[8051]] families; the Zilog [[Z80]], [[Zilog Z8|Z8]] and [[Z8000]] f ...ran]] or [[ALGOL|Algol]] were not always available or appropriate. Indeed, microprocessors in this category are sometimes still programmed in assembly language for ce ...
    17 KB (2,386 words) - 19:21, 18 November 2025
  • {{Short description|Series of x86-compatible processor}} '''Geode''' is a series of [[x86]]-compatible [[system-on-a-chip]] (SoC) [[microprocessor]]s and I/O compani ...
    21 KB (2,818 words) - 17:17, 7 August 2024
  • ...ious models continued until 1993 when [[Silicon Graphics|SGI]] bought MIPS Technologies. SGI cancelled the MIPS Magnum line to promote their own workstations inclu The MIPS Magnum 3000 has a 25 or 33&nbsp;MHz [[MIPS Technologies|MIPS]] [[R3000A]] microprocessor. ...
    9 KB (1,351 words) - 20:54, 10 May 2025
  • ...(CPU) and [[peripheral device]]s in a [[computer]] (often mediating access via [[chipset]]). An alternative approach is using dedicated I/O processors, co ...the hardware. The reservation may be permanent, or temporary (as achieved via [[bank switching]]). An example of the latter is found in the [[Commodore 6 ...
    17 KB (2,651 words) - 01:44, 18 November 2024
  • | arch = [[x86-16]], [[IA-32]], [[x86-64]] ...ology included in the design is [[Macro-Ops Fusion]], which combines two [[x86]] instructions into a single [[micro-operation]]. For example, a common cod ...
    57 KB (7,647 words) - 01:59, 17 May 2025
  • ...nstructions <code>[[SCAS (x86 instruction)|SCAS]]</code> and <code>[[CMPS (x86 instruction)|CMPS]]</code>) while a less or not less condition remained tru .../code> (call native) which issues an 8086-type interrupt call that enables x86 code (which returns using an <code>IRET</code>) to be mixed in with 8080 co ...
    23 KB (3,347 words) - 22:31, 28 June 2025
  • ..._via_130m_microtec_acquisition |title=Mentor Graphics to add real time ARM via $130m Microtec acquisition |work=Computer Business Review |date=October 11, ...anger.com/ |title=MapuSoft: Porting Made Easy |date=2008 |website=MapuSoft Technologies |url-status=dead |archive-url=https://web.archive.org/web/20081120174628/ht ...
    7 KB (904 words) - 13:54, 26 May 2025
  • ...Statement Applied Micro Circuits (AMCC) annual SEC income statement filing via Wikinvest.]</ref> ...alance_Sheet Applied Micro Circuits (AMCC) annual SEC balance sheet filing via Wikinvest.]</ref> ...
    12 KB (1,554 words) - 15:37, 10 June 2025
  • [[x86]] processors use context switching and fast interrupts for switching betwee ...ter adapted by [[SPARC]], [[MIPS Technologies|MIPS]] and some of the later x86 implementations. ...
    28 KB (4,449 words) - 06:42, 2 March 2025
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