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| arch = [[SPARC]] V7 ...d instruction set computer|RISC]] [[central processing unit|processor]] ([[SPARC]] V7 specification) developed for space applications. It was developed by [ ...

...Set''', or '''VIS''', is a [[SIMD]] instruction set extension for [[SPARC|SPARC V9]] [[microprocessor]]s developed by [[Sun Microsystems]]. There are five ...[UltraSPARC]] microprocessor (1995) and by Fujitsu in their [[SPARC64 GP]] microprocessors (2000). ...

...hardware]] project, started in December 2005, for CPUs implementing the [[SPARC]] instruction architecture. The initial contribution to the project was [[S {{Soft microprocessors}} ...

| arch = [[SPARC V9]] ...id-1995. It is the first microprocessor from Sun to implement the 64-bit [[SPARC V9]] [[instruction set architecture]] (ISA). [[Marc Tremblay]] was a co-mic ...

| arch = [[SPARC|SPARC V9]] ...generation of UltraSPARC microprocessors, and implement the 64-bit [[SPARC|SPARC V9]] [[instruction set architecture]] (ISA). The UltraSPARC IV was original ...

| platform = [[SPARC]], [[DEC Alpha|Alpha]], [[PowerPC]], [[IA-32]] ...microprocessor]]s. Ports of the compiler have been made for [[PowerPC]], [[SPARC]], [[x86]], and [[DEC Alpha|Alpha]] processors. ...

| arch = [[SPARC V9]] | successor = [[SPARC T3]] ...

...intent to develop a high-performance [[microprocessor]] implementing the [[SPARC]] architecture prompted [[Fujitsu]] to fund the company in 1991. $40.2 mill ...icrosystems]]' [[UltraSPARC|UltraSPARC I]] by a few months to be the first SPARC V9 microprocessor produced. ...

...r [[Sun-3]] series, but employing [[microprocessor]]s based on Sun's own [[SPARC]] V7 [[RISC]] architecture in place of the [[68k]] family processors of pre ...an engineering context to identify the basic hardware architecture of all SPARC-based Sun systems. ...

...SPARCstation 20]] workstations. The bus permits the integration of several microprocessors on a single motherboard, in a [[multiprocessing]] configuration with up to .../www.thefreelibrary.com/hyperSPARC+GOES+HOLLYWOOD%3b+PIXAR+USES+hyperSPARC+MICROPROCESSORS+FROM...-a017824466 |date=2012-10-20 }}.</ref> ...

...ate (DDR) buses (AMD Athlon and Duron) and quad-data rate buses (all Intel microprocessors starting from Pentium 4) the effective bus speed should be divided by 2 for ...y CPU design. While these qualification samples and majority of production microprocessors cannot be overclocked by increasing their clock multiplier, they still can ...

[[File:MCST HT-R1000 Elbrus laptop (cropped).jpg|thumb|Moscow Center of SPARC Technologies designed a laptop for military and industrial use.]] In 1992, a spin-off company [[Moscow Center of SPARC Technologies]] (MCST) was created and continued development, using the "Elb ...

| arch = [[SPARC V9]] ...omputer Systems]] and fabricated by [[Fujitsu]]. It implements the [[SPARC|SPARC V9]] [[instruction set architecture]] (ISA), the first microprocessor to do ...

...Systems|defunct = 1996|type = Private|industry = Semiconductors|products = microprocessors, chipset|location = [[San Jose, California]]}} ...Weitek's WTL 1167]][[File:KL Weitek SPARC Power uP.jpg|thumb|180px|Weitek SPARC Power μP]] ...

...personal-workstation_1990-06_2_6/page/50/mode/2up | title=Solbourne Speeds SPARC | magazine=Personal Workstation | last1=Smith | first1=Bud E. | date=June 1 ...le to reap its just rewards. Begun in 1985, the company's first project, a SPARC-based ECL [[gate array|gate-array]] processor, was supplanted in 1989 by Li ...

Below is a list of typically used addresses by different microprocessors: ...01/SPARCV9.pdf.gz|title=The SPARC Architecture Manual, Version 9|publisher=SPARC International|pages=109–112}}</ref> ...

{{About|the family of microprocessors|other uses|Leon (disambiguation)}} ...ocessor, design derivative{{Clarify|reason=Instruction set is derived from SPARC V8, with changes, or processor design is derived from some chip design by S ...

| arch = [[SPARC V9]] ...PARC T1|date=2006|access-date=August 3, 2024}}</ref> and executes the full SPARC V9 [[instruction set]]. Sun has produced two previous multicore processors ...

...architecture|MIPS]] [[Nios II]], [[OpenRISC]], [[PowerPC]], [[SuperH]], [[SPARC]] ([[ERC32]], [[LEON]]), [[HAL SPARC64|SPARC64]] * [[SPARC]] – [[ERC32]], [[LEON]], [[SPARC V9|V9]] ...

...|date=2011-10-27 }}</ref> Some people have put dozens or hundreds of soft microprocessors on a single FPGA.<ref> | colspan="7" align="center" | ''based on the [[SPARC]] instruction set architecture'' ...