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'''PALcode''' ('''Privileged Architecture Library code''')<ref>{{cite book |title=Alpha Architecture Reference Manual |date=2014 ...

{{Short description|Microcontroller architecture}} {{Infobox CPU architecture ...

...ruction set extension for [[SPARC|SPARC V9]] [[microprocessor]]s developed by [[Sun Microsystems]]. There are five versions of VIS: VIS 1, VIS 2, VIS 2+, ...[UltraSPARC]] microprocessor (1995) and by Fujitsu in their [[SPARC64 GP]] microprocessors (2000). ...

{{Infobox CPU architecture | design = [[Reduced instruction set computer|RISC]] ...

...ependencies are managed by making [[processor registers|registers]] in the microprocessors executing the code synchronising, so one microthread will wait for another ...ncurrency and can be scheduled to different processors. An iterator over a set is created dynamically and is called a family of microthreads. This is the ...

{{distinguish|MIPS architecture|MIPS-X}} {{Infobox CPU architecture ...

[[Image:C64 architecture.png|right|thumbnail|300px|The architecture for Cyclops64]] ...wn as '''[[Blue Gene]]/C''') is a [[cellular architecture]] in development by [[IBM]]. The Cyclops64 project aims to create the first "[[supercomputer]] ...

...r over the internet, as protocols often use [[big endian]] [[byte]] coding by default.<ref>{{cite web| url = http://beej.us/guide/bgnet/output/html/singl ...[[RCA 1802]] series of microprocessors, the SEX, for "<code>SEt X</code>," instruction is used to designate which of the machine's sixteen 16-bit registers is to ...

...w [[UltraSPARC T1]] microprocessor in early 2004. It was instead succeeded by the Fujitsu-designed [[SPARC64 VI]]. ...the ''Millennium'' and ''Niagara'' implemented [[Multithreading (computer architecture)#Coarse-grained multithreading|block multithreading]] - also known as ''coa ...

{{Short description|RISC processor architecture}} {{About|the CPU architecture}} ...

{{short description|Instruction set architecture}} ...ly parallel instruction computing''' ('''EPIC''') is a term coined in 1997 by the [[Itanium|HP–Intel alliance]]<ref>{{cite web ...

{{Short description|Processor using Java bytecode as its instruction set}} ...hine. These were the most popular form of a [[high-level language computer architecture]], and were "an attractive choice for building embedded and real-time syste ...

...e chip's features: ''Ethernet, Token Ring, AXis - Code Reduced Instruction Set''. [[Token Ring]] support has been taken out from the latest chips as it ha ...and various I/O's such as serial and parallel. The CGA-1 chip was designed by Martin Gren and Staffan Göransson.<ref>{{cite web|url=http://www.axis.com/f ...

{{Short description|Microprocessor developed by Sun Microsystems}} ...oprocessor from Sun to implement the 64-bit [[SPARC V9]] [[instruction set architecture]] (ISA). [[Marc Tremblay]] was a co-microarchitect. ...

...e chip. Like its predecessor, the [[Transmeta Crusoe]] (a [[128-bit]] VLIW architecture), Efficeon stresses computational efficiency, low power consumption, and a ...n to [[Physical Address Extension|PAE mode]]. The Efficeon has a 128 KB L1 instruction cache, a 64 KB L1 data cache and a 1 MB L2 cache. All caches are on die. Ad ...

<ref>{{Cite web |title=Motorola 32-Bit Microcontrollers Chosen by GM for Electronic Powertrain Systems |url=https://www.theautochannel.com/ne ...anslation and a hardware-driven, fixed-page address translation prescribed by the first PowerPC specification, the 5xx cores provided a software-driven t ...

...plementing the [[ARM architecture|ARM]] processor architecture. Developed by the ''Advanced Processor Technologies'' group at the [[Department of Comput == List of AMULET microprocessors == ...

...he [[Fujitsu VP]]/[[Fujitsu VP2000|2000]] vector processor [[Supercomputer architecture|supercomputer]] line.<ref>[http://ascii.jp/elem/000/000/346/346429/ 8way VL ...processor]] also in VLIW and vector architecture. Each processor core is [[Instruction pipeline|superpipelined]] as well as 4-unit [[superscalar]]. ...

The '''IMP-16''', by [[National Semiconductor]], was the first multi-chip [[16-bit computing|16- ...rlapping clock that had a +5 to -12 voltage swing. An integral part of the architecture was a 16-bit input mux that provided various condition bits from the ALUs s ...

{{Short description|1998 family of microprocessors by IBM}} ...but was renamed, probably to differentiate the server-oriented [[IBM Power microprocessors|POWER processors]] it replaced from the more consumer-oriented 32-bit Power ...