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* YMM registers in the x86 microprocessor instruction set [[Advanced Vector Extensions]] ...

'''Visual Instruction Set''', or '''VIS''', is a [[SIMD]] instruction set extension for [[SPARC|SPARC V9]] [[microprocessor]]s developed by [[Sun Mic ...ubsequent UltraSPARC and SPARC64 microprocessors implement the instruction set. ...

* Virtual Machine Extensions, instructions on processors with [[x86 virtualization]] * [[AltiVec]], a floating point and integer SIMD instruction set called VMX by IBM ...

| design = [[Reduced instruction set computer|RISC]] | extensions = ...

...re! instruction set is compatible with that of the Z8 but it provides some extensions for use with high-level languages. ...

| extensions = ...32R''' is a 32-bit [[Reduced instruction set computer|RISC]] [[instruction set architecture]] (ISA) developed by [[Mitsubishi Electric]] for embedded [[mi ...

{{Short description|CPU instruction set}} ...]] (developed by AMD, no longer supported on newer CPUs), [[Streaming SIMD Extensions|SSE]], and [[SSE2]]. ...

{{Short description|Computer chip instruction set extension}} ...'''SSE''') is a single instruction, multiple data ([[SIMD]]) [[instruction set]] extension to the [[x86]] architecture, designed by [[Intel]] and introduc ...

{{Short description|SIMD instruction set}} ...t created by [[Intel]] and is the fourth iteration of the [[Streaming SIMD Extensions|SSE]] technology. ...

* All models support: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]]'' * All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[3DNow!|Enhanced 3DNow!]]'' ...

| design = [[Reduced instruction set computer|RISC]] | extensions = ...

| extensions = None, but [[MDMX]] & [[MIPS-3D]] could be used The '''DLX''' (pronounced "Deluxe") is a [[Reduced instruction set computer|RISC]] [[Central processing unit|processor]] [[Computer architectu ...

...lly, it may substitute a sequence of automatically generated [[Instruction set architecture|instructions]] for the original function call, similar to an [ ...cannot assume.<ref>{{cite web |last1=The Clang Team |title=Clang Language Extensions |url=https://clang.llvm.org/docs/LanguageExtensions.html#builtin-assume |we ...

{{short description|Extension to the x86 instruction set by AMD}}{{Infobox computer hardware | type = [[instruction set architecture]] ...

* All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[Intel 64]], [[XD bit]] (an [[NX bit]] implemen * All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[Intel 64]], [[XD bit]] (an [[NX bit]] implemen ...

* All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[3DNow!|Enhanced 3DNow!]], [[NX bit]], [[AMD64] * All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[3DNow!|Enhanced 3DNow!]], [[NX bit]], [[AMD64] ...

...to convert code written for [[x86]] processors to the native [[instruction set]] of the chip. Like its predecessor, the [[Transmeta Crusoe]] (a [[128-bit] ...n to [[Physical Address Extension|PAE mode]]. The Efficeon has a 128 KB L1 instruction cache, a 64 KB L1 data cache and a 1 MB L2 cache. All caches are on die. Ad ...

| extensions = '''Unicore''' is a computer [[instruction set]] architecture designed by the Microprocessor Research and Development Cent ...

* All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[3DNow!|Enhanced 3DNow!]]'' * All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[3DNow!|Enhanced 3DNow!]]'' ...

{{Short description|Instruction set designed by Intel}} '''MMX''' is a ''single instruction, multiple data'' ([[SIMD]]) [[instruction set architecture]] designed by [[Intel]], introduced on January 8, 1997<ref nam ...