AMD K9: Difference between revisions

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K9 appears originally to have been an ambitious 8 issue per clock cycle core redesign of the K7 or the K8 processor core.<ref>{{cite web |url=http://www.theinquirer.net/default.aspx?article=27421 |title=The Inquirer report|work=[[The Inquirer]] |url-status=unfit |archive-url=https://web.archive.org/web/20070906163444/http://www.theinquirer.net/default.aspx?article=27421 |archive-date=September 6, 2007}}</ref>  At one point, K9 was the ''Greyhound'' project at AMD, and was worked on by the K7 design team beginning in early 2001, with tape-out revision A0 scheduled for 2003. The L1 instruction cache was said to hold decoded instructions, essentially the same as Intel's trace cache.
K9 appears originally to have been an ambitious 8 issue per clock cycle core redesign of the K7 or the K8 processor core.<ref>{{cite web |url=http://www.theinquirer.net/default.aspx?article=27421 |title=The Inquirer report|work=[[The Inquirer]] |url-status=unfit |archive-url=https://web.archive.org/web/20070906163444/http://www.theinquirer.net/default.aspx?article=27421 |archive-date=September 6, 2007}}</ref>  At one point, K9 was the ''Greyhound'' project at AMD, and was worked on by the K7 design team beginning in early 2001, with tape-out revision A0 scheduled for 2003. The L1 instruction cache was said to hold decoded instructions, essentially the same as Intel's trace cache.


The existence of a massively parallel CPU design concept for heavily multi threaded applications has also been revealed, as a planned successor to K8. This was reportedly canceled in the conceptualization phase, after about 6 months' work.<ref>{{citation |url=http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2986&p=5 |title=www.anandtech.com/show/2229/5 |publisher=Anandtech.com |page=5 |date=2007-05-11 |accessdate=2012-01-23}}</ref>
The existence of a massively parallel CPU design concept for heavily multi threaded applications has also been revealed, as a planned successor to K8. This was reportedly canceled in the conceptualization phase, after about 6 months' work.<ref>{{citation |url=http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2986&p=5 |archive-url=https://web.archive.org/web/20070513020024/http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2986&p=5 |url-status=dead |archive-date=May 13, 2007 |title=www.anandtech.com/show/2229/5 |publisher=Anandtech.com |page=5 |date=2007-05-11 |accessdate=2012-01-23}}</ref>


At one time K9 was the internal codename for the dual-core [[AMD64]] processors as the brand [[Athlon 64 X2]];<ref>{{cite web |url= http://www.theinquirer.net/default.aspx?article=37444|title=The Inquirer |url-status=unfit |archive-url=https://web.archive.org/web/20070210133934/http://www.theinquirer.net/default.aspx?article=37444 |archive-date=February 10, 2007}}</ref><ref>[http://www.syndrome-oc.net/articles.php?article=94&lang=en Video interview of Giuseppe Amato (AMD's Technical Director, Sales and Marketing EMEA) done in February 2007] {{webarchive |url=https://web.archive.org/web/20070313231334/http://www.syndrome-oc.net/articles.php?article=94&lang=en |date=March 13, 2007 }}</ref> however, AMD has distanced itself from the old K series naming convention, and now seeks to talk about a portfolio of products tailored to different markets.<ref>{{citation |url=http://news.cnet.com/AMD-hatches-new-naming-plan-for-chip-generations/2100-1006_3-5453187.html |title=AMD hatches new naming plan for chip generations |publisher=news.cnet.com |date=2004-11-15 |accessdate=2012-01-23}}</ref>
At one time K9 was the internal codename for the dual-core [[AMD64]] processors as the brand [[Athlon 64 X2]];<ref>{{cite web |url= http://www.theinquirer.net/default.aspx?article=37444|title=The Inquirer |url-status=unfit |archive-url=https://web.archive.org/web/20070210133934/http://www.theinquirer.net/default.aspx?article=37444 |archive-date=February 10, 2007}}</ref><ref>[http://www.syndrome-oc.net/articles.php?article=94&lang=en Video interview of Giuseppe Amato (AMD's Technical Director, Sales and Marketing EMEA) done in February 2007] {{webarchive |url=https://web.archive.org/web/20070313231334/http://www.syndrome-oc.net/articles.php?article=94&lang=en |date=March 13, 2007 }}</ref> however, AMD has distanced itself from the old K series naming convention, and now seeks to talk about a portfolio of products tailored to different markets.<ref>{{citation |url=http://news.cnet.com/AMD-hatches-new-naming-plan-for-chip-generations/2100-1006_3-5453187.html |title=AMD hatches new naming plan for chip generations |publisher=news.cnet.com |date=2004-11-15 |accessdate=2012-01-23}}</ref>

Latest revision as of 05:26, 6 August 2025

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The AMD K9 represents a microarchitecture by AMD designed to replace the K8 processors, featuring dual-core processing.

Development

K9 appears originally to have been an ambitious 8 issue per clock cycle core redesign of the K7 or the K8 processor core.[1] At one point, K9 was the Greyhound project at AMD, and was worked on by the K7 design team beginning in early 2001, with tape-out revision A0 scheduled for 2003. The L1 instruction cache was said to hold decoded instructions, essentially the same as Intel's trace cache.

The existence of a massively parallel CPU design concept for heavily multi threaded applications has also been revealed, as a planned successor to K8. This was reportedly canceled in the conceptualization phase, after about 6 months' work.[2]

At one time K9 was the internal codename for the dual-core AMD64 processors as the brand Athlon 64 X2;[3][4] however, AMD has distanced itself from the old K series naming convention, and now seeks to talk about a portfolio of products tailored to different markets.[5]

References

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