Super Harvard Architecture Single-Chip Computer: Difference between revisions
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{{Short description|Series of digital signal processor chips}} | {{Short description|Series of digital signal processor chips}} | ||
{{Distinguish|SuperH}} | |||
{{Primary sources|date=September 2010}} | {{Primary sources|date=September 2010}} | ||
{{ | {{Infobox CPU architecture | ||
The '''Super Harvard Architecture Single-Chip Computer''' ('''SHARC''') is a high performance [[floating-point]] and [[Fixed-point arithmetic|fixed-point]] [[digital signal processor|DSP]] from [[Analog Devices]]. SHARC is used in a variety of signal processing applications ranging from [[ | | name = SHARC | ||
| designer = [[Analog Devices]] | |||
| bits = 32-bit | |||
| introduced = {{Start date and age|1999}} | |||
| version = | |||
| design = DSP/RISC | |||
| type = [[Load–store]], [[Harvard architecture]], [[Word addressing|word-addressed]], [[VLIW]] | |||
| encoding = 48-bit | |||
| branching = ? | |||
| endianness = Neither | |||
| extensions = | |||
| open = | |||
| registers = ? | |||
| gpr = ? | |||
| fpr = | |||
}} | |||
The '''Super Harvard Architecture Single-Chip Computer''' ('''SHARC''') is a high performance [[floating-point]] and [[Fixed-point arithmetic|fixed-point]] [[digital signal processor|DSP]] from [[Analog Devices]]. SHARC is used in a variety of signal processing applications ranging from [[Audio signal processing|audio processing]], to single-CPU guided artillery shells to 1000-CPU over-the-horizon radar processing computers. The original design dates to about January 1994. | |||
SHARC processors are typically intended to have a good number of serial links to other SHARC processors nearby, to be used as a low-cost alternative to [[Symmetric multiprocessing|SMP]]. | SHARC processors are typically intended to have a good number of serial links to other SHARC processors nearby, to be used as a low-cost alternative to [[Symmetric multiprocessing|SMP]]. | ||
==Architecture== | ==Architecture== | ||
The SHARC is a [[Harvard architecture]] [[Word addressing|word-addressed]] [[VLIW]] processor; it knows nothing of 8-bit or 16-bit values since each address is used to point to a whole 32-bit word, not just an [[Octet (computing)|octet]]. It is thus neither little-endian nor big-endian, though a compiler may use either convention if it implements 64-bit data and/or some way to pack multiple 8-bit or 16-bit values into a single 32-bit word. In C, the characters are 32-bit as they are the smallest addressable words | The SHARC is a [[Harvard architecture]] [[Word addressing|word-addressed]] [[VLIW]] processor; it knows nothing of 8-bit or 16-bit values since each address is used to point to a whole 32-bit word, not just an [[Octet (computing)|octet]]. It is thus neither little-endian nor big-endian, though a compiler may use either convention if it implements 64-bit data and/or some way to pack multiple 8-bit or 16-bit values into a single 32-bit word. In C, the characters are 32-bit as they are the smallest addressable words in the architecture. | ||
The word size is [[48-bit]] for instructions, [[32-bit]] for integers and normal floating-point, and 40-bit for extended floating-point. Code and data are normally fetched from on-chip memory, which the user must split into regions of different word sizes as desired. Small data types may be stored in wider memory, simply wasting the extra space. A system that does not use 40-bit extended floating-point might divide the on-chip memory into two sections, a 48-bit one for code and a 32-bit one for everything else. Most memory-related CPU instructions can not access all the bits of 48-bit memory, but a special 48-bit register is provided for this purpose. The special 48-bit register may be accessed as a pair of smaller registers, allowing movement to and from the normal registers. | The word size is [[48-bit]] for instructions, [[32-bit]] for integers and normal floating-point, and 40-bit for extended floating-point. Code and data are normally fetched from on-chip memory, which the user must split into regions of different word sizes as desired. Small data types may be stored in wider memory, simply wasting the extra space. A system that does not use 40-bit extended floating-point might divide the on-chip memory into two sections, a 48-bit one for code and a 32-bit one for everything else. Most memory-related CPU instructions can not access all the bits of 48-bit memory, but a special 48-bit register is provided for this purpose. The special 48-bit register may be accessed as a pair of smaller registers, allowing movement to and from the normal registers. | ||
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The SHARC has two full sets of general-purpose registers. Code can instantly switch between them, allowing for fast context switches between an application and an [[Operating system|OS]] or between two threads. | The SHARC has two full sets of general-purpose registers. Code can instantly switch between them, allowing for fast context switches between an application and an [[Operating system|OS]] or between two threads. | ||
== Software support == | |||
Compilers: | |||
* Analog Devices CrossCore compiler (commercial)<ref>{{cite web |title=C/C++ Compiler Manual for SHARC ® Processors |url=https://www.analog.com/media/en/dsp-documentation/software-manuals/cces_1-1-0_sharc_comp_man_rev_1-2.pdf}}</ref> | |||
* Analog Devices Visual DSP++ (commercial)<ref>{{cite web |title=VisualDSP++ 5.1 . |url=https://www.analog.com/en/resources/evaluation-hardware-and-software/software/vdsp-bf-sh-ts.html |quote=VisualDSP++ for Blackfin, SHARC, and TigerSHARC processors is an easy-to-install and easy-to-use integrated software development and debugging environment (IDDE) that enables efficient management of projects from start to finish from within a single interface}}</ref> | |||
* Analog Devices g21k, a defunct fork of [[GNU Compiler Collection|GCC]] (GPLv2)<ref>{{cite web |title=Dockeen - DSP/GCC Information |url=https://gcc.gnu.org/legacy-ml/gcc-help/2002-04/msg00059.html |website=gcc.gnu.org}}</ref><ref>{{cite web |last1=Vakulenko |first1=Serge |title=sergev/g21k |url=https://github.com/sergev/g21k |date=19 June 2025}}</ref> | |||
==See also== | ==See also== | ||
*[[TigerSHARC]] | *[[TigerSHARC]] – parallel descendant from Analog Devices | ||
*[[Blackfin]] | *[[Blackfin]] – modern (2000–) replacement from Analog Devices | ||
*[[Qualcomm Hexagon]] | *[[Qualcomm Hexagon]] – competitor | ||
*[[Texas Instruments TMS320]] | *[[Texas Instruments TMS320]] – competitor | ||
*[[CEVA, Inc.]] | *[[CEVA, Inc.]] – competitor | ||
==References== | |||
{{Reflist}} | |||
==External links== | ==External links== | ||
Latest revision as of 07:32, 6 December 2025
Template:Short description Script error: No such module "Distinguish". Script error: No such module "Unsubst". Template:Infobox CPU architecture The Super Harvard Architecture Single-Chip Computer (SHARC) is a high performance floating-point and fixed-point DSP from Analog Devices. SHARC is used in a variety of signal processing applications ranging from audio processing, to single-CPU guided artillery shells to 1000-CPU over-the-horizon radar processing computers. The original design dates to about January 1994.
SHARC processors are typically intended to have a good number of serial links to other SHARC processors nearby, to be used as a low-cost alternative to SMP.
Architecture
The SHARC is a Harvard architecture word-addressed VLIW processor; it knows nothing of 8-bit or 16-bit values since each address is used to point to a whole 32-bit word, not just an octet. It is thus neither little-endian nor big-endian, though a compiler may use either convention if it implements 64-bit data and/or some way to pack multiple 8-bit or 16-bit values into a single 32-bit word. In C, the characters are 32-bit as they are the smallest addressable words in the architecture.
The word size is 48-bit for instructions, 32-bit for integers and normal floating-point, and 40-bit for extended floating-point. Code and data are normally fetched from on-chip memory, which the user must split into regions of different word sizes as desired. Small data types may be stored in wider memory, simply wasting the extra space. A system that does not use 40-bit extended floating-point might divide the on-chip memory into two sections, a 48-bit one for code and a 32-bit one for everything else. Most memory-related CPU instructions can not access all the bits of 48-bit memory, but a special 48-bit register is provided for this purpose. The special 48-bit register may be accessed as a pair of smaller registers, allowing movement to and from the normal registers.
Off-chip memory can be used with the SHARC. This memory can only be configured for one single size. If the off-chip memory is configured as 32-bit words to avoid waste, then only the on-chip memory may be used for code execution and extended floating-point. Operating systems may use overlays to work around this problem, transferring 48-bit data to on-chip memory as needed for execution. A DMA engine is provided for this. True paging is impossible without an external MMU.
The SHARC has a 32-bit word-addressed address space. Depending on word size this is 16 GB, 20 GB, or 24 GB (using the common definition of an 8-bit "byte").
SHARC instructions may contain a 32-bit immediate operand. Instructions without this operand are generally able to perform two or more operations simultaneously. Many instructions are conditional, and may be preceded with "if condition " in the assembly language. There are a number of condition choices, similar to the choices provided by the x86 flags register.
There are two delay slots. After a jump, two instructions following the jump will normally be executed.
The SHARC processor has built-in support for loop control. Up to 6 levels may be used, avoiding the need for normal branching instructions and the normal bookkeeping related to loop exit.
The SHARC has two full sets of general-purpose registers. Code can instantly switch between them, allowing for fast context switches between an application and an OS or between two threads.
Software support
Compilers:
- Analog Devices CrossCore compiler (commercial)[1]
- Analog Devices Visual DSP++ (commercial)[2]
- Analog Devices g21k, a defunct fork of GCC (GPLv2)[3][4]
See also
- TigerSHARC – parallel descendant from Analog Devices
- Blackfin – modern (2000–) replacement from Analog Devices
- Qualcomm Hexagon – competitor
- Texas Instruments TMS320 – competitor
- CEVA, Inc. – competitor
References
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