Intel MCS-48: Difference between revisions

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imported>Stepho-wrs
Restored piped links. Short acronyms have a tendency to be replaced with redirects to completely different articles in completely different fields.
 
imported>ToaneeM
Undid revision 1322683358 by RastaKins (talk) Removed another unproposed/undiscussed and unbeneficial code lump. Reinstated original article before change. Have repeatedly asked for discussion (and have started one) but Rastkins keeps edit warring. (Do not revoke this edit. Do not edit war. Again, please first propose and discuss any changes on Talk page and reach agreement.)
 
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{| class="infobox" style="font-size:88%;width:21em;"
{| class="infobox" style="font-size:88%;width:21em;"
|-
|-
|+ Intel 8048 registers
|+ Intel 8048 registers<ref name="MCS-48 UM"/>
|-
|-
|
|
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| style="text-align:center;" colspan="10"| PC
| style="text-align:center;" colspan="10"| PC
| style="background:white; color:black;"| '''P'''rogram&nbsp;'''C'''ounter
| style="background:white; color:black;"| '''P'''rogram&nbsp;'''C'''ounter
|-
|colspan="17" | '''Timer/Counter'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="2" | &nbsp;
| style="text-align:center;" colspan="8"| T
| style="width:auto; background:white; color:black;"| '''T'''imer
|-
|-
|colspan="17" | '''Program Status Word'''
|colspan="17" | '''Program Status Word'''
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| style="text-align:center;"| [[Carry flag|CY]]
| style="text-align:center;"| [[Carry flag|CY]]
| style="text-align:center;"| [[Half-carry flag|AC]]
| style="text-align:center;"| [[Half-carry flag|AC]]
| style="text-align:center;"| FO
| style="text-align:center;"| F0
| style="text-align:center;"| BS
| style="text-align:center;"| BS
| style="text-align:center;"| 1
| style="text-align:center;"| 1
| style="text-align:center;" colspan="3"| Stack
| style="text-align:center;" colspan="3"| [[Stack register|Stack]]
|-
|colspan="17" | '''Flags'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6" | &nbsp;
| colspan="2"; style="text-align:center;"| DBF
| style="text-align:center;"| F1
| style="text-align:center;"| [[Interrupt flag|I]]
|-
|-
|colspan="20" | Note: All other programmer-visible registers and stack are allocated in RAM.
|colspan="20" | Note: All other programmer-visible registers and stack are allocated in RAM.
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The '''MCS-48''' [[microcontroller]] series, [[Intel]]'s first microcontroller, was originally released in 1976. Its first members were '''8048''', '''8035''' and '''8748'''. The 8048<ref name= computerHistory >{{cite conference |first1=David |last1=Laws |first2=Henry |last2=Blume Jr. |first3=John |last3=Ekiss |first4=Yung |last4=Feng |first5=Barbara |last5=Kline |first6=Howard |last6=Raphael |first7=David |last7=Stamm |url=http://archive.computerhistory.org/resources/access/text/2013/05/102658328-05-01-acc.pdf |date=2008-07-30 |archive-url=https://web.archive.org/web/20141227131405/http://archive.computerhistory.org/resources/access/text/2013/05/102658328-05-01-acc.pdf |archive-date=2014-12-27 |title=Oral History Panel on the Development and Promotion of the Intel 8048 Microcontroller}}</ref> is arguably the most prominent member of the family. Initially, this family was produced using [[NMOS logic|NMOS]] (n-type [[metal–oxide–semiconductor]]) technology. In the early 1980s, it became available in [[CMOS]] technology. It was manufactured into the 1990s to support older designs that still used it.
The '''MCS-48''' [[microcontroller]] series, [[Intel]]'s first microcontroller, was originally released in 1976. Its first members were '''8048''', '''8035''' and '''8748'''. The 8048<ref name= computerHistory >{{cite conference |first1=David |last1=Laws |first2=Henry |last2=Blume Jr. |first3=John |last3=Ekiss |first4=Yung |last4=Feng |first5=Barbara |last5=Kline |first6=Howard |last6=Raphael |first7=David |last7=Stamm |url=http://archive.computerhistory.org/resources/access/text/2013/05/102658328-05-01-acc.pdf |date=2008-07-30 |archive-url=https://web.archive.org/web/20141227131405/http://archive.computerhistory.org/resources/access/text/2013/05/102658328-05-01-acc.pdf |archive-date=2014-12-27 |title=Oral History Panel on the Development and Promotion of the Intel 8048 Microcontroller}}</ref> is arguably the most prominent member of the family. Initially, this family was produced using [[NMOS logic|NMOS]] (n-type [[metal–oxide–semiconductor]]) technology. In the early 1980s, it became available in [[CMOS]] technology. It was manufactured into the 1990s to support older designs that still used it.


The MCS-48 series has a [[modified Harvard architecture]], with internal or external program [[read-only memory|ROM]] and 64 to 256 bytes of internal (on-chip) [[random-access memory|RAM]]. The [[input/output|I/O]] is mapped into its own [[address space]], separate from programs and data.
The MCS-48 series has a [[modified Harvard architecture]], with internal or external program [[ROM]] and 64 to 256 bytes of internal (on-chip) [[RAM]]. The [[I/O]] is mapped into its own [[address space]], separate from programs and data.


Though the MCS-48 series was eventually replaced by the very successful [[Intel MCS-51|MCS-51]] series, it remained quite popular even by the year 2000 due to its low cost, wide availability, memory-efficient one-byte instruction set, and mature development tools. Because of this, it is used in high-volume, cost-sensitive consumer electronics devices such as TV remotes, computer keyboards, and toys.
Though the MCS-48 series was eventually replaced by the very successful [[MCS-51]] series, it remained quite popular even by the year 2000 due to its low cost, wide availability, memory-efficient one-byte instruction set, and mature development tools. Because of this, it is used in high-volume, cost-sensitive consumer electronics devices such as TV remotes, computer keyboards, and toys.


== Variants ==
== Variants ==
The '''8049''' has 2&nbsp;KB of masked [[read-only memory|ROM]] (the 8748 and 8749 had [[EPROM]]) that can be replaced with a 4&nbsp;KB external ROM, as well as 128&nbsp;[[byte]]s of [[random-access memory|RAM]] and 27&nbsp;[[input/output|I/O]] ports.{{sfn|Intel Corporation|1978}} The microcontroller's [[Electronic oscillator|oscillator]] block divides the clock input frequency by three and then further divides the result into five machine states. Using the 11&nbsp;[[megahertz|MHz]] maximum crystal frequency will produce 0.73&nbsp;[[Instructions per second#Millions of instructions per second (MIPS)|MIPS]] of single-cycle [[instruction set architecture|instruction]]s. Some 70% of instructions are single byte and single cycle ones, but 30% need two cycles or two bytes, so its typical performance would be closer to 0.5&nbsp;MIPS.
The '''8049''' has 2&nbsp;KB of masked [[ROM]] (the 8748 and 8749 had [[EPROM]]) that can be replaced with a 4&nbsp;KB external ROM, as well as 128&nbsp;[[byte]]s of [[RAM]] and 27&nbsp;[[I/O]] ports.{{sfn|Intel Corporation|1978}} The microcontroller's [[Electronic oscillator|oscillator]] block divides the clock input frequency by three and then further divides the result into five machine states. Using the 11&nbsp;[[MHz]] maximum crystal frequency will produce 0.73&nbsp;[[Instructions per second#Millions of instructions per second (MIPS)|MIPS]] of single-cycle [[instruction set architecture|instruction]]s. Some 70% of instructions are single byte and single cycle ones, but 30% need two cycles or two bytes, so its typical performance would be closer to 0.5&nbsp;MIPS.


{| class="wikitable"
{| class="wikitable"
|+Microcontroller{{fact|date=November 2022}}
|+Microcontroller<ref name="MCS-48 UM"/>
! Device !! Internal           !! Memory     !! Remarks
! Device !! Program memory           !! Data memory     !! Remarks
|-
|-
| 8020  || 1K × 8 ROM        || 64 × 8 RAM  || subset of 8048, 20 pins, only 13 I/O lines
| 8020  || 1K × 8 ROM        || 64 × 8 RAM  || subset of 8048, 20 pins, only 13 I/O lines
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{| class="wikitable"
{| class="wikitable"
|+Universal Peripheral Interface
|+Universal Peripheral Interface
! Device !! Internal           !! Memory     !! Remarks
! Device !! Program memory           !! Data memory     !! Remarks
|-
|-
| 8041    || 1K × 8 ROM        || 64 × 8 RAM  || Universal Peripheral Interface (UPI)
| 8041    || 1K × 8 ROM        || 64 × 8 RAM  || Universal Peripheral Interface (UPI)
Line 113: Line 126:


== Uses ==
== Uses ==
The MCS-48 series was commonly used in computer and terminal keyboards, converting key presses into protocols that can be understood by digital circuits. This also allows the possibility of serial communication, reducing the amount of conductors needed in cables on external keyboards. Microprocessors had been used in keyboards since at least 1972, simplifying earlier discrete designs. The 8048 has been used in this application since its introduction in 1978.{{cn|date=March 2023}}
The MCS-48 series was commonly used in computer and terminal keyboards, converting key presses into protocols that can be understood by digital circuits. This also allows the possibility of serial communication, reducing the number of conductors needed in cables on external keyboards. Microprocessors had been used in keyboards since at least 1972, simplifying earlier discrete designs. The 8048 has been used in this application since its introduction in 1978.{{cn|date=March 2023}}


The Tandy/Radio Shack [[TRS-80 Model II]], released in 1979, used the 8021 in its keyboard.<ref>{{cite book |title=TRS-80 Model II Technical Reference Manual |publisher=Radio Shack |page=135}}</ref> The 8021 processor scans the key matrix, converts switch closures to an 8-bit code and then transmits that code serially to the keyboard interface on the main system. It will also accept commands to turn indicator LEDs on or off. The 8021 was also used in the keyboards for the TRS-80 Model 12, 12B, 16, 16B and the Tandy 6000/6000HD.<ref>{{cite book |title=Tandy 6000/6000HD Service Manual |date=1985 |publisher=Tandy/Radio Shack |page=213}}</ref>
The Tandy/Radio Shack [[TRS-80 Model II]], released in 1979, used the 8021 in its keyboard.<ref>{{cite book |title=TRS-80 Model II Technical Reference Manual |publisher=Radio Shack |page=135}}</ref> The 8021 processor scans the key matrix, converts switch closures to an 8-bit code and then transmits that code serially to the keyboard interface on the main system. It will also accept commands to turn indicator LEDs on or off. The 8021 was also used in the keyboards for the TRS-80 Model 12, 12B, 16, 16B and the Tandy 6000/6000HD.<ref>{{cite book |title=Tandy 6000/6000HD Service Manual |date=1985 |publisher=Tandy/Radio Shack |page=213}}</ref>


The original [[IBM PC keyboard]] used an 8048 as its internal [[microcontroller]].<ref>{{Citation |title=Technical Reference: Personal Computer |series=Personal Computer Hardware Reference Library |chapter=Section 4: Keyboard |publisher=[[IBM]] |date=April 1984 |edition=Revised}}</ref> The [[IBM Personal Computer/AT|PC AT]] replaced the PC's [[Intel 8255]] peripheral interface chip at I/O port addresses {{mono|[[hexadecimal|0x]]60–63}} with an 8042 accessible through port addresses {{mono|0x60}} and {{mono|0x64}}.<ref>{{Citation |title=Technical Reference: Personal Computer AT |series=Personal Computer Hardware Reference Library |chapter=Section 1: System Board |publisher=IBM |date=September 1985}}</ref> As well as managing the keyboard interface, the 8042 controlled the [[A20 line]] gating function for the AT's [[Intel 80286]] CPU and could be commanded by software to reset the 80286 (unlike the [[Intel 80386|80386]] and later processors, the 80286 had no way of switching from [[protected mode]] back to [[real mode]] except by being reset). Later PC compatibles integrate the 8042's functions into their [[super I/O]] devices.
The original [[IBM PC keyboard]] and the keyboard for its precursor the [[IBM System/23 Datamaster]] used an 8048 as its internal [[microcontroller]].<ref>{{Citation |title=Technical Reference: Personal Computer |series=Personal Computer Hardware Reference Library |chapter=Section 4: Keyboard |publisher=[[IBM]] |date=April 1984 |edition=Revised}}</ref> The [[PC AT]] replaced the PC's [[Intel 8255]] peripheral interface chip at I/O port addresses {{mono|[[hexadecimal|0x]]60–63}} with an 8042 accessible through port addresses {{mono|0x60}} and {{mono|0x64}}.<ref>{{Citation |title=Technical Reference: Personal Computer AT |series=Personal Computer Hardware Reference Library |chapter=Section 1: System Board |publisher=IBM |date=September 1985}}</ref> As well as managing the keyboard interface, the 8042 controlled the [[A20 line]] gating function for the AT's [[Intel 80286]] CPU and could be commanded by software to reset the 80286 (unlike the [[80386]] and later processors, the 80286 had no way of switching from [[protected mode]] back to [[real mode]] except by being reset). Later PC compatibles integrate the 8042's functions into their [[super I/O]] devices.


The 8048 was used in the [[Magnavox Odyssey²]] [[video game console]], the [[Korg Trident]] series,<ref>{{Cite web|title=Korg Trident Service Manual|url=http://www.synthfool.com/docs/Korg/Korg_Trident_Service_manual/ |page=4 |publisher=Korg |via=Synthfool |access-date=10 February 2018}}</ref> and the [[Korg Poly-61]],<ref>{{cite web|title=Korg Poly-61 Service Manual|url=http://fa.utfs.org/diy/korgpoly61/Korg_Poly-61_ServiceManual.pdf|access-date=2013-03-07|archive-date=2010-06-02|archive-url=https://web.archive.org/web/20100602041214/http://fa.utfs.org/diy/korgpoly61/Korg_Poly-61_ServiceManual.pdf|url-status=dead}}</ref> [[Roland Jupiter-4]] and [[Roland ProMars]]<ref name="SOS11-04">{{cite web|title=The History Of Roland, Part 1: 1930–1978|url=http://www.soundonsound.com/sos/nov04/articles/roland.htm|work=The History Of Roland|publisher=Sound On Sound Magazine|access-date=29 November 2010|author=Gordon Reid|date=November 2004}}</ref> [[analog synthesizer]]s. The [[Sinclair QL]] used the closely related Intel 8049 to manage its keyboard, joystick ports, RS-232 inputs and audio. The ROM-less 8035 variant was used in [[Nintendo]]'s arcade game ''[[Donkey Kong (arcade game)|Donkey Kong]]'' to generate the background music.
The 8048 was used in the [[Magnavox Odyssey²]] [[video game console]], the [[Korg Trident]] series,<ref>{{Cite web|title=Korg Trident Service Manual|url=http://www.synthfool.com/docs/Korg/Korg_Trident_Service_manual/ |page=4 |publisher=Korg |via=Synthfool |access-date=10 February 2018}}</ref> and the [[Korg Poly-61]],<ref>{{cite web|title=Korg Poly-61 Service Manual|url=http://fa.utfs.org/diy/korgpoly61/Korg_Poly-61_ServiceManual.pdf|access-date=2013-03-07|archive-date=2010-06-02|archive-url=https://web.archive.org/web/20100602041214/http://fa.utfs.org/diy/korgpoly61/Korg_Poly-61_ServiceManual.pdf|url-status=dead}}</ref> [[Roland Jupiter-4]] and [[Roland ProMars]]<ref name="SOS11-04">{{cite web|title=The History Of Roland, Part 1: 1930–1978|url=http://www.soundonsound.com/sos/nov04/articles/roland.htm|work=The History Of Roland|publisher=Sound On Sound Magazine|access-date=29 November 2010|author=Gordon Reid|date=November 2004}}</ref> [[analog synthesizer]]s. The [[Sinclair QL]] used the closely related Intel 8049 to manage its keyboard, joystick ports, RS-232 inputs and audio. The ROM-less 8035 variant was used in [[Nintendo]]'s arcade game ''[[Donkey Kong (arcade game)|Donkey Kong]]'' to generate the background music and some of the game's sound effects.
 
==Instruction set==
All MCS-48 instructions are one or two bytes long with 70% of the instructions being one byte. The MCS-48 can address 4096 bytes of program memory, 256 bytes of RAM, and eight port I/O addresses. Most arithmetic and logical operations use the accumulator as a parameter and destination. Eight memory locations are mapped as registers so they can be addressed by a 3-bit field embedded in many instructions. Two of those registers can be used as memory pointers. Conditional branches can only access the current 256-byte page. JMP and CALL can directly access 2048 locations. To access the entire 4096 byte program space, a clunky select memory bank instruction must be used. The RET instruction can, however, return anywhere in the address space. Interrupts are well supported with alternate registers for quick context switches and the ability to restore the state of the flags with the RETR instruction. All instructions execute in one or two machine cycles. Each machine cycle takes 15 external clocks.<ref name="MCS-48 UM">{{cite book |title=MCS-48 Family of Single Chip Microcomputers User's Manual |date=September 1980 |publisher=Intel |edition=AFN·01300A-1 |url=http://www.bitsavers.org/components/intel/8048/1980_MCS-48_Users_Manual.pdf |access-date=15 November 2025}}</ref>
 
{|class="wikitable mw-collapsible" style="text-align:center"
!colspan=8| Opcode ||rowspan=2| Operand ||rowspan=2| Mnemonic || rowspan=2| Cycles ||rowspan=2| Description
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || &mdash; ||align=left| NOP || 1 ||align=left| No operation
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || &mdash; ||align=left| OUTL BUS,A || 2 ||align=left| Bus latch ← A
|-
|colspan=4|ALUI|| 0 || 0 || 1 || 1 || data ||align=left| ADD ADDC MOV ORL ANL XRL || 2 ||align=left| A ← A ALU #
|-
| colspan=3|addhi|| 0 || 0 || 1 || 0 || 0 || addlo ||align=left| JMP add || 2 ||align=left| PC ← DBF:addhi:addlo
|-
| 0 || 0 || 0 || I || 0 || 1 || 0 || 1 || &mdash; ||align=left| EN/DIS I || 1 ||align=left| I ← 0 (EN) or I ← 1 (DIS)
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || &mdash; ||align=left| DEC A || 1 ||align=left| A ← A - 1
|-
| 0 || 0 || 0 || 0 || 1 || 0 || 0 || 0 || &mdash;  ||align=left| INS A,BUS || 2 ||align=left| A ← bus
|-
| 0 || 0 || 0 || 0 || 1 || 0 ||colspan=2|PP|| &mdash;  ||align=left| IN A,Pp || 2 ||align=left| A ← Port(p) (Ports 1-2)
|-
| 0 || 0 || 0 || 0 || 1 ||colspan=3|PP|| &mdash;  ||align=left| MOVD A,Pp || 2 ||align=left| A<sub>0-3</sub> ← 8243 Port(p); A<sub>4-7</sub> ← 0 (Ports 4-7)
|-
|colspan=4|ALU|| 0 || 0 || 0 || R || &mdash; ||align=left| INC XCH ORL ANL ADD ADDC<br>MOVaA XRL MOVAa || 1 ||align=left| dest ← dest ALU @Rr (@R0, @R1 only; no DEC)
|-
|colspan=4|ALU|| 1 ||colspan=3|RRR|| &mdash; ||align=left| INC XCH ORL ANL ADD ADDC<br>MOVaA DEC XRL MOVAa || 1 ||align=left| dest ← dest ALU Rr
|-
|colspan=3|BIT|| 1 || 0 || 0 || 1 || 0 || addr ||align=left| JBb addr || 2 ||align=left| If A ∧ (1 << b) then PC<sub>0-7</sub> ← addr
|-
| colspan=3|addhi|| 1 || 0 || 1 || 0 || 0 || addlo ||align=left| CALL add || 2 ||align=left| (SP) ← PSW<sub>4-7</sub>:PC; SP ← SP + 1; PC ← DBF:addhi:addlo
|-
| 0 || 0 || 0 || 1 || 0 || 1 || 1 || 0 || addr ||align=left| JTF addr || 2 ||align=left| If TF = 1 then PC<sub>0-7</sub> ← addr (timer flag set)
|-
| 0 || 0 || 0 || 1 || 0 || 1 || 1 || 1 || &mdash; ||align=left| INC A || 1 ||align=left| A ← A + 1
|-
| 0 || 0 || 1 || T || 0 || 1 || 0 || 1 || &mdash; ||align=left| EN/DIS TCNTI || 1 ||align=left| TCNTI ← 0 (EN) or TCNTI ← 1 (DIS) (timer/counter interrupt)
|-
| 0 || 0 || 1 || F || 0 || 1 || 1 || 0 || addr ||align=left| JNT0 JT0 addr || 2 ||align=left| If F = T0 then PC<sub>0-7</sub> ← addr (test input 0)
|-
| 0 || 0 || 1 || 0 || 0 || 1 || 1 || 1 || &mdash; ||align=left| CLR A || 1 ||align=left| A ← 0
|-
| 0 || 0 || 1 || 1 || 0 || 1 || 1 || 1 || &mdash; ||align=left| CPL A || 1 ||align=left| A ← ¬A
|-
| 0 || 0 || 1 || 1 || 1 || 0 ||colspan=2|PP|| &mdash;  ||align=left| OUTL Pp,A || 2 ||align=left| Port(p) ← A (Ports 1-2)
|-
| 0 || 0 || 1 || 1 || 1 ||colspan=3|PP|| &mdash;  ||align=left| MOVD Pp,A || 2 ||align=left| 8243 Port(p) ← A<sub>0-3</sub>  (Ports 4-7)
|-
| 0 || 1 || 0 || 0 || 0 || 0 || 1 || 0 || &mdash; ||align=left| MOV A,T || 1 ||align=left| A ← T (Move timer to A)
|-
| 0 || 1 || 0 || T || 0 || 1 || 0 || 1 || &mdash; ||align=left| STRT CNT/T || 1 ||align=left| If T = 0 start count else start timer
|-
|| 0 || 1 || 0 || F || 0 || 1 || 1 || 0 || addr ||align=left| JNT1 JT1 addr || 2 ||align=left| If F = T1 then PC<sub>0-7</sub> ← addr (test input 1)
|-
| 0 || 1 || 0 || 0 || 0 || 1 || 1 || 1 || &mdash; ||align=left| SWAP A || 1 ||align=left| A<sub>0-3</sub> ↔ A<sub>4-7</sub>
|-
| 0 || 1 || 0 || 1 || 0 || 1 || 1 || 1 || &mdash; ||align=left| DA A || 1 ||align=left| If A<sub>0-4</sub> > 9 OR AC = 1 then A ← A + 6;
 
then if A<sub>4-7</sub> > 9 OR C = 1 then A ← A + 0x60
|-
| 0 || 1 || 1 || 0 || 0 || 0 || 1 || 0 || &mdash; ||align=left| MOV T,A || 1 ||align=left| T ← A (Move A to timer)
|-
| 0 || 1 || 1 || 0 || 0 || 1 || 0 || 1 || &mdash; ||align=left| STOP TCNT || 1 ||align=left| Stop timer and count
|-
| 0 || 1 || 1 || 0 || 0 || 1 || 1 || 1 || &mdash; ||align=left| RRC A || 1 ||align=left|  C ← A<sub>0</sub>; A<sub>0-6</sub> ← A<sub>1-7</sub>; A<sub>7</sub> ← C
|-
| 0 || 1 || 1 || 1 || 0 || 1 || 0 || 1 || &mdash; ||align=left| ENT0 CLK || 1 ||align=left| Set T0 as a clock output
|-
| 0 || 1 || 1 || 1 || 0 || 1 || 1 || 0 || addr ||align=left| JF1 addr || 2 ||align=left| If F1 = 1 then PC<sub>0-7</sub> ← addr
|-
| 0 || 1 || 1 || 1 || 0 || 1 || 1 || 1 || &mdash; ||align=left| RR A || 1 ||align=left| A<sub>0-6</sub> ← A<sub>1-7</sub>; A<sub>7</sub> ← A<sub>0</sub>
|-
| 1 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || &mdash; ||align=left| RET || 2 ||align=left| SP ← SP - 1; PC ← (SP)
|-
| 1 || 0 || N || 0|| 0 || 1 || 0 || 1 || &mdash; ||align=left| CLR Fn || 1 ||align=left| Fn ← 0
|-
| 1 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || addr ||align=left| JNI addr || 2 ||align=left| If I input = 0 then PC<sub>0-7</sub> ← addr (test interrupt input low)
|-
| 1 || 0 || 0 || 0 || 1 || 0 || 0 || 0 || data ||align=left| ORL BUS,# || 2 ||align=left| A ← bus ∨ #
|-
| 1 || 0 || 0 || 0 || 1 || 0 ||colspan=2|PP|| data ||align=left| ORL Pp,# || 2 ||align=left| A ← Port(p) ∨ #  (Ports 1-2)
|-
| 1 || 0 || 0 || 0 || 1 ||colspan=3|PP|| &mdash;  ||align=left| ORLD Pp,A || 2 ||align=left| 8243 Port(p) ← 8243 Port(p) ∨ A<sub>0-3</sub>  (Ports 4-7)
|-
| 1 || 0 || 0 || 1 || 0 || 0 || 1 || 1 || &mdash; ||align=left| RETR || 2 ||align=left| SP ← SP - 1; PC ← (SP); PSW<sub>4-7</sub> ← (SP)
|-
| 1 || 0 || N || 1|| 0 || 1 || 0 || 1 || &mdash; ||align=left| CPL Fn || 1 ||align=left| Fn ← ¬Fn
|-
| 1 || 0 || 0 || 1|| 0 || 1 || 1 || 1 || &mdash; ||align=left| CLR C || 1 ||align=left| C ← 0
|-
| 1 || 0 || 0 || 1 || 1 || 0 || 0 || 0 || data ||align=left| ANL BUS,# || 2 ||align=left| A ← bus ∧ #
|-
| 1 || 0 || 0 || 1 || 1 || 0 ||colspan=2|PP|| data  ||align=left| ANL Pp,# || 2 ||align=left| A ← Port(p) ∧ #  (Ports 1-2)
|-
| 1 || 0 || 0 || 1 || 1 ||colspan=3|PP|| &mdash;  ||align=left| ANLD Pp,A || 2 ||align=left| 8243 Port(p) ← 8243 Port(p) ∧ A<sub>0-3</sub> (Ports 4-7)
|-
| 1 || 0 || 1 || 0 || 0 || 0 || 1 || 1 || &mdash;  ||align=left| MOVP A,@A || 2 ||align=left| A ← ROM(PC<sub>8-11</sub>:A) (read program memory)
|-
| 1 || 0 || 1 || 0|| 0 || 1 || 1 || 1 || &mdash; ||align=left| CPL C || 1 ||align=left| C ← ¬C
|-
| 1 || 0 || 1 || 1 || 0 || 0 || 1 || 1 || &mdash;  ||align=left| JMPP @A || 2 ||align=left| PC<sub>0-7</sub> ← A (indirect JMP)
|-
| 1 || 0 || 1 || 1 || 0 || 1 || 1 || 0 || addr ||align=left| JF0 addr || 2 ||align=left| If F0 = 1 then PC<sub>0-7</sub> ← addr
|-
| 1 || 1 || 0 || N || 0 || 1 || 0 || 1 || &mdash; ||align=left| SEL RBn || 1 ||align=left| BS ← n (select register bank)
|-
| 1 || 1 || 0 || 0 || 0 || 1 || 1 || 0 || addr ||align=left| JZ addr || 2 ||align=left| If A = 0 then PC<sub>0-7</sub> ← addr
|-
| 1 || 1 || 0 || 0 || 0 || 1 || 1 || 1 || &mdash; ||align=left| MOV A,PSW || 1 ||align=left| A ← PSW
|-
| 1 || 1 || 0 || 1 || 0 || 1 || 1 || 1 || &mdash; ||align=left| MOV PSW,A || 1 ||align=left| PSW ← A
|-
| 1 || 1 || 1 || 0 || 0 || 0 || 1 || 1 || &mdash;  ||align=left| MOVP3 A,@A || 2 ||align=left| A ← ROM(0011:A) (read page 3 program memory)
|-
| 1 || 1 || 1 || N || 0 || 1 || 0 || 1 || &mdash; ||align=left| SEL MBn || 1 ||align=left| DBF ← n (select memory bank: PC<sub>11</sub>)
|-
| 1 || 1 || 1 || F || 0 || 1 || 1 || 0 || addr ||align=left| JNC JC addr || 2 ||align=left| If F = C then PC<sub>0-7</sub> ← addr
|-
| 1 || 1 || 1 || 0 || 0 || 1 || 1 || 1 || &mdash; ||align=left| RL A || 1 ||align=left| A<sub>1-7</sub> ← A<sub>0-6</sub>; A<sub>0</sub> ← A<sub>7</sub>
|-
| 1 || 1 || 1 || 0 || 1 ||colspan=3|RRR || addr ||align=left| DJNZ Rr,addr || 2 ||align=left| Rr ← Rr - 1; If Rr ≠ 0 then PC<sub>0-7</sub> ← addr
|-
| 1 || 1 || 1 || 1 || 0 || 1 || 1 || 1 || &mdash; ||align=left| RLC A || 1 ||align=left|  C ← A<sub>7</sub>; A<sub>1-7</sub> ← A<sub>0-6</sub>; A<sub>0</sub> ← C
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || Operand || Mnemonic || Cycles || Description
|-
!colspan=12|
|-
!colspan=4|RRR or R|| 3 || 2 || 1 || 0 ||colspan=2 | ALU||colspan=2| ALUI #immed
|-
|colspan=4| R0 @R0 || 0 || 0 || 0 || 0 || style="text-align: left;" colspan=2 | || style="text-align: left;" colspan=2|ADD A,# (A ← A + #)
|-
|colspan=4| R1 @R1 || 0 || 0 || 0 || 1|| style="text-align: left;" colspan=2 |INC arg (arg ← arg + 1) || style="text-align: left;" colspan=2|ADDC A,# (A ← A + # + C)
|-
|colspan=4| R2 || 0 || 0 || 1 || 0||style="text-align: left;"  colspan=2 |XCH A,arg (A ↔ arg) || style="text-align: left;" colspan=2|MOV R,# (R ← #)
|-
|colspan=4| R3 || 0 || 0 || 1 || 1|| style="text-align: left;" colspan=2 |
|-
|colspan=4| R4 || 0 || 1 || 0 || 0|| style="text-align: left;" colspan=2 |ORL A,arg (A ← A ∨ arg) || style="text-align: left;" colspan=2|ORL A,# (A ← A ∨ #)
|-
|colspan=4| R5 || 0 || 1 || 0 || 1|| style="text-align: left;" colspan=2 |ANL A,arg (A ← A ∧ arg) || style="text-align: left;" colspan=2|ANL A,# (A ← A ∧ #)
|-
|-
|colspan=4| R6 || 0 || 1 || 1 || 0|| style="text-align: left;" colspan=2 |ADD A,arg (A ← A + arg) || style="text-align: left;" colspan=2|
|-
|colspan=4| R7 || 0 || 1 || 1 || 1|| style="text-align: left;" colspan=2 |ADDC A,arg (A ← A + arg + C)|| style="text-align: left;" colspan=2|
|-
|colspan=4| || 1 || 0 || 1 || 0||style="text-align: left;"  colspan=2 |MOV arg,A (arg ← A) || style="text-align: left;" colspan=2|
|-
|colspan=4| || 1 || 1 || 0 || 0|| style="text-align: left;" colspan=2 |DEC arg (arg ← arg - 1) || style="text-align: left;" colspan=2|
|-
|colspan=4| || 1 || 1 || 0 || 1|| style="text-align: left;" colspan=2 |XRL A,arg (A ← A ⊻ arg) || style="text-align: left;" colspan=2| XRL A,# (A ← A ⊻ #)
|-
|colspan=4| || 1 || 1 || 1 || 1|| style="text-align: left;" colspan=2 |MOV A,arg (A ← arg)
|-
!colspan=4|RRR or R|| 3 || 2 || 1 || 0 ||colspan=2 | ALU||colspan=2|ALUI #immed
|}


== Derived microcontrollers ==
== Derived microcontrollers ==
Philips Semiconductors (now [[NXP Semiconductors|NXP]]) owned a license to produce this series and developed their MAB8400-family based on this architecture. These were the first microcontrollers with an integrated [[I²C]]-interface and were used in the first [[Philips]] ([[Magnavox]] in the US) [[CD player|Compact Disc players]] (e.g. the CD-100).<ref>[http://arquivo.pt/wayback/20160515111736/http://www.datasheetarchive.com/dl/Datasheets-110/DSAP005622.pdf Datasheet (pdf)] Philips MAB8400-Family</ref>
Philips Semiconductors (now [[NXP]]) owned a license to produce this series and developed their MAB8400-family based on this architecture. These were the first microcontrollers with an integrated [[I²C]]-interface and were used in the first [[Philips]] ([[Magnavox]] in the US) [[CD player|Compact Disc players]] (e.g. the CD-100).<ref>[http://arquivo.pt/wayback/20160515111736/http://www.datasheetarchive.com/dl/Datasheets-110/DSAP005622.pdf Datasheet (pdf)] Philips MAB8400-Family</ref>


<gallery mode="packed" heights="80px" caption="Intel MCS-48 [[second source]]s">
<gallery mode="packed" heights="80px" caption="Intel MCS-48 [[second source]]s">

Latest revision as of 15:53, 17 November 2025

Template:Short description

File:KL Intel P8048H.jpg
Intel 8048 microcontroller
File:KL Intel D8749.jpg
The 8749 with UV EPROM
File:Intel 8049 Microcontroller.jpg
An Intel 8049 microcontroller, as used in a HP3478A multimeter. This chip was manufactured in the second week of 1984.
File:EPROM-Microcontroller Intel 8749H (chip) - (1).jpg
Intel 8749 die
Intel 8048 registers[1]
09 08 07 06 05 04 03 02 01 00 (bit position)
Main registers
  A Accumulator
PC Program Counter
Timer/Counter
  T Timer
Program Status Word
  CY AC F0 BS 1 Stack
Flags
  DBF F1 I
Note: All other programmer-visible registers and stack are allocated in RAM.

The MCS-48 microcontroller series, Intel's first microcontroller, was originally released in 1976. Its first members were 8048, 8035 and 8748. The 8048[2] is arguably the most prominent member of the family. Initially, this family was produced using NMOS (n-type metal–oxide–semiconductor) technology. In the early 1980s, it became available in CMOS technology. It was manufactured into the 1990s to support older designs that still used it.

The MCS-48 series has a modified Harvard architecture, with internal or external program ROM and 64 to 256 bytes of internal (on-chip) RAM. The I/O is mapped into its own address space, separate from programs and data.

Though the MCS-48 series was eventually replaced by the very successful MCS-51 series, it remained quite popular even by the year 2000 due to its low cost, wide availability, memory-efficient one-byte instruction set, and mature development tools. Because of this, it is used in high-volume, cost-sensitive consumer electronics devices such as TV remotes, computer keyboards, and toys.

Variants

The 8049 has 2 KB of masked ROM (the 8748 and 8749 had EPROM) that can be replaced with a 4 KB external ROM, as well as 128 bytes of RAM and 27 I/O ports.Template:Sfn The microcontroller's oscillator block divides the clock input frequency by three and then further divides the result into five machine states. Using the 11 MHz maximum crystal frequency will produce 0.73 MIPS of single-cycle instructions. Some 70% of instructions are single byte and single cycle ones, but 30% need two cycles or two bytes, so its typical performance would be closer to 0.5 MIPS.

Microcontroller[1]
Device Program memory Data memory Remarks
8020 1K × 8 ROM 64 × 8 RAM subset of 8048, 20 pins, only 13 I/O lines
8021 1K × 8 ROM 64 × 8 RAM subset of 8048, 28 pins, 21 I/O lines
8022 2K × 8 ROM 64 × 8 RAM subset of 8048, A/D-converter
8035 none 64 × 8 RAM
8038 none 64 × 8 RAM
8039 none 128 × 8 RAM
8040 none 256 × 8 RAM
8048 1K × 8 ROM 64 × 8 RAM 27× I/O ports
8049 2K × 8 ROM 128 × 8 RAM 27× I/O ports
8050 4K x 8 ROM 256 × 8 RAM
8648 1K × 8 OTP EPROM 64 × 8 RAM Factory OTP EPROM
8748 1K × 8 EPROM[3] 64 × 8 RAM[3] 4K program memory expandable,[3] 2× 8-bit timers, 27× I/O ports
8749 2K × 8 EPROM 128 × 8 RAM 2× 8-bit timers, 27× I/O ports
87P50 ext. ROM socket 256 × 8 RAM Has piggy-back socket for 2758/2716/2732 EPROM
File:Intel P8242.jpg
Intel P8242 - keyboard controller with Phoenix firmware for AT-compatible computers
File:NS87P50D-6.jpg
National Semiconductor NS87P50D-6 – Second source for the 87P50 piggyback microcontroller
Universal Peripheral Interface
Device Program memory Data memory Remarks
8041 1K × 8 ROM 64 × 8 RAM Universal Peripheral Interface (UPI)
8041AH 1K × 8 ROM 128 × 8 RAM UPI
8741A 1K × 8 EPROM 64 × 8 RAM UPI, EPROM version of 8041
8741AH 1K × 8 OTP EPROM 128 × 8 RAM UPI, OTP EPROM version of 8041AH
8042AH 2K × 8 ROM 256 × 8 RAM UPI
8242 2K × 8 ROM 256 × 8 RAM UPI, preprogrammed with keyboard controller firmware[4]
8742 2K × 8 EPROM 128 × 8 RAM UPI, EPROM version
8742AH 2K × 8 OTP EPROM 256 × 8 RAM UPI, OTP EPROM version of 8042AH

Uses

The MCS-48 series was commonly used in computer and terminal keyboards, converting key presses into protocols that can be understood by digital circuits. This also allows the possibility of serial communication, reducing the number of conductors needed in cables on external keyboards. Microprocessors had been used in keyboards since at least 1972, simplifying earlier discrete designs. The 8048 has been used in this application since its introduction in 1978.Script error: No such module "Unsubst".

The Tandy/Radio Shack TRS-80 Model II, released in 1979, used the 8021 in its keyboard.[5] The 8021 processor scans the key matrix, converts switch closures to an 8-bit code and then transmits that code serially to the keyboard interface on the main system. It will also accept commands to turn indicator LEDs on or off. The 8021 was also used in the keyboards for the TRS-80 Model 12, 12B, 16, 16B and the Tandy 6000/6000HD.[6]

The original IBM PC keyboard and the keyboard for its precursor the IBM System/23 Datamaster used an 8048 as its internal microcontroller.[7] The PC AT replaced the PC's Intel 8255 peripheral interface chip at I/O port addresses Template:Mono with an 8042 accessible through port addresses Template:Mono and Template:Mono.[8] As well as managing the keyboard interface, the 8042 controlled the A20 line gating function for the AT's Intel 80286 CPU and could be commanded by software to reset the 80286 (unlike the 80386 and later processors, the 80286 had no way of switching from protected mode back to real mode except by being reset). Later PC compatibles integrate the 8042's functions into their super I/O devices.

The 8048 was used in the Magnavox Odyssey² video game console, the Korg Trident series,[9] and the Korg Poly-61,[10] Roland Jupiter-4 and Roland ProMars[11] analog synthesizers. The Sinclair QL used the closely related Intel 8049 to manage its keyboard, joystick ports, RS-232 inputs and audio. The ROM-less 8035 variant was used in Nintendo's arcade game Donkey Kong to generate the background music and some of the game's sound effects.

Instruction set

All MCS-48 instructions are one or two bytes long with 70% of the instructions being one byte. The MCS-48 can address 4096 bytes of program memory, 256 bytes of RAM, and eight port I/O addresses. Most arithmetic and logical operations use the accumulator as a parameter and destination. Eight memory locations are mapped as registers so they can be addressed by a 3-bit field embedded in many instructions. Two of those registers can be used as memory pointers. Conditional branches can only access the current 256-byte page. JMP and CALL can directly access 2048 locations. To access the entire 4096 byte program space, a clunky select memory bank instruction must be used. The RET instruction can, however, return anywhere in the address space. Interrupts are well supported with alternate registers for quick context switches and the ability to restore the state of the flags with the RETR instruction. All instructions execute in one or two machine cycles. Each machine cycle takes 15 external clocks.[1]

Opcode Operand Mnemonic Cycles Description
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 — NOP 1 No operation
0 0 0 0 0 0 1 0 — OUTL BUS,A 2 Bus latch ← A
ALUI 0 0 1 1 data ADD ADDC MOV ORL ANL XRL 2 A ← A ALU #
addhi 0 0 1 0 0 addlo JMP add 2 PC ← DBF:addhi:addlo
0 0 0 I 0 1 0 1 — EN/DIS I 1 I ← 0 (EN) or I ← 1 (DIS)
0 0 0 0 0 1 1 1 — DEC A 1 A ← A - 1
0 0 0 0 1 0 0 0 — INS A,BUS 2 A ← bus
0 0 0 0 1 0 PP — IN A,Pp 2 A ← Port(p) (Ports 1-2)
0 0 0 0 1 PP — MOVD A,Pp 2 A0-3 ← 8243 Port(p); A4-7 ← 0 (Ports 4-7)
ALU 0 0 0 R — INC XCH ORL ANL ADD ADDC
MOVaA XRL MOVAa		 1 dest ← dest ALU @Rr (@R0, @R1 only; no DEC)
ALU 1 RRR — INC XCH ORL ANL ADD ADDC
MOVaA DEC XRL MOVAa		 1 dest ← dest ALU Rr
BIT 1 0 0 1 0 addr JBb addr 2 If A ∧ (1 << b) then PC0-7 ← addr
addhi 1 0 1 0 0 addlo CALL add 2 (SP) ← PSW4-7:PC; SP ← SP + 1; PC ← DBF:addhi:addlo
0 0 0 1 0 1 1 0 addr JTF addr 2 If TF = 1 then PC0-7 ← addr (timer flag set)
0 0 0 1 0 1 1 1 — INC A 1 A ← A + 1
0 0 1 T 0 1 0 1 — EN/DIS TCNTI 1 TCNTI ← 0 (EN) or TCNTI ← 1 (DIS) (timer/counter interrupt)
0 0 1 F 0 1 1 0 addr JNT0 JT0 addr 2 If F = T0 then PC0-7 ← addr (test input 0)
0 0 1 0 0 1 1 1 — CLR A 1 A ← 0
0 0 1 1 0 1 1 1 — CPL A 1 A ← ¬A
0 0 1 1 1 0 PP — OUTL Pp,A 2 Port(p) ← A (Ports 1-2)
0 0 1 1 1 PP — MOVD Pp,A 2 8243 Port(p) ← A0-3 (Ports 4-7)
0 1 0 0 0 0 1 0 — MOV A,T 1 A ← T (Move timer to A)
0 1 0 T 0 1 0 1 — STRT CNT/T 1 If T = 0 start count else start timer
0 1 0 F 0 1 1 0 addr JNT1 JT1 addr 2 If F = T1 then PC0-7 ← addr (test input 1)
0 1 0 0 0 1 1 1 — SWAP A 1 A0-3 ↔ A4-7
0 1 0 1 0 1 1 1 — DA A 1 If A0-4 > 9 OR AC = 1 then A ← A + 6;

then if A4-7 > 9 OR C = 1 then A ← A + 0x60

0 1 1 0 0 0 1 0 — MOV T,A 1 T ← A (Move A to timer)
0 1 1 0 0 1 0 1 — STOP TCNT 1 Stop timer and count
0 1 1 0 0 1 1 1 — RRC A 1 C ← A0; A0-6 ← A1-7; A7 ← C
0 1 1 1 0 1 0 1 — ENT0 CLK 1 Set T0 as a clock output
0 1 1 1 0 1 1 0 addr JF1 addr 2 If F1 = 1 then PC0-7 ← addr
0 1 1 1 0 1 1 1 — RR A 1 A0-6 ← A1-7; A7 ← A0
1 0 0 0 0 0 1 1 — RET 2 SP ← SP - 1; PC ← (SP)
1 0 N 0 0 1 0 1 — CLR Fn 1 Fn ← 0
1 0 0 0 0 1 1 0 addr JNI addr 2 If I input = 0 then PC0-7 ← addr (test interrupt input low)
1 0 0 0 1 0 0 0 data ORL BUS,# 2 A ← bus ∨ #
1 0 0 0 1 0 PP data ORL Pp,# 2 A ← Port(p) ∨ # (Ports 1-2)
1 0 0 0 1 PP — ORLD Pp,A 2 8243 Port(p) ← 8243 Port(p) ∨ A0-3 (Ports 4-7)
1 0 0 1 0 0 1 1 — RETR 2 SP ← SP - 1; PC ← (SP); PSW4-7 ← (SP)
1 0 N 1 0 1 0 1 — CPL Fn 1 Fn ← ¬Fn
1 0 0 1 0 1 1 1 — CLR C 1 C ← 0
1 0 0 1 1 0 0 0 data ANL BUS,# 2 A ← bus ∧ #
1 0 0 1 1 0 PP data ANL Pp,# 2 A ← Port(p) ∧ # (Ports 1-2)
1 0 0 1 1 PP — ANLD Pp,A 2 8243 Port(p) ← 8243 Port(p) ∧ A0-3 (Ports 4-7)
1 0 1 0 0 0 1 1 — MOVP A,@A 2 A ← ROM(PC8-11:A) (read program memory)
1 0 1 0 0 1 1 1 — CPL C 1 C ← ¬C
1 0 1 1 0 0 1 1 — JMPP @A 2 PC0-7 ← A (indirect JMP)
1 0 1 1 0 1 1 0 addr JF0 addr 2 If F0 = 1 then PC0-7 ← addr
1 1 0 N 0 1 0 1 — SEL RBn 1 BS ← n (select register bank)
1 1 0 0 0 1 1 0 addr JZ addr 2 If A = 0 then PC0-7 ← addr
1 1 0 0 0 1 1 1 — MOV A,PSW 1 A ← PSW
1 1 0 1 0 1 1 1 — MOV PSW,A 1 PSW ← A
1 1 1 0 0 0 1 1 — MOVP3 A,@A 2 A ← ROM(0011:A) (read page 3 program memory)
1 1 1 N 0 1 0 1 — SEL MBn 1 DBF ← n (select memory bank: PC11)
1 1 1 F 0 1 1 0 addr JNC JC addr 2 If F = C then PC0-7 ← addr
1 1 1 0 0 1 1 1 — RL A 1 A1-7 ← A0-6; A0 ← A7
1 1 1 0 1 RRR addr DJNZ Rr,addr 2 Rr ← Rr - 1; If Rr ≠ 0 then PC0-7 ← addr
1 1 1 1 0 1 1 1 — RLC A 1 C ← A7; A1-7 ← A0-6; A0 ← C
7 6 5 4 3 2 1 0 Operand Mnemonic Cycles Description
RRR or R 3 2 1 0 ALU ALUI #immed
R0 @R0 0 0 0 0 ADD A,# (A ← A + #)
R1 @R1 0 0 0 1 INC arg (arg ← arg + 1) ADDC A,# (A ← A + # + C)
R2 0 0 1 0 XCH A,arg (A ↔ arg) MOV R,# (R ← #)
R3 0 0 1 1
R4 0 1 0 0 ORL A,arg (A ← A ∨ arg) ORL A,# (A ← A ∨ #)
R5 0 1 0 1 ANL A,arg (A ← A ∧ arg) ANL A,# (A ← A ∧ #)
R6 0 1 1 0 ADD A,arg (A ← A + arg)
R7 0 1 1 1 ADDC A,arg (A ← A + arg + C)
1 0 1 0 MOV arg,A (arg ← A)
1 1 0 0 DEC arg (arg ← arg - 1)
1 1 0 1 XRL A,arg (A ← A ⊻ arg) XRL A,# (A ← A ⊻ #)
1 1 1 1 MOV A,arg (A ← arg)
RRR or R 3 2 1 0 ALU ALUI #immed

Derived microcontrollers

Philips Semiconductors (now NXP) owned a license to produce this series and developed their MAB8400-family based on this architecture. These were the first microcontrollers with an integrated I²C-interface and were used in the first Philips (Magnavox in the US) Compact Disc players (e.g. the CD-100).[12]

See also

References

Template:Reflist

Bibliography

MCS-48
  • Script error: No such module "citation/CS1".
  • Script error: No such module "citation/CS1".
  • Script error: No such module "citation/CS1".
  • Script error: No such module "citation/CS1".
  • Script error: No such module "citation/CS1".
  • Script error: No such module "citation/CS1".
  • Script error: No such module "citation/CS1".
UPI-41
  • Script error: No such module "citation/CS1".
  • Script error: No such module "citation/CS1".
  • Script error: No such module "citation/CS1".

External links

Script error: No such module "Navbox". Template:8bitMCUs

Template:Authority control

  1. ↑ a b c Script error: No such module "citation/CS1".
  2. ↑ Script error: No such module "citation/CS1".
  3. ↑ a b c Script error: No such module "citation/CS1".
  4. ↑ Script error: No such module "citation/CS1".
  5. ↑ Script error: No such module "citation/CS1".
  6. ↑ Script error: No such module "citation/CS1".
  7. ↑ Script error: No such module "citation/CS1".
  8. ↑ Script error: No such module "citation/CS1".
  9. ↑ Script error: No such module "citation/CS1".
  10. ↑ Script error: No such module "citation/CS1".
  11. ↑ Script error: No such module "citation/CS1".
  12. ↑ Datasheet (pdf) Philips MAB8400-Family
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