imported>Xose.vazquez: /* History */

2025-12-06T13:30:08Z

History

← Previous revision		Revision as of 13:30, 6 December 2025
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	SDRAM is also available in [[Registered memory\|registered]] varieties, for systems that require greater scalability such as [[Server (computing)\|server]]s and [[workstations]].		SDRAM is also available in [[Registered memory\|registered]] varieties, for systems that require greater scalability such as [[Server (computing)\|server]]s and [[workstations]].

	Today, the world's largest manufacturers of SDRAM include [[Samsung Electronics]], [[~~SK Hynix~~]], [[~~Micron Technology~~]], and [[Nanya Technology]].		Today, the world's largest manufacturers of SDRAM include [[SK Hynix]], [[Samsung Electronics]], [[Micron Technology]], [[ChangXin Memory Technologies]], and [[Nanya Technology]].

	== Timing ==		== Timing ==
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	In March 2017, JEDEC announced a DDR5 standard is under development,<ref>{{cite press release \|title=JEDEC DDR5 & NVDIMM-P Standards Under Development \|url=https://www.jedec.org/news/pressreleases/jedec-ddr5-nvdimm-p-standards-under-development \|date=30 March 2017 \|publisher=[[JEDEC]]}}</ref> but provided no details except for the goals of doubling the bandwidth of DDR4, reducing power consumption, and publishing the standard in 2018. The standard was released on 14 July 2020.<ref name="anandtech-ddr5">{{cite web\|url=https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond\|archive-url=https://web.archive.org/web/20200714225042/https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond\|url-status=dead\|archive-date=July 14, 2020\|title=DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond\|last=Smith\|first=Ryan\|date=2020-07-14\|website=AnandTech\|access-date=2020-07-15}}</ref>		In March 2017, JEDEC announced a DDR5 standard is under development,<ref>{{cite press release \|title=JEDEC DDR5 & NVDIMM-P Standards Under Development \|url=https://www.jedec.org/news/pressreleases/jedec-ddr5-nvdimm-p-standards-under-development \|date=30 March 2017 \|publisher=[[JEDEC]]}}</ref> but provided no details except for the goals of doubling the bandwidth of DDR4, reducing power consumption, and publishing the standard in 2018. The standard was released on 14 July 2020.<ref name="anandtech-ddr5">{{cite web\|url=https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond\|archive-url=https://web.archive.org/web/20200714225042/https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond\|url-status=dead\|archive-date=July 14, 2020\|title=DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond\|last=Smith\|first=Ryan\|date=2020-07-14\|website=AnandTech\|access-date=2020-07-15}}</ref>

			=== DDR6 ===
			{{Main\|DDR6 SDRAM}}
			It is the future series of DDR SDRAM, and has a target of 2027. It will have a speed of 8,800–17,600 MT/s with four memory channels, and a bandwidth up to 134.4 GB/s.

	== Failed successors ==		== Failed successors ==
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	== High Bandwidth Memory (HBM) ==		== High Bandwidth Memory (HBM) ==
	{{Main\|High Bandwidth Memory}}		{{Main\|High Bandwidth Memory}}
			High Bandwidth Memory (HBM) is a high-performance RAM interface for [[three-dimensional integrated circuit\|3D-stacked]] SDRAM from [[Samsung Electronics\|Samsung]], [[Advanced Micro Devices\|AMD]] and [[SK Hynix]]. It is designed to be used in conjunction with high-performance graphics accelerators and network devices.<ref>[http://isscc.org/doc/2014/2014_Trends.pdf ISSCC 2014 Trends] {{webarchive\|url=https://web.archive.org/web/20150206093927/http://isscc.org/doc/2014/2014_Trends.pdf \|date=2015-02-06 }} page 118 "High-Bandwidth DRAM"</ref> The first HBM memory chip was produced by SK Hynix in 2013.<ref name="hynix2010s"/>
	[[High Bandwidth Memory]] (HBM) is a high-performance RAM interface for [[three-dimensional integrated circuit\|3D-stacked]] SDRAM from [[Samsung Electronics\|Samsung]], [[Advanced Micro Devices\|AMD]] and [[SK Hynix]]. It is designed to be used in conjunction with high-performance graphics accelerators and network devices.<ref>[http://isscc.org/doc/2014/2014_Trends.pdf ISSCC 2014 Trends] {{webarchive\|url=https://web.archive.org/web/20150206093927/http://isscc.org/doc/2014/2014_Trends.pdf \|date=2015-02-06 }} page 118 "High-Bandwidth DRAM"</ref> The first HBM memory chip was produced by SK Hynix in 2013.<ref name="hynix2010s"/>

	== Timeline ==		== Timeline ==
	{{See also\|Random-access memory#Timeline\|Flash memory#Timeline\|Transistor count#Memory}}{{Update section\|date=December 2023\|reason=Advances in DDR5 need to be included}}		{{See also\|Random-access memory#Timeline\|Flash memory#Timeline\|Transistor count#Memory}}{{Update section\|date=December 2023\|reason=Advances in DDR5/6/7 need to be included}}

	=== SDRAM ===		=== SDRAM ===
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	\|<ref name="Shilov2017" />		\|<ref name="Shilov2017" />
	\|}		\|}

	== See also ==		== See also ==
	* [[GDDR]] (graphics DDR) and its subtypes [[GDDR2]], [[GDDR3]], [[GDDR4]], [[GDDR5]], [[GDDR6]] and [[GDDR7]]		* [[GDDR]] (graphics DDR) and its subtypes [[GDDR2]], [[GDDR3]], [[GDDR4]], [[GDDR5]], [[GDDR6]] and [[GDDR7]]

imported>JJMC89 bot III: Moving :Category:SDRAM to :Category:Synchronous dynamic random-access memory per Wikipedia:Categories for discussion/Speedy

2025-11-16T09:21:42Z

Moving Category:SDRAM to Category:Synchronous dynamic random-access memory per Wikipedia:Categories for discussion/Speedy

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2025-06-01T11:22:41Z

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Synchronous dynamic random-access memory - Revision history

imported>Xose.vazquez: /* History */

imported>JJMC89 bot III: Moving :Category:SDRAM to :Category:Synchronous dynamic random-access memory per Wikipedia:Categories for discussion/Speedy

110.77.164.74: /* History */