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References: Shirriff_2015 cite includes a quote that in the source continues with a qualification. Added an ellipsis.

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{{Short description|Computer with a bit-serial architecture}}
{{Use dmy dates|date=April 2022|cs1-dates=y}}
{{Use list-defined references|date=June 2022}}
A '''serial computer''' is a computer typified by [[bit-serial architecture]]{{snd}} i.e., internally operating on one [[bit]] or [[numerical digit|digit]] for each [[clock signal|clock cycle]]. Machines with serial [[main storage]] devices such as acoustic or [[magnetostrictive]] [[Delay-line memory|delay lines]] and [[drum memory|rotating magnetic devices]] were usually serial computers.

Serial computers require much less hardware than their bit-parallel counterparts<ref name="Wilkes_1956"/> which exploit [[bit-level parallelism]] to do more computation per clock cycle. There are modern variants of the serial computer available as a [[soft microprocessor]]<ref name="Howe_2019"/> which can serve niche purposes where the size of the CPU is the main constraint.

The first computer that was not serial and used a [[parallel bus]] was the [[Whirlwind I|Whirlwind]] in 1951.

A serial computer is not necessarily the same as a computer with a [[1-bit architecture]], which is a subset of the serial computer class. 1-bit computer instructions operate on data consisting of single bits, whereas a serial computer can operate on ''N''-bit data widths, but does so a single bit at a time.

== Serial machines ==
* [[EDVAC]] (1949)
* [[BINAC]] (1949)
* [[SEAC (computer)|SEAC]] (1950)
* [[UNIVAC I]] (1951)
* [[Elliott Brothers (computer company)|Elliott Brothers]] [[Elliott 152]]{{Citation needed|date=April 2020}} (1954)
* [[Bendix G-15]] (1956)
* [[LGP-30]] (1956)<ref name="Miller_1966"/>
* [[Elliott Brothers (computer company)|Elliott Brothers]] [[Elliott 803]] (1958)
* [[ZEBRA (computer)|ZEBRA]]{{Citation needed|date=April 2020}} (1958)
* [[D-17B]] guidance computer (1962)
* [[PDP-8/S]]<ref name="DEC_1978"/> (1966)
* General Electric [[GE-PAC 4040]] [[process control computer]]
* [[F14 CADC]] (1970) {{snd}} transferred all data serially, but internally operated on many bits in parallel<ref name="Holt_1971"/>
* [[Kenbak-1]] (1971)
* [[Datapoint 2200]] (1971)<ref name="Shirriff_2015"/>
* [[HP-35]] (1972)<ref name="Stone_1975"/>
* Digit-serial [[HP Saturn]]-based calculators<ref name="Smith_2023"/> from the [[HP-71B]] (1974) to the [[HP 50g]] (2006–2015)
* [[National Semiconductor SC/MP]] (1976)
* [[Ferranti F100-L]] (1977) {{snd}} [[16-bit computing|16-bit]], but uses a bit-serial [[arithmetic logic unit]]

=== Massively parallel ===
Most of the early [[massively parallel (computing)|massive parallel processing]] machines were built out of individual serial processors, including:
* [[ICL Distributed Array Processor]] (1979)
* [[Goodyear MPP]] (1983)
* [[Connection Machine]] CM-1 (1985)
* Connection Machine CM-2 (1987)
* [[MasPar]] MP-1 (1990) {{snd}} 32-bit architecture, internally processed 4 bits at a time<ref name="Culver_2014"/>
* [[VIRAM1]] [[computational RAM]] (2003)

== See also ==
* [[1-bit computing]]
* [[BKM algorithm]]
* [[CORDIC algorithm]]

== References ==
{{reflist|refs=
<ref name="DEC_1978">{{cite book |title=Nineteen Fifty-Seven to the Present |date=1978 |orig-date=1972 |edition=6 |publisher=[[Digital Equipment Corporation]] |location=Maynard, Massachusetts, USA |page=7 |url=http://www.bitsavers.org/pdf/dec/_Books/DEC_1957_To_The_Present_1978.pdf |access-date=2021-02-06 |url-status=live |archive-url=https://web.archive.org/web/20220302210148/http://bitsavers.org/pdf/dec/_Books/DEC_1957_To_The_Present_1978.pdf |archive-date=2022-03-02}} (1+viii+87+3 pages)</ref>
<ref name="Miller_1966">{{cite book |title=Switching Theory – Volume 1: Combinational Circuits |author-first=Raymond E. |author-last=Miller |date=1965 |edition=Second printing, March 1966, of 1st |lccn=65-14249 |volume=1 |publisher=[[John Wiley & Sons, Inc.]] |pages=44–47}}</ref>
<ref name="Wilkes_1956">{{cite book |title=Automatic digital computers |author-last=Wilkes |author-first=Maurice Vincent |author-link=Maurice Vincent Wilkes |date=1956 |publisher=[[Methuen Publishing Ltd]] / [[John Wiley & Sons, Inc.]] |url=https://books.google.com/books?id=1vUrAAAAIAAJ |access-date=2012-06-06}}</ref>
<ref name="Holt_1971">{{cite book |title=This paper describes the architecture of the CPU and Memory for the Central Air Data Computer (CADC) System used in the Grumman/Navy F14A carrier-based fighter aircraft. |author-first=Raymond M. |author-last=Holt |author-link=Raymond M. Holt |date=1971 |id=AP1-26-97 |pages=5, 7 |url=http://firstmicroprocessor.com/documents/ap1-26-97.pdf |access-date=2017-11-04 |url-status=deviated |archive-url=https://web.archive.org/web/20171104082502/http://firstmicroprocessor.com/documents/ap1-26-97.pdf |archive-date=2017-11-04 |quote=[…] the processor was designed to transfer data serially throughout the entire system. […] The Parallel Multiplier Unit […] by means of a parallel algorithm […]}} (26 pages)</ref>
<ref name="Howe_2019">{{cite web |title=Bit-Serial: A bit-serial CPU written in VHDL, with a simulator written in C. |author-last=Howe |author-first=Richard James |date=2020 |orig-date=2019-06-27 |website=Github Project: A Bit Serial CPU |url=https://github.com/howerj/bit-serial |access-date=2019-06-28 |url-status=live |archive-url=https://web.archive.org/web/20220615231144/https://github.com/howerj/bit-serial |archive-date=2022-06-15}}
</ref>
<ref name="Shirriff_2015">{{cite web |title=The Texas Instruments TMX 1795: the (almost) first, forgotten microprocessor |author-first=Ken |author-last=Shirriff |date=May 2015 |url=https://www.righto.com/2015/05/the-texas-instruments-tmx-1795-first.html |access-date=2020-05-29 |url-status=live |archive-url=https://web.archive.org/web/20220615173952/https://www.righto.com/2015/05/the-texas-instruments-tmx-1795-first.html |archive-date=2022-06-15 |quote=Even operating one bit at a time as a serial computer, the Datapoint 2200 performed considerably faster than the 8008 chip...}}</ref>
<ref name="Culver_2014">{{cite web |title=MasPar: Massively Parallel Computers – 32 cores on a chip |date=2014-09-05 |author-first=John |author-last=Culver |url=http://www.cpushack.com/2014/09/05/maspar-massively-parallel-computers-32-cores-on-a-chip/ |access-date=2022-06-15 |url-status=live |archive-url=https://web.archive.org/web/20220615173816/https://www.cpushack.com/2014/09/05/maspar-massively-parallel-computers-32-cores-on-a-chip/ |archive-date=2022-06-15}}</ref>
<ref name="Smith_2023">{{cite web |title=HP-15C CE woes: 1 bug, 2 limitations, 3 questions |author-first=Eric L. "Brouhaha" |author-last=Smith |date=2023-08-09 |work=MoHPC - The Museum of HP Calculators |url=https://www.hpmuseum.org/forum/thread-20281.html |access-date=2023-09-24 |url-status=live |archive-url=https://web.archive.org/web/20230810144726/https://www.hpmuseum.org/forum/thread-20281.html |archive-date=2023-08-10}}</ref>
<ref name="Stone_1975">{{cite book |title=Introduction to Computer Architecture |author-first=Thomas M. |author-last=Whitney |author-link=Thomas Whitney (computing) |editor-first=Harold Stuart |editor-last=Stone |editor-link=Harold Stuart Stone |date=1975 |edition=1 |chapter=Part I. Basic Computer Architecture. / Chapter 3. Introduction to Calculators: / 3-5. Example Systems / The Hewlett Packard HP-35 |series=Computer Sciences Series |publisher=[[Science Research Associates, Inc.]] (SRA) |publication-place= |id=ark:/13960/t8pc40t3q. Order-Code 13-4005 |lccn=75-14016 |isbn=0-574-18405-8 |pages=118–135 [123–135] |chapter-url=https://archive.org/details/introductiontoco00ston/page/123/mode/2up?view=theater |access-date=2023-09-29 |quote-page=124 |quote=[…] The [[HP-35]] is a totally serial computer. The adder is a [[Binary-coded decimal|BCD]] serial type […] The serial structure means less integrated circuit area must be allocated to interconnection lines and gating functions and an interesting trade off occurs. A bit-serial, digit-serial architecture is inherently one fourth the speed of a bit-parallel digit-serial structure […] But the basic clock rate for a bit-serial structure can sometimes be increased since additional area can be allocated for larger integrated devices that are necessary for greater speed. In the HP-35, the execution time of the most complex functions is under one second, while the serial architecture permits an increased circuit complexity. […] Instructions in the HP-35 are transferred serially from the active read-only memory to the arithmetic and control circuits and to other ROMs if present. […]}}</ref>
}}

== Further reading ==
* {{cite book |title=Digit-Serial Computation |author-first1=Richard I. |author-last1=Hartley |author-link1=Richard I. Hartley |author-first2=Keshab K. |author-last2=Parhi |publisher=[[Kluwer Academic Publishers]] |date=1995 |edition=1 |isbn=0-7923-9573-5 |id=SECS316 |series=The Kluwer International Series in Engineering and Computer Science |publication-place=Norwell, Massachusetts, USA}} (xiv+306 pages)
* {{cite journal |title=A Systematic Approach for Design of Digit-Serial Signal Processing Architectures |author-last=Parhi |author-first=Keshab K. |journal=[[IEEE Transactions on Circuits and Systems]] |issn= |volume=38 |number=4 |date=April 1991 |pages=358–375 |doi=10.1109/31.75394}} (8 pages)

[[Category:Classes of computers]]
[[Category:Early computers|*Serial computers]]
[[Category:Serial computers| ]]

Serial computer - Revision history

imported>RastaKins: /* References */ Shirriff_2015 cite includes a quote that in the source continues with a qualification. Added an ellipsis.