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	<title>Serial Vector Format - Revision history</title>
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	<updated>2026-09-07T22:18:19Z</updated>
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		<title>imported&gt;KMaster888: added Category:Computer file formats using HotCat</title>
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		<updated>2024-12-30T20:28:21Z</updated>

		<summary type="html">&lt;p&gt;added &lt;a href=&quot;/wiki143/index.php?title=Category:Computer_file_formats&quot; title=&quot;Category:Computer file formats&quot;&gt;Category:Computer file formats&lt;/a&gt; using &lt;a href=&quot;/wiki143/index.php?title=WP:HC&amp;amp;action=edit&amp;amp;redlink=1&quot; class=&quot;new&quot; title=&quot;WP:HC (page does not exist)&quot;&gt;HotCat&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;&amp;#039;&amp;#039;&amp;#039;Serial Vector Format&amp;#039;&amp;#039;&amp;#039; (&amp;#039;&amp;#039;&amp;#039;SVF&amp;#039;&amp;#039;&amp;#039;) is a file format that contains [[boundary scan]] vectors to be sent to an [[electronic circuit]] using a [[JTAG]] interface. Boundary scan vectors consist of the following data:&lt;br /&gt;
* Stimulus data: This is data to be sent to a device or [[electronic circuit]]&lt;br /&gt;
* Expected response: This is the data the device or circuit is expected to send back if there is no error&lt;br /&gt;
* [[Mask (computing)|Mask]] data: Defines which [[bit]]s in the expected response are valid; other bits of the device&amp;#039;s response are unknown and must be ignored when comparing the expected response and the data returned from the circuit&lt;br /&gt;
* Additional information on how to send the data (e.g. maximum [[Clock signal|clock]] frequency)&lt;br /&gt;
&lt;br /&gt;
The SVF standard was jointly developed by companies &amp;#039;&amp;#039;[[Texas Instruments]]&amp;#039;&amp;#039; and &amp;#039;&amp;#039;[[Teradyne]]&amp;#039;&amp;#039;.  Control over the format has been handed off to boundary-scan solution provider &amp;#039;&amp;#039;ASSET InterTech&amp;#039;&amp;#039;. The most recent revision is Revision E.&lt;br /&gt;
&lt;br /&gt;
SVF files are used to transfer boundary scan data between tools. As an example a [[VHDL]] compiler may create an SVF file that is read by a tool for programming [[CPLD]]s.&lt;br /&gt;
&lt;br /&gt;
The SVF file is defined as an ASCII file that consists of a set of SVF statements. The maximum number of characters allowed on a line is 256, although one SVF statement can span more than one line. Each statement consists of a command and associated parameters. Each SVF statement is terminated by a semicolon. SVF is not case sensitive. Comments can be inserted into a SVF file after an exclamation point ‘!’ or a pair of slashes ‘//’. Either ‘//’ or ‘!’ will comment out the remainder of the line.&lt;br /&gt;
&lt;br /&gt;
== SVF commands ==&lt;br /&gt;
&lt;br /&gt;
* ENDDR: Specifies default end state for DR scan operations.&lt;br /&gt;
* ENDIR: Specifies default end state for IR scan operations.&lt;br /&gt;
* FREQUENCY: Specifies maximum test clock frequency for IEEE 1149.1 bus operations.&lt;br /&gt;
* HDR: (Header Data Register) Specifies a header pattern that is prepended to the beginning of subsequent DR scan operations.&lt;br /&gt;
* HIR: (Header Instruction Register) Specifies a header pattern that is prepended to the beginning of subsequent IR scan operations.&lt;br /&gt;
* PIO: (Parallel Input/Output) Specifies a parallel test pattern.&lt;br /&gt;
* PIOMAP: (Parallel Input/Output Map) Maps PIO column positions to a logical pin.&lt;br /&gt;
* RUNTEST: Forces the IEEE 1149.1 bus to a run state for a specified number of clocks or a specified time period.&lt;br /&gt;
* SDR: (Scan Data Register) Performs an IEEE 1149.1 Data Register scan.&lt;br /&gt;
* SIR: (Scan Instruction Register) Performs an IEEE 1149.1 Instruction Register scan.&lt;br /&gt;
* STATE: Forces the IEEE 1149.1 bus to a specified stable state.&lt;br /&gt;
* TDR: (Trailer Data Register) Specifies a trailer pattern that is appended to the end of subsequent DR scan operations.&lt;br /&gt;
* TIR: (Trailer Instruction Register) Specifies a trailer pattern that is appended to the end of subsequent IR scan operations.&lt;br /&gt;
* TRST: (Test ReSeT) Controls the optional Test Reset line.&lt;br /&gt;
&lt;br /&gt;
== References ==&lt;br /&gt;
* The In-System Configuration Handbook: A Designer&amp;#039;s Guide to ISC, Neil G. Jacobson, {{ISBN|1-4020-7655-X}}&lt;br /&gt;
&lt;br /&gt;
== External links ==&lt;br /&gt;
* [http://www.asset-intertech.com/eresources/svf-serial-vector-format-specification-jtag-boundary-scan Serial Vector Format Specification] latest version available - Revision E&lt;br /&gt;
* [http://www.xilinx.com/support/documentation/application_notes/xapp503.pdf SVF and XSVF File Formats for Xilinx Devices] specifies XSVF, a binary version of SVF&lt;br /&gt;
&lt;br /&gt;
[[Category:Electronics manufacturing]]&lt;br /&gt;
[[Category:Computer file formats]]&lt;/div&gt;</summary>
		<author><name>imported&gt;KMaster888</name></author>
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