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The '''RISC Single Chip''', or '''RSC''', is a single-chip [[microprocessor]] developed and [[Semiconductor device fabrication|fabricated]] by [[IBM|International Business Machines]] (IBM). The RSC was a feature-reduced single-chip implementation of the [[POWER1]], a multi-chip [[central processing unit]] (CPU) which implemented the [[IBM POWER Instruction Set Architecture|POWER]] [[instruction set architecture]] (ISA). It was used in entry-level [[workstation]] models of the [[IBM RS/6000]] family, such as the Model 220 and 230.

[[File:RSC chip schema.png|right|thumb|Logic schematic of the RSC chip]]
The RSC operated at frequencies of 33 and 45 MHz. It has three [[execution unit]]s: a [[Arithmetic logic unit|fixed point unit]], [[floating point unit]] and branch processor; and an 8 KB unified instruction and data cache. Like the POWER1, the memory controller and I/O was tightly integrated, with the functional units responsible for the functions: a memory interface unit and sequencer unit;{{Clarify|date=March 2011}} residing on the same die as the processor. The RSC contains nine functional units: fixed-point execution unit (FXU), floating-point execution unit (FPU), the [[memory management unit]] (MMU), memory interface unit (MIU), sequencer unit, common on-chip processor unit (COP), instruction fetch unit, and instruction queue and dispatch unit.

The fixed point unit executes [[integer]] instructions, generates addresses in load store operations and some portions of branch instructions. It has a three-stage [[Instruction pipeline|pipeline]] consisting of ''decode'', ''execute'' and ''writeback'' stages. Some instructions require several cycles in the execute stage before they are completed.

The floating point unit executes [[floating point]] instructions. Unlike the POWER1, the RSC does not have [[register renaming]] capability due to a limited die area in which the unit must fit in. To further save die area, the floating point multiply-add array is 32 bits wide. To perform 64-bit ([[double-precision]]) operations, the operands are broken into two, and the instruction passes twice through the multiply-add array. The floating point pipeline consists of four stages, ''decode'', ''multiply'', ''add'' and ''writeback''.

The RSC has an 8 KB unified [[CPU cache|cache]] instead of the separate instruction and large data caches like the POWER1. The unified cache is two-way set associative and uses a store-through policy with no reload on a store miss and a least recently used (LRU) replacement policy. It has a cache line size of 64 bytes, and each cache line is sectored into four [[quadword]]s (16 bytes), with each quadword given its own valid bit in the cache directory. During each cycle, four words can be read from it and two [[doubleword]]s can be written to it.

The memory data bus is 72 bits wide, with 64 bits used for the data path and 8 bits used for [[error correcting code]] (ECC). The memory interface unit manages the bus and performs ECC checks on data coming into the processor. The ECC logic is capable of correcting single-bit errors. Compared to the POWER1, the RSC memory data bus is narrower and uses industry standard [[SIMM]]s instead of custom memory cards.

The RSC contained approximately one million transistors on a 14.9 mm by 15.2 mm (226.48 mm<sup>2</sup>) die fabricated by IBM in a [[CMOS|complementary metal-oxide semiconductor]] (CMOS) [[Semiconductor device fabrication|process]] with a minimal feature size of 0.8 μm and three levels of wiring. It is packaged in a 36 mm by 36 mm ceramic [[pin grid array]] module which had 201 signal pins. It required a 3.6 volt power supply and consumed 4 watts during operation at 33 MHz.

==See also==
* [[PowerPC 600#PowerPC 601|PowerPC 601]] which essentially was a cheaper and less powerful version of RSC with some [[PowerPC]] instructions added.
* [[RAD6000]] which is a radiation hardened version of RSC.

==References==
* {{cite conference|author=Moore, C. R., Balser, D. M., Muhich, J. S., and East, R. E.|year=1992|url=http://zmoore.net/RSC%20ICCD92.pdf|title=IBM Single Chip RISC Processor (RSC)|book-title=Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors|publisher=IEEE Computer Society|isbn=978-0-8186-3110-8|pages= 200–204|archive-url=https://web.archive.org/web/20131004213712/http://zmoore.net/RSC%20ICCD92.pdf|archive-date=4 October 2013}}

[[Category:IBM microprocessors]]

RISC Single Chip - Revision history

imported>Martin Kealey: /* top */ Spelling/grammar/punctuation/typographical correction