imported>PaulBoddie: Changed Acorn press release citation details.

2025-06-28T22:51:26Z

Changed Acorn press release citation details.

New page

The '''R2000''' is a [[32-bit]] [[microprocessor]] chip set developed by [[MIPS Computer Systems]] that implemented the [[MIPS I]] [[instruction set architecture]] (ISA). Introduced in May 1986, it was one of the first commercial implementations of a [[RISC]] architecture, preceded only by the [[IBM RT PC]].<ref name="computerworld19860512_mips">{{ cite magazine | url=https://archive.org/details/computerworld2019unse/page/34/mode/1up | title=MIPS Computer Systems jumps into OEM mart with RISC-based products | magazine=Computerworld | last1=Connolly | first1=James | date=12 May 1986 | access-date=29 June 2025 | pages=34 }}</ref> The R2000 competed with [[Digital Equipment Corporation]] (DEC) [[VAX]] minicomputers and with [[Motorola]] [[68020]] and [[Intel Corporation]] [[80386]] microprocessors. R2000 users included [[Ardent Computer]], DEC, [[Silicon Graphics]], [[Northern Telecom]] and MIPS's own Unix workstations. The "first confirmed customer" of the R2000 was [[Prime Computer]].<ref name="unigramx19860517_mips">{{ cite news | url=https://archive.org/details/UnigramX1986059-108/page/43/mode/1up | title=MIPS Unveils 10 MIPS CMOS RISC Board Set | work=Unigram/X | date=17 May 1986 | access-date=29 June 2025 | pages=1 }}</ref>

The chip set consisted of the R2000 microprocessor, R2010 floating-point accelerator, and four R2020 write buffer chips. The core R2000 chip executed all non-floating-point instructions with a simple short pipeline. This chip also controlled the external code and data caches, made of fast standard SRAM chips organized with direct indexing and one-cycle read latency. The R2000 chip contained a small [[translation lookaside buffer]] for mapping virtual memory addresses. The R2010 chip held the floating point registers, floating point data paths, and their longer simple pipeline. Writes to main memory DRAM took tens of cycles to fully complete. But the R2020 chips queued and completed up to 4 pending writes to main memory, allowing the R2000 core to proceed without stalling itself. In the absence of cache misses, this chip set sustained an instruction completion rate of one instruction per ALU cycle. This was more efficient than non-RISC microprocessors of that time, which needed several cycles per instruction. The initial R2000A, clocked at 12.5 MHz, offered 8-10 Million integer Instructions Per Second (MIPS), or 0.9 Million FLoating Point Operations Per Second (MFLOPS), and would appear in the like of the 1987 [[SGI IRIS]] 4D and 1988 [[DECstation]] 2100 workstations.<ref>{{Cite web |date=1988 |title=Personal IRIS - 4D-20 One-sheet |url=https://forums.sgi.sh/index.php?attachments/personal-iris-4d-20-one-sheet-pdf.2441/}}</ref><ref>{{Cite web |title=DECstation 2100 |url=https://web.archive.org/web/20230603121330/john.ccac.rwth-aachen.de:8000/alf/ds2100/ |access-date=2024-08-20 |website=web.archive.org}}</ref> 1986 also saw similar technology in Sun's first [[SPARC]] microprocessor, Hewlett Packard's first [[PA-RISC]] microprocessor, and the first [[ARM architecture family|Acorn RISC Machine (ARM)]] evaluation kits shipping to developers.<ref>{{ cite press release | date=7 July 1986 | access-date=29 June 2025 | title=Acorn Computers Announce The Availability Of An Evaluation System For Their Single Chip, 32-Bit Reduced Instruction Set Computer - The Arm | url=https://chrisacorns.computinghistory.org.uk/docs/Acorn/PR/Acorn_announces_the_ARM_Evaluation_kit.pdf | publisher=Acorn Computers Limited}}</ref>

Overall speed was limited by the cache size and cache cycle time. The R2000 chip set and SRAM was initially sold only as a complete circuit board to ensure good cache bus timings. In 1987 system builders began using the chip set in arbitrary new board designs.

The R2000 was available in 8.3, 12.5 and 15 MHz grades. The die contained 110,000 transistors and measured 80 mm<sup>2</sup> in a 2.0 μm double-metal CMOS process. MIPS was a [[fabless]] semiconductor company, that is, they did not have the capability to fabricate integrated circuits. The chip set was initially fabricated for MIPS by [[Sierra Semiconductor]] and [[Toshiba]]. In December 1987, MIPS licensed [[Integrated Device Technology]], [[LSI Logic]], and Performance Semiconductor to also fabricate and market the R2000. Sierra and Toshiba continued to serve as foundries.

LSI fabricated the chip set in its 2.0 μm double-metal CMOS process and marketed it as the LR2000. Performance Semiconductor fabricated the chip set in its PACE-I 0.8 μm double-metal CMOS process and marketed it as the PR2000.

In 1988, an improved version was introduced, the R2000A. It was composed of the R2000A and R2010A ICs. It operated at 12.5 and 16.67 MHz. It has been used extensively in embedded applications such as printer controllers.

In 1988, the R2000 was followed by the [[R3000]], using a similar overall system design but faster chip implementation.

==References==
{{reflist}}
* Furber, Stephen Bo (1989). [https://books.google.com/books?id=jKOsdJ8Rk6EC ''VLSI RISC Architecture and Organization'']. p. 132. [[CRC Press]].

{{MIPS microprocessors}}

{{DEFAULTSORT:R2000}}
[[Category:32-bit microprocessors]]
[[Category:Computer-related introductions in 1986]]
[[Category:MIPS implementations]]
[[Category:MIPS microprocessors]]

R2000 microprocessor - Revision history

imported>PaulBoddie: Changed Acorn press release citation details.