imported>Ionmars10: clean up

2025-12-09T04:21:29Z

clean up

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	{{Short description\|Type of programmable logic device}}		{{Short description\|Type of programmable logic device}}
	{{~~confused~~\|Programmable Array Logic}}		{{distinguish\|Programmable Array Logic}}

	[[Image:Programmable logic array (schematic drawing example).svg\|thumb\|right\|PLA schematic example]]		[[Image:Programmable logic array (schematic drawing example).svg\|thumb\|right\|PLA schematic example]]
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	! ~~1<sup>st</sup>~~ block !! ~~2<sup>nd</sup>~~ block !! ~~3<sup>rd</sup>~~ block !! ~~4<sup>TH</sup>~~ block !! ~~5<sup>th</sup>~~ block		! 1st block !! 2nd block !! 3rd block !! 4th block !! 5th block
	\|-		\|-
	\| Input buffer \|\| AND matrix \|\| OR matrix \|\| Invert/non-invert matrix \|\| Flip-flop output buffer		\| Input buffer \|\| AND matrix \|\| OR matrix \|\| Invert/non-invert matrix \|\| Flip-flop output buffer
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	{{Digital electronics}}		{{Digital electronics}}
	{{Authority control}}		{{Authority control}}

	[[Category:Electronic design automation]]		[[Category:Electronic design automation]]
	[[Category:Gate arrays]]		[[Category:Gate arrays]]

imported>Nyq: Decapitlized table contents to sentence case

2025-06-15T02:52:25Z

Decapitlized table contents to sentence case

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	{\| class="wikitable"		{\| class="wikitable"
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	! ~~1ST BLOCK~~ !! ~~2ND BLOCK~~ !! ~~3RD BLOCK~~ !! ~~4TH BLOCK~~ !! ~~5TH BLOCK~~		! 1<sup>st</sup> block !! 2<sup>nd</sup> block !! 3<sup>rd</sup> block !! 4<sup>TH</sup> block !! 5<sup>th</sup> block
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	\| ~~INPUT BUFFER~~ \|\| AND ~~MATRIX~~ \|\| OR ~~MATRIX~~ \|\| ~~INVERT~~/ ~~NON INVERT MATRIX~~ \|\| ~~FLIP~~-~~FLOP OUTPUT BUFFER~~		\| Input buffer \|\| AND matrix \|\| OR matrix \|\| Invert/non-invert matrix \|\| Flip-flop output buffer
	\|}		\|}

imported>Wotheina: Undid revision 1256589020 by 59.88.5.87 (talk):rvv

2024-12-31T02:51:52Z

Undid revision 1256589020 by 59.88.5.87 (talk):rvv

New page

{{Short description|Type of programmable logic device}}
{{confused|Programmable Array Logic}}

[[Image:Programmable logic array (schematic drawing example).svg|thumb|right|PLA schematic example]]
A ''' programmable logic array''' ('''PLA''') is a kind of [[programmable logic device]] used to implement [[combinational logic]] [[electrical network|circuits]]. The PLA has a set of programmable [[AND gate]] planes, which link to a set of programmable [[OR gate]] planes, which can then be conditionally complemented to produce an output. It has 2<sup>N</sup> AND gates for N input variables, and for M outputs from the PLA, there should be M OR gates, each with programmable inputs from all of the AND gates. This layout allows for many logic functions to be synthesized in the sum of products [[Canonical normal form|canonical forms]].

PLAs differ from [[Programmable Array Logic|programmable array logic]] devices ([[Programmable Array Logic|PALs]] and [[Generic Array Logic|GAL]]s) in that both the AND and OR gate planes are programmable. PAL has programmable AND gates but fixed OR gates {{clarify|date=March 2021}}

== History ==
In 1970, [[Texas Instruments]] developed a [[photomask|mask]]-programmable IC based on the [[IBM]] read-only [[Content-addressable memory|associative memory]] or ROAM. This device, the TMS2000, was programmed by altering the metal layer during the production of the IC. The TMS2000 had up to 17 inputs and 18 outputs with 8 [[JK flip-flops]] for memory. TI coined the term ''Programmable Logic Array'' for this device.<ref name = "TI PLA 1970">{{Cite book | last = Andres | first = Kent | title = A Texas Instruments Application Report: MOS programmable logic arrays. | publisher = Texas Instruments | date = October 1970 | id = Bulletin CA-158}}</ref>

==Implementation procedure==

# Preparation in SOP ([[sum of products]]) form.
# Obtain the minimum SOP form to reduce the number of product terms to a minimum.
# Decide the input connection of the AND matrix for generating the required product term.
# Then decide the input connections of the OR matrix to generate the sum terms.
# Decide the connections of the inversion matrix.
# Program the PLA.

PLA block diagram:
{| class="wikitable"
|-
! 1ST BLOCK !! 2ND BLOCK !! 3RD BLOCK !! 4TH BLOCK !! 5TH BLOCK
|-
| INPUT BUFFER || AND MATRIX || OR MATRIX || INVERT/ NON INVERT MATRIX || FLIP-FLOP OUTPUT BUFFER
|}

== Advantages over read-only memory ==
The desired outputs for each combination of inputs ''could'' be programmed into a [[read-only memory]], with the inputs being driven by the address bus and the outputs being read out as data. However, that would require a separate memory location for ''every'' possible combination of inputs, including combinations that are never supposed to occur, and also duplicating data for "don't care" conditions (for example, logic like "if input A is 1, then, as far as output X is concerned, we don't care what input B is": in a ROM this would have to be written out twice, once for each possible value of B, and as more "don't care" inputs are added, the duplication grows exponentially); therefore, a programmable logic array can often implement a piece of logic using fewer transistors than the equivalent in read-only memory. This is particularly valuable when it is part of a processing chip where transistors are scarce (for example, the original [[MOS Technology 6502|6502]] chip contained a PLA to direct various operations of the processor<ref>[http://www.pagetable.com/?p=39 How MOS 6502 Illegal Opcodes really work]</ref>).

== Applications ==
One application of a PLA is to implement the control over a [[datapath]]. It defines various states in an instruction set, and produces the next state (by conditional branching). [e.g. if the machine is in state 2, and will go to state 4 if the instruction contains an immediate field; then the PLA should define the actions of the control in state 2, will set the next state to be 4 if the instruction contains an immediate field, and will define the actions of the control in state 4]. Programmable logic arrays should correspond to a [[state diagram]] for the system.

The earliest [[Commodore 64]] home computers released in 1982 (into early 1983) initially used a programmed Signetics 82S100 PLA, but as the demand increased, MOS Technology / Commodore Semiconductor Group began producing a mask-programmed PLA, which bore part number 906114-01.<ref>[http://www.arcadecomponents.com/catalog/item/3054735/2582640.htm arcadecomponents.com - Commodore 906114-01 64 PLA IC]</ref>

==See also==
* [[Field-programmable gate array]]
* [[Gate array]]
* [[Programmable Array Logic]]

== References ==
{{reflist}}

== External links ==
* {{cite web |url= http://www.cs.umd.edu/class/spring2003/cmsc311/Notes/Comb/pla.html |date= 2003 |work= cmsc311 |title= Programmable Logic Array (PLA) |publisher= [[University of Maryland]] |archive-url=https://web.archive.org/web/20171214191144/www.cs.umd.edu/class/spring2003/cmsc311/Notes/Comb/pla.html |archive-date=2017-12-14 |url-status= dead}}
* {{cite web |url= http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/42-programmable/10-pla/pla.html |title= PLA (programmable logic array) |work= Java Applet |publisher= [[University of Hamburg]] |access-date= 2010-04-07 |archive-url= https://web.archive.org/web/20130115113124/http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/42-programmable/10-pla/pla.html |archive-date= 2013-01-15 |url-status= dead }}

{{Programmable Logic}}
{{Digital electronics}}
{{Authority control}}
[[Category:Electronic design automation]]
[[Category:Gate arrays]]

Programmable logic array - Revision history

imported>Ionmars10: clean up

imported>Nyq: Decapitlized table contents to sentence case

imported>Wotheina: Undid revision 1256589020 by 59.88.5.87 (talk):rvv