imported>Uavertgahe: /* Stud */ Siemens

2025-09-20T05:04:33Z

Stud: Siemens

← Previous revision		Revision as of 05:04, 20 September 2025
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	[[File:AMD Phenom X4 9750 (Underside).JPG\|thumb\|The pin grid array on the bottom of an [[AMD Phenom]] X4 9750 processor that uses the AMD [[Socket AM2+\|AM2+ socket]]]]		[[File:AMD Phenom X4 9750 (Underside).JPG\|thumb\|The pin grid array on the bottom of an [[AMD Phenom]] X4 9750 processor that uses the AMD [[Socket AM2+\|AM2+ socket]]]]

	A '''pin grid array''' ('''PGA''') is a type of [[integrated circuit packaging]]. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart,<ref name="Nath2017">{{cite book\|author=Vijay Nath\|title=Proceedings of the International Conference on Nano-electronics, Circuits & Communication Systems\|url=https://books.google.com/books?id=xvF5DgAAQBAJ&pg=PA304\|date=24 March 2017\|publisher=Springer\|isbn=978-981-10-2999-8\|page=304}}</ref> and may or may not cover the entire underside of the package.		A '''pin grid array''' ('''PGA''') is a type of [[integrated circuit packaging]]. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart,<ref name="Nath2017">{{cite book\|author=Vijay Nath\|title=Proceedings of the International Conference on Nano-electronics, Circuits & Communication Systems\|url=https://books.google.com/books?id=xvF5DgAAQBAJ&pg=PA304\|date=24 March 2017\|publisher=Springer\|isbn=978-981-10-2999-8\|page=304}}</ref> and may or may not cover the entire underside of the package. 1.27 mm (0.05") is commonly used with higher pin count PGAs.

	PGAs are often mounted on [[printed circuit board]]s using the [[Through-hole technology\|through hole]] method or inserted into a [[CPU socket\|socket]]. PGAs allow for more pins per integrated circuit than older packages, such as [[dual in-line package]] (DIP).		PGAs are often mounted on [[printed circuit board]]s using the [[Through-hole technology\|through hole]] method or inserted into a [[CPU socket\|socket]]. PGAs allow for more pins per integrated circuit than older packages, such as [[dual in-line package]] (DIP).
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	=== Stud ===		=== Stud ===
	A stud grid array (SGA) is a short-pinned pin grid array chip scale package for use in [[surface-mount technology]]. The polymer stud grid array or plastic stud grid array was developed jointly by the [[Interuniversity Microelectronics Centre]] (IMEC) and [[Laboratory for Production Technology]], [[Siemens AG]].<ref>{{cite web\|url=http://www.jsits.com/bga-socket/bga_summary.htm \|title=BGA socket/BGA 소켓 \|publisher=Jsits.com \|access-date=2015-06-05}}</ref><ref>[http://www.atplas.com/de/index/mr_index/mr_news/mr_news_business/mr_news_business-fullpage.htm?printout=1&id=7921 link] {{in lang\|de}} {{webarchive \|url=https://web.archive.org/web/20111001232205/http://www.atplas.com/de/index/mr_index/mr_news/mr_news_business/mr_news_business-fullpage.htm?printout=1&id=7921 \|date=October 1, 2011 }}</ref>		A stud grid array (SGA) is a short-pinned pin grid array chip scale package for use in [[surface-mount technology]]. The polymer stud grid array or plastic stud grid array was developed jointly by the [[Interuniversity Microelectronics Centre]] (IMEC) and [[Laboratory for Production Technology]], [[Siemens]].<ref>{{cite web\|url=http://www.jsits.com/bga-socket/bga_summary.htm \|title=BGA socket/BGA 소켓 \|publisher=Jsits.com \|access-date=2015-06-05}}</ref><ref>[http://www.atplas.com/de/index/mr_index/mr_news/mr_news_business/mr_news_business-fullpage.htm?printout=1&id=7921 link] {{in lang\|de}} {{webarchive \|url=https://web.archive.org/web/20111001232205/http://www.atplas.com/de/index/mr_index/mr_news/mr_news_business/mr_news_business-fullpage.htm?printout=1&id=7921 \|date=October 1, 2011 }}</ref>

	=== rPGA ===		=== rPGA ===

imported>MrOllie: Reverted 1 edit by Clarke000 (talk): Spam

2024-11-20T16:44:24Z

Reverted 1 edit by Clarke000 (talk): Spam

New page

{{Short description|Type of integrated circuit packaging with the pins mounted on the underside of the package}}
{{refimprove|date=December 2011}}
[[File:AMD Phenom II X6 1090T (HDT90ZFBK6DGR) CPU-pins PNr°0295.jpg|thumb|350px|Closeup of the pins of a pin grid array]]
[[File:XC68020 bottom p1160085.jpg|thumb|The pin grid array at the bottom of prototype [[Motorola 68020]] microprocessor]]

[[File:AMD Phenom X4 9750 (Underside).JPG|thumb|The pin grid array on the bottom of an [[AMD Phenom]] X4 9750 processor that uses the AMD [[Socket AM2+|AM2+ socket]]]]

A '''pin grid array''' ('''PGA''') is a type of [[integrated circuit packaging]]. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart,<ref name="Nath2017">{{cite book|author=Vijay Nath|title=Proceedings of the International Conference on Nano-electronics, Circuits & Communication Systems|url=https://books.google.com/books?id=xvF5DgAAQBAJ&pg=PA304|date=24 March 2017|publisher=Springer|isbn=978-981-10-2999-8|page=304}}</ref> and may or may not cover the entire underside of the package.

PGAs are often mounted on [[printed circuit board]]s using the [[Through-hole technology|through hole]] method or inserted into a [[CPU socket|socket]]. PGAs allow for more pins per integrated circuit than older packages, such as [[dual in-line package]] (DIP).

== Chip mounting ==

[[File:80486 open.jpg|thumb|right|Underside of an 80486 with lid removed shows die and wire bonded connections.]]

The chip can be mounted either on the top or the bottom (the pinned side). Connections can be made either by [[wire bonding]] or through [[flip chip]] mounting. Typically, PGA packages use wire bonding when the chip is mounted on the pinned side, and flip chip construction when the chip is on the top side. Some PGA packages contain multiple dies, for example [[Zen 2]] and [[Zen 3]] Ryzen CPUs for the [[Socket AM4|AM4 socket]].

=== Flip chip ===
[[File:Ppga.jpg|thumb|right|The underside of a FC-PGA package (The die is on the other side.)]]

A [[flip-chip]] pin grid array (FC-PGA or FCPGA) is a form of pin grid array in which the [[Die (integrated circuit)|die]] faces downwards on the top of the substrate with the back of the die exposed. This allows the die to have a more direct contact with the [[heatsink]] or other cooling mechanism.

FC-PGA CPUs were introduced by [[Intel]] in 1999, for Coppermine core [[Pentium III]] and [[Celeron]]<ref>{{cite web | title=Intel Releases New Design for sub-$1,000 PCs | publisher=Philippine Daily Inquirer | date=April 24, 2000 }}</ref> processors based on [[Socket 370]], and were produced until [[Intel Socket G3|Socket G3]] in 2013. FC-PGA processors fit into [[zero insertion force]] (ZIF) [[CPU socket|motherboard sockets]]; similar packages were also used by AMD.

== Material ==

=== Ceramic ===
A ceramic pin grid array (CPGA) is a type of packaging used by [[integrated circuits]]. This type of packaging uses a ceramic substrate with pins arranged in a pin grid array. Some [[CPU]]s that use CPGA packaging are the AMD [[Socket A]] [[Athlon]]s and the [[Duron]].

A CPGA was used by AMD for Athlon and Duron processors based on Socket A, as well as some AMD processors based on [[Socket AM2]] and [[Socket AM2+]]. While similar form factors have been used by other manufacturers, they are not officially referred to as CPGA. This type of packaging uses a [[ceramic]] substrate with pins arranged in an array.

<gallery class="center">
File:VIA C3 C5XL CPGA.jpg|A 1.2 GHz [[VIA C3]] microprocessor in a ceramic package
File:Pentium P54 Socket7 PGA.jpg|133 MHz Pentium chip in a ceramic package
</gallery>

=== Organic ===
[[File:AMD 754 - PGA ZIF demonstration - 2016.webm|thumb|Demonstration of a PGA-ZIF socket ([[Socket 754|AMD 754]])]]
An organic pin grid array (OPGA) is a type of connection for [[integrated circuit]]s, and especially [[Central processing unit|CPUs]], where the [[silicon]] [[Die (integrated circuit)|die]] is attached to a plate made out of an [[organic compound|organic]] [[plastic]] which is pierced by an array of [[pin]]s which make the requisite connections to the [[CPU socket|socket]].

<gallery class="center">
File:SL3A2down.JPG|The underside of a [[Celeron]]-400 in a PPGA
File:AMD Athlon XP 2000 - Socket A - OPGA.jpg|An OPGA CPU. Note the brown color – many OPGA parts are colored green. The die is in the center of the device, and the four gray circles are foam spacers to relieve pressure from the die, caused by the heat sink.
</gallery>

=== Plastic ===
[[File:UpSL3A2.JPG|thumb|left|180px|The topside of a [[Celeron]]-400 in a PPGA packing]]

Plastic pin grid array (PPGA) packaging was used by Intel for late-model Mendocino core [[Celeron]] processors based on [[Socket 370]].<ref name="ThompsonThompson2003">{{cite book|author1=Robert Bruce Thompson|author2=Barbara Fritchman Thompson|title=PC Hardware in a Nutshell: A Desktop Quick Reference|url=https://books.google.com/books?id=kG8LcWfruOAC&pg=PT44|date=24 July 2003|publisher=O'Reilly Media, Inc.|isbn=978-0-596-55234-3|page=44}}</ref> Some pre-Socket 8 processors also used a similar form factor, although they were not officially referred to as PPGA.

[[File:Pentium 4 Underside Demonstrating PGA Socket.JPG|thumb|Underside of a [[Pentium 4]] in a PGA package]]
== Pin layout ==

=== Staggered pin ===
The staggered pin grid array (SPGA) is used by Intel processors based on [[Socket 5]] and [[Socket 7]]. [[Socket 8]] used a partial SPGA layout on half the processor.
[[File:Socket 7.jpg|right|thumb|300px|An example of a socket for a staggered pin grid array package]]

[[File:Cyrix IBM CPU 6x86MX PR200 bottom.jpg|thumb|View of the socket 7 321-pin connectors of a CPU]]

It consists of two square arrays of pins, offset in both directions by half the minimum distance between pins in one of the arrays. Put differently: within a square boundary the pins form a diagonal square [[Lattice (group)|lattice]]. There is generally a section in the center of the package without any pins. SPGA packages are usually used by devices that require a higher pin density than what a PGA can provide, such as [[microprocessor]]s.

=== Stud ===
A stud grid array (SGA) is a short-pinned pin grid array chip scale package for use in [[surface-mount technology]]. The polymer stud grid array or plastic stud grid array was developed jointly by the [[Interuniversity Microelectronics Centre]] (IMEC) and [[Laboratory for Production Technology]], [[Siemens AG]].<ref>{{cite web|url=http://www.jsits.com/bga-socket/bga_summary.htm |title=BGA socket/BGA 소켓 |publisher=Jsits.com |access-date=2015-06-05}}</ref><ref>[http://www.atplas.com/de/index/mr_index/mr_news/mr_news_business/mr_news_business-fullpage.htm?printout=1&id=7921 link] {{in lang|de}} {{webarchive |url=https://web.archive.org/web/20111001232205/http://www.atplas.com/de/index/mr_index/mr_news/mr_news_business/mr_news_business-fullpage.htm?printout=1&id=7921 |date=October 1, 2011 }}</ref>

=== rPGA ===
The reduced pin grid array was used by the socketed mobile variants of Intel's Core i3/5/7 processors and features a reduced pin pitch of 1{{nbsp}}mm,<ref>{{cite web|title=Molex Sockets for Servers, Desktops and Notebooks Earn Intel® Validation|url=http://www.molex.com/mx_upload/editorial/833/Sockets_earn_intel_validation_pr.html|access-date=2016-03-15|archive-date=2019-12-09|archive-url=https://web.archive.org/web/20191209133509/http://www.molex.com/mx_upload/editorial/833/Sockets_earn_intel_validation_pr.html|url-status=dead}}</ref> as opposed to the 1.27{{nbsp}}mm pin pitch used by contemporary AMD processors and older Intel processors. It is used in the [[Socket G1|G1]], [[Socket G2|G2]], and [[Intel Socket G3|G3]] sockets.

== See also ==
{{Div col|colwidth=30em}}
* [[Ball grid array]] (BGA)
* [[Centered square number]]
* [[Chip carrier]] - chip packaging and package types list
* [[Dual in-line package]] (DIP)
* [[Land grid array]] (LGA)
* [[Single in-line package]] (SIP)
* [[Zig-zag in-line package]] (ZIP)
{{div col end}}

== References ==
{{Reflist}}

== Sources ==
* {{cite web | url=https://www.theregister.co.uk/2000/08/04/what_the_hell/ | title=What the Hell is… a flip-chip? | publisher=The Register | date=August 4, 2010 | access-date=December 30, 2011 | author=Thomas, Andrew}}
* {{cite web | url=http://reviews.cnet.com/soho-servers/xseries-335-xeon-dp/1707-3125_7-20584151.html | title=XSERIES 335 XEON DP-2.4G 512 MB | publisher=CNET | date=October 26, 2002 | access-date=December 30, 2011}}
* {{cite web | url=http://www.topline.tv/SMT_Nomenclature.pdf | title=SURFACE MOUNT NOMENCLATURE AND PACKAGING }}

== External links ==
* [http://support.intel.com/support/processors/sb/CS-009863.htm Intel CPU Processor Identification]
* [http://www.semiconductor.net/article/196993-Ball_Grid_Arrays_the_High_Pincount_Workhorses.php Ball Grid Arrays: the High-Pincount Workhorses]{{Dead link|date=May 2020 |bot=InternetArchiveBot |fix-attempted=yes }}, John Baliga, associate editor, ''[[Semiconductor International]]'', 9/1/1999
* [http://www.epp-online.de/epp/live/de/fachartikelarchiv/ha_artikel/detail/330473.html Spot on component packaging]{{Dead link|date=May 2020 |bot=InternetArchiveBot |fix-attempted=yes }}, 08/1998, ''[[Elektronik, Produktion & Prüftechnik]]''
* [http://sandbox.cz/~covex/nse/terminy.html Terminology]


{{Semiconductor packages}}

[[Category:Chip carriers]]

Pin grid array - Revision history

imported>Uavertgahe: /* Stud */ Siemens

imported>MrOllie: Reverted 1 edit by Clarke000 (talk): Spam