<?xml version="1.0"?>
<feed xmlns="http://www.w3.org/2005/Atom" xml:lang="en">
	<id>http://debianws.lexgopc.com/wiki143/index.php?action=history&amp;feed=atom&amp;title=Open_Verification_Library</id>
	<title>Open Verification Library - Revision history</title>
	<link rel="self" type="application/atom+xml" href="http://debianws.lexgopc.com/wiki143/index.php?action=history&amp;feed=atom&amp;title=Open_Verification_Library"/>
	<link rel="alternate" type="text/html" href="http://debianws.lexgopc.com/wiki143/index.php?title=Open_Verification_Library&amp;action=history"/>
	<updated>2026-05-10T16:27:45Z</updated>
	<subtitle>Revision history for this page on the wiki</subtitle>
	<generator>MediaWiki 1.43.1</generator>
	<entry>
		<id>http://debianws.lexgopc.com/wiki143/index.php?title=Open_Verification_Library&amp;diff=4920828&amp;oldid=prev</id>
		<title>imported&gt;ClueBot NG: Reverting possible vandalism by 171.61.113.103 to version by Justanothersgwikieditor. Report False Positive? Thanks, ClueBot NG. (4033472) (Bot)</title>
		<link rel="alternate" type="text/html" href="http://debianws.lexgopc.com/wiki143/index.php?title=Open_Verification_Library&amp;diff=4920828&amp;oldid=prev"/>
		<updated>2021-09-05T11:43:59Z</updated>

		<summary type="html">&lt;p&gt;Reverting possible vandalism by &lt;a href=&quot;/wiki143/index.php?title=Special:Contributions/171.61.113.103&quot; title=&quot;Special:Contributions/171.61.113.103&quot;&gt;171.61.113.103&lt;/a&gt; to version by Justanothersgwikieditor. &lt;a href=&quot;/wiki143/index.php?title=WP:CBFP&amp;amp;action=edit&amp;amp;redlink=1&quot; class=&quot;new&quot; title=&quot;WP:CBFP (page does not exist)&quot;&gt;Report False Positive?&lt;/a&gt; Thanks, &lt;a href=&quot;/wiki143/index.php?title=WP:CBNG&amp;amp;action=edit&amp;amp;redlink=1&quot; class=&quot;new&quot; title=&quot;WP:CBNG (page does not exist)&quot;&gt;ClueBot NG&lt;/a&gt;. (4033472) (Bot)&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;&amp;#039;&amp;#039;&amp;#039;Open Verification Library&amp;#039;&amp;#039;&amp;#039; (OVL) is a library of property checkers for digital circuit descriptions written in popular [[hardware description language|Hardware Description Languages (HDLs)]]. OVL is currently maintained by [[Accellera]].&lt;br /&gt;
==Applications==&lt;br /&gt;
OVL works by placing modules or components checking specific properties of the circuit alongside regular modules or components. Those special modules are called &amp;#039;&amp;#039;&amp;#039;checkers&amp;#039;&amp;#039;&amp;#039; and are tied to circuit signals via &amp;#039;&amp;#039;&amp;#039;ports&amp;#039;&amp;#039;&amp;#039;. Some aspects of the checker functionality can be modified by adjusting checker &amp;#039;&amp;#039;&amp;#039;parameters&amp;#039;&amp;#039;&amp;#039;. Typical properties verified by OVL checkers include:&lt;br /&gt;
* condition that should be always met,&lt;br /&gt;
* sequence of conditions that should be met,&lt;br /&gt;
* condition that should never occur,&lt;br /&gt;
* proper data value (even, odd, within a range, etc.),&lt;br /&gt;
* proper value change (e.g. increment or decrement within specified range),&lt;br /&gt;
* proper data encoding (e.g. &amp;#039;&amp;#039;one hot&amp;#039;&amp;#039; or &amp;#039;&amp;#039;one cold&amp;#039;&amp;#039;),&lt;br /&gt;
* proper timing of event (within given number of clock cycles or within window created by trigger events),&lt;br /&gt;
* valid protocol of data transmission,&lt;br /&gt;
* valid behavior of popular building blocks (e.g. [[FIFO (computing and electronics)|FIFOs]]).&lt;br /&gt;
Depending on the selected parameters, OVL checkers can work as assertion, assumption or coverage point checkers.&lt;br /&gt;
Main source of OVL popularity is the fact that it allows introducing high-level verification concepts to the existing or new designs without requiring new language, e.g. a designer having access to Verilog tools does not need a new language to start using property checking with OVL.  &lt;br /&gt;
==Supported Languages==&lt;br /&gt;
While first versions of OVL supported [[Verilog]] and [[VHDL]], most recent versions support (in alphabetical order):&lt;br /&gt;
* [[Property Specification Language|PSL]] - Verilog flavour&lt;br /&gt;
* [[SystemVerilog]]&lt;br /&gt;
* [[Verilog]]&lt;br /&gt;
* [[VHDL]]&lt;br /&gt;
Depending on the demand, support for two more languages may be added: &amp;#039;&amp;#039;[[Property Specification Language|PSL]] - VHDL&amp;#039;&amp;#039; flavour and &amp;#039;&amp;#039;[[SystemC]]&amp;#039;&amp;#039;.&lt;br /&gt;
==External links==&lt;br /&gt;
* OVL section of the Accellera page [http://www.accellera.org/activities/ovl/] &lt;br /&gt;
&lt;br /&gt;
[[Category:Hardware description languages]]&lt;/div&gt;</summary>
		<author><name>imported&gt;ClueBot NG</name></author>
	</entry>
</feed>