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In [[computing]], '''Machine Check Architecture''' ('''MCA''') is an [[Intel]] and [[AMD]] mechanism in which the [[CPU]] reports hardware errors to the [[operating system]].

[[Intel]]'s P6 and Pentium 4 family processors, [[AMD]]'s K7 and K8 family processors, as well as the Itanium architecture implement a machine check architecture that provides a mechanism for detecting and reporting hardware (machine) errors, such as: system bus errors, [[Error detection and correction#Error-correcting code|ECC]] errors, parity errors, [[CPU cache|cache]] errors, and [[translation lookaside buffer]] errors. It consists of a set of model-specific registers ([[Model-specific register|MSR]]s) that are used to set up machine checking and additional banks of MSRs used for recording errors that are detected.<ref>{{cite book
| title = Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2
| publisher = [[Intel]] Corporation
| date = November 2018
| chapter = Machine Check Architecture
| url = https://www.intel.com/content/www/us/en/content-details/789580/intel-64-and-ia-32-architectures-software-developer-s-manual-volume-3b-system-programming-guide-part-2.html}}</ref>

==See also==
* [[Machine-check exception]] (MCE)
* [[High availability]] (HA)
* [[Reliability, availability and serviceability]] (RAS)
* [[Windows Hardware Error Architecture]] (WHEA)

==References==
{{Reflist}}

==External links==
* [http://www.microsoft.com/whdc/system/platform/64bit/MCAsupport.mspx Microsoft's article on Itanium's MCA]
* [http://www.mcelog.org/ Linux x86 daemon for processing of machine checks]

[[Category:Computer architecture]]
[[Category:X86 architecture]]

{{Compu-hardware-stub}}

Machine Check Architecture - Revision history

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