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{{short description|Type of interrupt signal sent between computer processors}}
{{More references|date=December 2014}}

In [[computing]], an '''inter-processor interrupt''' ('''IPI'''), also known as a ''shoulder tap'', is a special type of [[interrupt]] by which one [[Processor (computing)|processor]] may interrupt another processor in a [[multiprocessor]] system if the interrupting processor requires action from the other processor. Actions that might be requested include:

* flushes of [[memory management unit]] caches, such as [[translation lookaside buffer]]s, on other processors when memory mappings are changed by one processor;
* stopping when the system is being shut down by one processor.
* Notify a processor that higher priority work is available.
* Notify a processor of work that cannot be done on all processors due to, e.g.,
** asymmetric access to [[I/O channel]]s<ref>{{cite manual
| title = OS I/O Supervisor Logic - Release 21 - Program Number 360S-CI-505
| id = GY28-6616-9
| page = 271
| section = Appendix F: Multiprocessing Extensions
| section-url = http://bitsavers.org/pdf/ibm/360/os/R21.7_Apr73/plm/GY28-6616-9_OS_IO_Superv_PLM_R21.7_Apr73.pdf#page=282
| url = http://bitsavers.org/pdf/ibm/360/os/R21.7_Apr73/plm/GY28-6616-9_OS_IO_Superv_PLM_R21.7_Apr73.pdf
| series = Program Logic
| publisher = [[IBM]]
| access-date = August 28, 2022
}}
</ref>
** special features on some processors<ref>{{Cite web |title=AMD Technical Information Portal |url=https://docs.amd.com/r/en-US/am011-versal-acap-trm/Inter-Processor-Interrupts |access-date=2024-07-18 |website=docs.amd.com}}</ref>

== Mechanism ==
The [[OS/360 and successors#M65MP|M65MP]] option of [[OS/360 and successors|OS/360]] used the Direct Control feature of the [[IBM System/360|S/360]] to generate an interrupt on another processor; on [[IBM System/370|S/370]] and its successors, including [[z/Architecture]], the SIGNAL PROCESSOR instruction provides a more formalized interface. The documentation for some IBM operating systems refers to this as a shoulder tap.

On [[IBM PC compatible]] computers that use the [[Advanced Programmable Interrupt Controller]] (APIC), IPI signaling is often performed using the APIC. When a CPU wishes to send an interrupt to another CPU, it stores the [[interrupt vector]] and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which then issues a corresponding interrupt to its own CPU.

== Examples ==
In a multiprocessor system running [[Microsoft Windows]], a processor may interrupt another processor for the following reasons, in addition to the ones listed above:<ref>{{Cite web |title=Inter Processor Interrupt usage |url=https://stackoverflow.com/questions/15091165/inter-processor-interrupt-usage |access-date=2024-07-18 |website=Stack Overflow |language=en}}</ref>

# queue a DISPATCH_LEVEL interrupt to schedule a particular thread for execution;
# kernel debugger breakpoint.

IPIs are given an [[IRQL (Windows)|IRQL]] of 29.<ref>{{cite web
|author = Matt
|title = Understanding IRQL
|url = http://ext2fsd.sourceforge.net/documents/irql.htm
|accessdate = 2014-12-06
|date = 2002-04-28
|archive-date = 2019-10-14
|archive-url = https://web.archive.org/web/20191014125625/http://ext2fsd.sourceforge.net/documents/irql.htm
|url-status = dead
}}</ref>

==See also==
* [[Interrupt]]
* [[Interrupt handler]]
* [[Non-maskable interrupt]] (NMI)

== References ==
{{Reflist}}

== External links ==
*[http://linux.linti.unlp.edu.ar/images/0/0c/ULK3-CAPITULO4-UNNOBA.pdf Interrupts and Exceptions]

[[Category:Interrupts]]

{{Compu-hardware-stub}}

Inter-processor interrupt - Revision history

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