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	<title>Core Multiplexing Technology - Revision history</title>
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	<updated>2026-05-07T16:49:30Z</updated>
	<subtitle>Revision history for this page on the wiki</subtitle>
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	<entry>
		<id>http://debianws.lexgopc.com/wiki143/index.php?title=Core_Multiplexing_Technology&amp;diff=3131248&amp;oldid=prev</id>
		<title>imported&gt;Renwick00: Linked &quot;CPU&quot; to its page</title>
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		<updated>2022-03-03T23:22:44Z</updated>

		<summary type="html">&lt;p&gt;Linked &amp;quot;CPU&amp;quot; to its page&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;{{Update|inaccurate=yes|date=November 2010}}&lt;br /&gt;
&amp;#039;&amp;#039;&amp;#039;Core Multiplexing Technology&amp;#039;&amp;#039;&amp;#039; is a term that appeared in some [[BIOS]]es.&lt;br /&gt;
&lt;br /&gt;
==Details==&lt;br /&gt;
A subset of traditional applications are often difficult to parallelize and make use of additional [[CPU]] hardware available on the platform, restraining applications to use only one CPU. Core Multiplexing Technology would allow for a process to be split into multiple threads at compilation time and execution time by the introduction of speculative multithreading.&lt;br /&gt;
&lt;br /&gt;
Much in the same way a [[branch predictor]] allows for a processor to speculate on the outcome of a branch operation without actually performing the operation, speculative multithreading allows for the processor to speculate deeper, executing entire branches of code on an additional core. Most of the implementation is done in [[software]], with the compiler rearranging code to take better use of a multithreaded platform, which allows [[Simultaneous multithreading]] (SMT) and [[Multi-core processor|Multicore]] systems (or a combination of the two) to take advantage of the technology. But, because the data dependencies of speculative multithreading, and the necessity to manage inter-thread dependent data, hardware implementation must be taken into consideration.&lt;br /&gt;
&lt;br /&gt;
Core Multiplexing Technology is thought to leverage [[Intel]]&amp;#039;s Advanced Smart Cache technology of the upcoming [[Core 2]] chips, which allows two cores to share a single [[L2 cache]], and actively resize the cache between the two processors if one is idle, by allowing the two cores to share data to manage inter-thread dependent data.&lt;br /&gt;
&lt;br /&gt;
==See also==&lt;br /&gt;
*[[3Server]]&lt;br /&gt;
*[[Apulet]]&lt;br /&gt;
*[[BINAC]]&lt;br /&gt;
&lt;br /&gt;
==External Resources==&lt;br /&gt;
*[http://www.intel.com/technology/magazine/research/speculative-threading-1205.htm Intel Research on Speculative Multithreading]&lt;br /&gt;
*[https://web.archive.org/web/20060717121425/http://www.xbitlabs.com/news/cpu/display/20060627095448.html Coverage of Core Multiplexing Technology BIOS Option]&lt;br /&gt;
&lt;br /&gt;
[[Category:BIOS]]&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
{{Compu-hardware-stub}}&lt;/div&gt;</summary>
		<author><name>imported&gt;Renwick00</name></author>
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