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	{{Refimprove\|date=November 2013}}		{{Refimprove\|date=November 2013}}
	{{Short description\|Type of electronic component}}		{{Short description\|Type of electronic component}}
	[[~~Image~~:Altera MAX 7128 2500 gate CPLD.jpg\|thumb~~\|300px~~\|An [[Altera]] MAX 7000-series CPLD with 2500 gates.]]		[[File:Altera MAX 7128 2500 gate CPLD.jpg\|thumb\|An [[Altera]] MAX 7000-series CPLD with 2500 gates in a [[Plastic leaded chip carrier\|PLCC]] package.]]
	[[~~Image~~:Altera-epm7032-HD.jpg\|thumb\|[[Die (integrated circuit)\|Die]] of an [[Altera]] EPM7032 [[EEPROM]]-based CPLD. Die size 3446x2252 μm. Technology node 1 μm.]]		[[File:Altera-epm7032-HD.jpg\|thumb\|[[Die (integrated circuit)\|Die]] of an [[Altera]] EPM7032 [[EEPROM]]-based CPLD. Die size 3446x2252 μm. [[Technology node]] [[1 μm process\|1 μm]].]]

	A '''complex programmable logic device''' ('''CPLD''') is a [[programmable logic device]] with complexity between that of [[Programmable Array Logic\|~~PAL~~]]s and [[Field-programmable gate array\|~~FPGA~~]]s, and architectural features of both. The main building block of the CPLD is a [[Macrocell array\|macrocell]], which contains logic implementing [[disjunctive normal form]] expressions and more specialized logic operations.		A '''complex programmable logic device''' ('''CPLD''') is a [[programmable logic device]] with complexity between that of [[Programmable Array Logic\|programmable array logic]] (PAL) and [[Field-programmable gate array\|field-programmable gate arrays]] (FPGA), and architectural features of both. The main building block of the CPLD is a [[Macrocell array\|macrocell]], which contains logic implementing [[disjunctive normal form]] expressions and more specialized logic operations.

	==Features==		==Features==
	Some of the CPLD features are in common with ~~[[Programmable array logic\|PAL]]s~~:		Some of the CPLD features are in common with PALs:
	* Non-volatile configuration memory. Unlike many FPGAs, an external configuration [[read-only memory\|ROM]] is not required, and the CPLD can function immediately on system start-up.		* Non-volatile configuration memory. Unlike many FPGAs, an external configuration [[read-only memory\|ROM]] is not required, and the CPLD can function immediately on system start-up.
	* For many legacy CPLD devices, routing constrains most logic blocks to have input and output signals connected to external pins, reducing opportunities for internal state storage and deeply layered logic. This is usually not a factor for larger CPLDs and newer CPLD product families.		* For many legacy CPLD devices, routing constrains most logic blocks to have input and output signals connected to external pins, reducing opportunities for internal state storage and deeply layered logic. This is usually not a factor for larger CPLDs and newer CPLD product families.

	Other features are in common with ~~[[field programmable gate array\|FPGA]]s~~:		Other features are in common with FPGAs:
	* Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of [[logic gate]]s, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million.		* Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of [[logic gate]]s, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million.
	* Some provisions for logic more flexible than [[disjunctive normal form\|sum-of-product]] expressions, including complicated feedback paths between macro cells, and specialized logic for implementing various commonly used functions, such as [[integer]] [[arithmetic]].		* Some provisions for logic more flexible than [[disjunctive normal form\|sum-of-product]] expressions, including complicated feedback paths between macro cells, and specialized logic for implementing various commonly used functions, such as [[integer]] [[arithmetic]].

	The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD, which allows CPLDs to be used for "[[boot loader]]" functions, before handing over control to other devices not having their own permanent program storage. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.<ref>{{cite web		The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD, which allows CPLDs to be used for "[[boot loader]]" functions, before handing over control to other devices not having their own permanent program storage. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.<ref>{{cite web \|url=http://only-vlsi.blogspot.com/2008/05/complex-programmable-logic-device.html \|title=Complex Programmable Logic Device \|date=May 2008 \|access-date = 2013-11-17 \|publisher=blogspot.com}}</ref>
	\| url = http://only-vlsi.blogspot.com/2008/05/complex-programmable-logic-device.html
	\| title = Complex Programmable Logic Device
	\|date=May 2008 \| access-date = 2013-11-17
	\| publisher = blogspot.com
	}}</ref>

	==Distinctions==		==Distinctions==
	CPLDs were an evolutionary step from even smaller devices that preceded them: [[~~programmable~~ logic array\|~~PLA~~]]s (first shipped by [[Signetics]]) and ~~[[programmable array logic\|PAL]]s~~. These in turn were preceded by [[Logic family\|standard logic]] products, which offered no programmability and were used to build logic functions by physically wiring several standard logic chips (or hundreds of them) together (usually with wiring on a printed circuit board or boards, but sometimes, especially for prototyping, using [[wire wrap]] wiring).		CPLDs were an evolutionary step from even smaller devices that preceded them: [[Programmable logic array\|programmable logic arrays]] (PLA) (first shipped by [[Signetics]]) and PALs. These in turn were preceded by [[Logic family\|standard logic]] products, which offered no programmability and were used to build logic functions by physically wiring several standard logic chips (or hundreds of them) together (usually with wiring on a printed circuit board or boards, but sometimes, especially for prototyping, using [[wire wrap]] wiring).

	The main distinction between FPGA and CPLD device architectures is that CPLDs are internally based on a collection of PLDs accompanied by a programmable interconnection structure, while FPGAs use [[Logic_block\|logic blocks]].		The main distinction between FPGA and CPLD device architectures is that CPLDs are internally based on a collection of PLDs accompanied by a programmable interconnection structure, while FPGAs use [[Logic_block\|logic blocks]].

216.152.18.132: /* See also */

2025-05-02T17:19:24Z

See also

New page

{{Refimprove|date=November 2013}}
{{Short description|Type of electronic component}}
[[Image:Altera MAX 7128 2500 gate CPLD.jpg|thumb|300px|An [[Altera]] MAX 7000-series CPLD with 2500 gates.]]
[[Image:Altera-epm7032-HD.jpg|thumb|[[Die (integrated circuit)|Die]] of an [[Altera]] EPM7032 [[EEPROM]]-based CPLD. Die size 3446x2252 μm. Technology node 1 μm.]]

A '''complex programmable logic device''' ('''CPLD''') is a [[programmable logic device]] with complexity between that of [[Programmable Array Logic|PAL]]s and [[Field-programmable gate array|FPGA]]s, and architectural features of both. The main building block of the CPLD is a [[Macrocell array|macrocell]], which contains logic implementing [[disjunctive normal form]] expressions and more specialized logic operations.

==Features==
Some of the CPLD features are in common with [[Programmable array logic|PAL]]s:
* Non-volatile configuration memory. Unlike many FPGAs, an external configuration [[read-only memory|ROM]] is not required, and the CPLD can function immediately on system start-up.
* For many legacy CPLD devices, routing constrains most logic blocks to have input and output signals connected to external pins, reducing opportunities for internal state storage and deeply layered logic. This is usually not a factor for larger CPLDs and newer CPLD product families.

Other features are in common with [[field programmable gate array|FPGA]]s:
* Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of [[logic gate]]s, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million.
* Some provisions for logic more flexible than [[disjunctive normal form|sum-of-product]] expressions, including complicated feedback paths between macro cells, and specialized logic for implementing various commonly used functions, such as [[integer]] [[arithmetic]].

The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD, which allows CPLDs to be used for "[[boot loader]]" functions, before handing over control to other devices not having their own permanent program storage. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.<ref>{{cite web
| url = http://only-vlsi.blogspot.com/2008/05/complex-programmable-logic-device.html
| title = Complex Programmable Logic Device
|date=May 2008 | access-date = 2013-11-17
| publisher = blogspot.com
}}</ref>

==Distinctions==
CPLDs were an evolutionary step from even smaller devices that preceded them: [[programmable logic array|PLA]]s (first shipped by [[Signetics]]) and [[programmable array logic|PAL]]s. These in turn were preceded by [[Logic family|standard logic]] products, which offered no programmability and were used to build logic functions by physically wiring several standard logic chips (or hundreds of them) together (usually with wiring on a printed circuit board or boards, but sometimes, especially for prototyping, using [[wire wrap]] wiring).

The main distinction between FPGA and CPLD device architectures is that CPLDs are internally based on a collection of PLDs accompanied by a programmable interconnection structure, while FPGAs use [[Logic_block|logic blocks]].

==See also==
* Language:
** [[VHSIC Hardware Description Language]] (VHDL)
** [[Verilog|Verilog Hardware Description Language]]
** [[Standard Test and Programming Language]] (JAM/STAPL)
* Manufacturers:
**[[Altera]] (Now Intel)
** [[Cypress Semiconductor]]
** [[Lattice Semiconductor]]
** [[Microchip Technology]] (subsumed [[Atmel]])
** [[Xilinx]] (Now AMD)
* Technology:
** [[Application-specific integrated circuit]] (ASIC)
** [[Erasable programmable logic device]] (EPLD)
** [[Simple programmable logic device]] (SPLD)
** [[Macrocell array]]
** [[Programmable array logic]] (PAL)
** [[Programmable logic array]] (PLA)
** [[Programmable logic device]] (PLD)
** [[Generic array logic]] (GAL)
** [[Programmable electrically erasable logic]] (PEEL)
** [[Field-programmable gate array]] (FPGA)

==References==
{{commonscat|Complex programmable logic devices}}
{{Reflist}}

{{Programmable Logic}}
{{Digital electronics}}
{{Hardware acceleration}}
{{DEFAULTSORT:Complex Programmable Logic Device}}

[[Category:Gate arrays]]
[[Category:Hardware acceleration]]

[[fr:Circuit logique programmable#CPLD]]

Complex programmable logic device - Revision history

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216.152.18.132: /* See also */