View source for Xeon

{{short description|Line of Intel server and workstation processors}}
{{distinguish|Xenon|Intel Xe}}
{{for|the English music producer|Sophie (musician)}}
{{Use mdy dates|date=October 2018}}
{{Infobox CPU
| name           = Xeon
| image          = Intel-Xeon-Badge-2024.jpg
| image_size     = 
| alt            = 
| caption        = Logo since 2024
<!----------------- General Info ----------------->
| produced-start = {{Start date and age|June 29, 1998}}<ref name=:0 />
| produced-end   = 
| soldby         = [[Intel]]
| designfirm     = Intel
| manuf1         = Intel
| cpuid          = 
| code           = 
<!----------------- Performance ------------------>
| slowest        = 400
| slow-unit      = MHz
| fastest        = 5.3
| fast-unit      = GHz
| fsb-slowest    = 100
| fsb-fastest    = 1.6
| fsb-slow-unit  = MT/s
| fsb-fast-unit  = GT/s
| hypertransport-slowest   = 
| hypertransport-fastest   = 
| hypertransport-slow-unit = 
| hypertransport-fast-unit = 
| qpi-slowest    = 4.8
| qpi-fastest    = 24
| qpi-slow-unit  = GT/s
| qpi-fast-unit  = GT/s
| dmi-slowest    = 2.0
| dmi-fastest    = 16
| dmi-slow-unit  = GT/s
| dmi-fast-unit  = GT/s
| data-width     = Up to 64 bits
| address-width  = Up to 64 bits
| virtual-width  = Up to 57 bits
<!-------------------- Cache --------------------->
| l1cache        = Up to 80&nbsp;KB per core <!-- leave it 80kb and don't change it to 112kb until granite rapids comes -->
| l2cache        = Up to 2&nbsp;MB per core
| l3cache        = Up to 320&nbsp;MB per socket <!-- leave it 320mb and don't change it to 480mb until granite rapids comes -->
| l4cache        = Up to 64{{nbsp}}GB [[High Bandwidth Memory#HBM2E|HBM2e]]<ref>{{cite web |last1=Cutress |first1=Ian |date=November 15, 2021 |title=Intel: Sapphire Rapids With 64 GB of HBM2e, Ponte Vecchio with 408 MB L2 Cache |url=https://www.anandtech.com/show/17067/intel-sapphire-rapids-with-64-gb-of-hbm2e-ponte-vecchio-with-408-mb-l2-cache |website=AnandTech |language=en-US |access-date=December 11, 2022}}</ref>
| llcache        = 
<!------- Architecture and classification -------->
| application    = {{ubl
  |[[Server (computing)|Servers]]
  |[[Workstation|Workstations]]
  |[[Embedded system|Embedded systems]]
}}
| size-from      = 250 nm
| size-to        = Intel 3 and TSMC N5
| microarch      = {{Unbulleted list
  | [[P6 (microarchitecture)|P6]]
  | [[NetBurst]]
  | [[Intel Core (microarchitecture)|Core]]
  | [[Nehalem (microarchitecture)|Nehalem]]
  | [[Westmere (microarchitecture)|Westmere]]
  | [[Sandy Bridge]]
  | [[Ivy Bridge (microarchitecture)|Ivy Bridge]]
  | [[Haswell (microarchitecture)|Haswell]]
  | [[Broadwell (microarchitecture)|Broadwell]]
  | [[Skylake (microarchitecture)|Skylake]]
  | [[Sunny Cove (microarchitecture)|Sunny Cove]]
  | [[Cypress Cove (microarchitecture)|Cypress Cove]]
  | [[Golden Cove (microarchitecture)|Golden Cove]]
  | [[Golden Cove (microarchitecture)#Raptor Cove|Raptor Cove]]
  | [[Redwood Cove (microarchitecture)|Redwood Cove]]
  | [[Crestmont (microarchitecture)|Crestmont]]
}}
| arch           = [[x86-16]], [[IA-32]], [[x86-64]]
| instructions   = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions#Advanced Vector Extensions 2|AVX2]], [[FMA3]], [[AVX-512]], [[Advanced Vector Extensions#AVX-VNNI|AVX-VNNI]], [[Advanced Matrix Extensions|AMX]], [[Transactional Synchronization Extensions|TSX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]]
| extensions     = [[Intel Software Guard Extensions|SGX]], [[Intel SHA extensions|SHA]], [[Trusted Execution Technology|TXT]], [[VT-x]], [[VT-d]]
<!----------- Physical specifications ------------>
| transistors    =
| numcores       = Up to 64 cores per socket (up to 128 threads per socket)
| amountmemory   = Up to 4&nbsp;TB and 8 channels per socket
| memory1        = Up to [[DDR5]]-5600 with [[Error correction code|ECC]] support
| gpu            = [[Intel Graphics Technology]] (some models only) 
| co-processor   = [[Xeon Phi]] (2010–2020)
| pack1          = 
| sock1          = {{ubl |[[Slot 2]] |[[Socket 603]] |[[Socket 604]] |[[LGA 775]] |[[LGA 771]] |[[LGA 1156]] |[[LGA 1366]] |[[LGA 1155]] |[[LGA 2011]] |[[LGA 1150]] |[[LGA 2011|LGA 2011-3]] |[[LGA 1151]] |[[LGA 1151|LGA 1151v2]] |[[LGA 1200]] |[[LGA 1700]] |[[LGA 2066]] |[[LGA 3647]] |[[LGA 4189]] |[[LGA 4677]]|[[LGA 7529]]}}
<!--------- Products, models, variants ----------->
| core1          = 
| pcode1         = 
| model1         = 
| brand1         = {{ubl |Xeon E |Xeon D |Xeon w3<ref name="Xeon W series">{{cite web |title=Intel Launches New Xeon Workstation Processors – the Ultimate Solution for Professionals |url=https://www.intel.com/content/www/us/en/newsroom/news/intel-launches-new-xeon-workstation-processors.html#gs.qeb2cq |website=Intel |access-date=18 February 2023 |language=en}}</ref>|Xeon w5<ref name="Xeon W series" />|Xeon w7<ref name="Xeon W series" />| Xeon w9<ref name="Xeon W series" />|Xeon Bronze |Xeon Silver |Xeon Gold |Xeon Platinum |Xeon Max<ref>{{cite web |title=Intel Max Series Brings Breakthrough Memory Bandwidth and Performance to HPC and AI |url=https://www.intel.com/content/www/us/en/newsroom/news/introducing-intel-max-series-product-family.html#gs.l5ms7r |website=Intel Newsroom |language=en-US |date=November 9, 2022 |access-date=December 22, 2022}}</ref>}}
| variant        = [[Itanium]] (2001–2020)
<!------------------  History  ------------------->
| predecessor    = [[Pentium Pro]]
| successor      = 
| support status = Supported
}}

'''Xeon''' ({{IPAc-en|ˈ|z|iː|ɒ|n}}; {{respell|ZEE|on}}) is a brand of [[x86]] [[microprocessor]]s designed, manufactured, and marketed by [[Intel]], targeted at the non-consumer [[workstation]], [[Server (computing)|server]], and [[embedded system|embedded]] markets. It was introduced in June 29, 1998.<ref name=:0>{{cite web |title=Microprocessor Quick Reference Guide |url=https://www.intel.com/pressroom/kits/quickrefyr.htm#1998:~:text=Back%20to%20top-,June%2029%2C%201998,-Intel%C2%AE%20Pentium%C2%AE |website=Intel.com |publisher=Intel |access-date=18 June 2025 |quote=June 29, 1998 Intel® Pentium® II Xeon™ Processor 400 MHz}}</ref> Xeon processors are based on the same architecture as regular desktop-grade CPUs, but have advanced features such as support for [[ECC memory|error correction code (ECC) memory]], higher [[Multi-core processor|core]] counts, more [[PCI Express]] lanes, support for larger amounts of RAM, larger [[cache memory]] and extra provision for enterprise-grade [[reliability, availability and serviceability]] (RAS) features responsible for handling hardware exceptions through the [[Machine Check Architecture]] (MCA). They are often capable of safely continuing execution where a normal processor cannot due to these extra RAS features, depending on the type and severity of the [[machine-check exception]] (MCE). Some also support multi-socket systems with two, four, or eight sockets through use of the [[Intel Ultra Path Interconnect|Ultra Path Interconnect]] (UPI) bus, which replaced the older [[Intel QuickPath Interconnect|QuickPath Interconnect]] (QPI) bus.
[[File:Intel Xeon E5-1620, front and back.jpg|thumb|center|Intel Xeon E5-1620's front and back]]

== Branding ==
The ''Xeon'' brand has been maintained over several generations of [[IA-32]] and [[x86-64]] processors. The P6-based models added the ''Xeon'' moniker to the end of the name of their corresponding desktop processor, but all models since 2001 used the name ''Xeon'' on its own. The ''Xeon'' CPUs generally have more [[CPU cache|cache]] and [[Multi-core processor|cores]] than their desktop counterparts in addition to multiprocessing capabilities.

{{Multiple image|total_width = 300
| align             = center
| direction         = horizontal
| perrow            = 2 / 2
| width             = 150
| caption_align     = center
| image_gap         = 10

| header_align      = center
| header            = Xeon branding
| image1            = Intel Xeon (2020).svg
| width1            = 150
| alt1              = 
| caption1          = (2020–2023)

| image2            = Intel-Xeon-Badge-2024.jpg
| width2            = 150
| alt2              = 
| caption2          = (2024–present)
}}

=== Xeon Scalable ===
The Xeon Scalable brand for high-performance server was introduced in May 2017 with the Skylake-based Xeon Platinum 8100 series. Xeon Scalable processors range from dual socket to 8 socket support. Within the Xeon Scalable brand, there exists the hierarchy of Xeon Bronze, Silver, Gold and Platinum.

{{Multiple image|total_width = 600
| align             = center
| direction         = horizontal
| perrow            = 4 / 4
| width             = 150
| caption_align     = center
| image_gap         = 10

| header_align      = center
| header            = Xeon Scalable branding
| image1            = Intel-Xeon-Bronze-Badge-2017.png
| width1            = 150
| alt1              = 
| caption1          = Xeon Bronze <br/> (2017–2019)

| image2            = Intel-Xeon-Silver-Badge-2017.png
| width2            = 150
| alt2              = 
| caption2          = Xeon Silver <br/> (2017–2019)

| image3            = Intel-Xeon-Gold-Badge-2017.png
| width3            = 
| alt3              = 
| caption3          = Xeon Gold <br/> (2017–2019)

| image4            = Intel-Xeon-Platinum-Badge-2017.png
| width4            = 150
| alt4              = 
| caption4          = Xeon Platinum <br/> (2017–2019)

| image5            = Intel-Xeon-Bronze-Badge-2020.png
| width5            = 150
| alt5              = 
| caption5          = Xeon Bronze <br/> (2020–2023)

| image6            = Intel-Xeon-Silver-Badge-2020.png
| width6            = 150
| alt6              = 
| caption6          = Xeon Silver <br/> (2020–2023)

| image7            = Intel-Xeon-Gold-Badge-2020.png
| width7            = 150
| alt7              = 
| caption7          = Xeon Gold <br/> (2020–2023)

| image8            = Intel-Xeon-Platinum-Badge-2020.png
| width8            = 150
| alt8              = 
| caption8          = Xeon Platinum <br/> (2020–2023)
}}

In April 2024, Intel announced at its Vision event that the Xeon Scalable brand would be retired, beginning with 6th generation Xeon processors codenamed [[Sierra Forest]] and [[Granite Rapids]] that will now be referred to as "Xeon 6" processors.<ref>{{cite web |last=Chiapetta |first=Marco |date=April 9, 2024 |title=Intel Unveils Powerful, Efficient Gaudi 3 AI Accelerator And New Xeon 6 Processors At Vision 2024 |url=https://www.forbes.com/sites/marcochiappetta/2024/04/09/intel-unveils-efficient-gaudi-3-ai-accelerator-and-new-xeons-at-vision/ |website=Forbes |language=en-US |access-date=April 22, 2024}}</ref> This change brings greater emphasis on processor generation numbers.<ref>{{cite web |last=Bonshor |first=Gavin |date=April 9, 2024 |title=Intel Unveils New Branding For 6th Generation Xeon Processors: Intel Xeon 6 |url=https://www.anandtech.com/show/21339/intel-unveils-new-branding-for-6th-generation-xeon-processors-intel-xeon-6 |website=AnandTech |language=en-US |access-date=April 22, 2024}}</ref>

=== Xeon 6 ===
With the launch of Intel's [[Sierra Forest]] line of processors, branding for mainstream server processors switched to Xeon #, with the # being the generation of the processor, such as Xeon 6 for the 6th generation of Xeon processors, this naming convention also carries over to the Granite Rapids line of server CPUs.<ref name="Kennedy2024">{{Cite web |last=Kennedy |first=Patrick |date=2024-06-04 |title=Intel Xeon 6 6700E Sierra Forest Shatters Xeon Expectations |url=https://www.servethehome.com/intel-xeon-6-6700e-sierra-forest-shatters-xeon-expectations/ |access-date=2024-10-03 |website=ServeTheHome |language=en-US}}</ref> 

Xeon 6 is split into two product lines, the E series and P series, which, respectively, are all E core and all P core designs. For example, the Xeon 6 6700E line is an all [[Intel Core|E core]] based (Sierra Forest) line of processors.<ref name="Kennedy2024" />

=== Xeon D ===
[[Xeon D]] is targeted towards microserver and edge computing markets with lower power consumption and integrated I/O blocks such as [[Network interface controller|network interface controllers]]. This allows Xeon D processors to function as SoCs that do not require a separate southbridge PCH.<ref>{{cite web |title=Intel's Xeon brand makes its first foray into SoC space with Xeon D |url=https://arstechnica.com/information-technology/2015/03/intels-xeon-brand-makes-its-first-foray-into-soc-space-with-xeon-d/ |website=Ars Technica |language=en-US |date=March 10, 2015 |access-date=April 22, 2024}}</ref> It was announced in 2014 and the first Xeon D processors were released in March 2015. Xeon D processors come in an [[Solder ball|soldered]] [[Ball grid array|BGA]] package rather than in a socketable form factor. Xeon D was introduced to compete with emerging ARM hyperscale server solutions that offered greater multi-threaded performance and power effiency.<ref>{{cite news |last1=Prickett Morgan |first1=Timothy |date=March 9, 2015 |title=Intel Crafts Broadwell Xeon D For Hyperscale |url=https://www.nextplatform.com/2015/03/09/intel-crafts-broadwell-xeon-d-for-hyperscale/ |website=The Next Platform |language=en-US |access-date=April 22, 2024}}</ref>

=== Xeon W ===
[[Xeon W]] branding is used for Xeon workstation processors. It was first introduced in August 2017 with the release of the [[Skylake_(microarchitecture)#Workstation_processors|Skylake]]-based Xeon W-2100 series workstation processors. With Sapphire Rapids-WS workstation processors that launched in March 2023, Intel introduced tiers within Xeon W. Xeon w3, w5, w7 and w9 was designed to emulate the Core i3, i5, i7 and i9 branding that Intel had been using for its desktop processors.

== Overview ==
Some shortcomings that make Xeon processors unsuitable for most consumer-grade desktop PCs include lower [[clock rate]]s at the same price point (since servers run more tasks in parallel than desktops, core counts are more important than clock rates), and, usually, the lack of an integrated [[graphics processing unit]] (GPU). Processor models prior to [[Sapphire Rapids#Sapphire Rapids-WS (Workstation)|Sapphire Rapids-WS]] lack support for [[overclocking]] (with the exception of [[Skylake (microarchitecture)#Xeon High-end desktop processors (Skylake-X)|Xeon W-3175X]]). Despite such disadvantages, Xeon processors have always had popularity among some desktop users (video editors and other [[power user]]s), mainly due to higher core count potential, and higher performance to price ratio vs. the [[Core i7]] in terms of total computing power of all cores. Since most Intel Xeon CPUs lack an integrated [[graphics processing unit|GPU]], systems built with those processors require a discrete graphics card or a separate GPU if [[computer monitor]] output is desired.

Intel Xeon is a distinct product line from the similarly named Intel [[Xeon Phi]]. The first-generation Xeon Phi is a completely different type of device more comparable to a graphics card; it is designed for a [[PCI Express]] slot and is meant to be used as a multi-core coprocessor, like the [[Nvidia Tesla]]. In the second generation, Xeon Phi evolved into a main processor more similar to the Xeon. It conforms to the same socket as a Xeon processor and is x86-compatible; however, as compared to Xeon, the design point of the Xeon Phi emphasizes more cores with higher memory bandwidth.

{| class="wikitable" style="border:0; font-size:90%; background:white"
|+ Intel Xeon processor family: [[Server (computing)|Server]]
|-
! width="10px!" style="background-color: #FFF; border-width:0;" |
! colspan="3" style="background-color:#dff;" | 1 or 2 Sockets<br /><small>UP/DP/3000/5000/E3/E5-1xxx and 2xxx/E7-2xxx/D/E/W series<br/>Bronze/Silver/Gold (non H)/Platinum (non H)/Max</small>
! colspan="3" style="background-color:#dff;" | 4 or 8 Sockets<br /><small>MP/7000/E5-4xxx/E7-4xxx and 8xxx series</small><small>Gold (H)/Platinum (H)</small>
|-
! style="text-align:left; vertical-align: bottom;" | <div style="{{Transform-rotate|-90}}; width:12px !important;">Node</div> || Code named                               || # of<br>Cores                    || Release<br />date || Code named                               || # of<br>Cores                    || Release<br />date
|---- style="background-color:#F8EEDD;"
| rowspan="2" style="text-align:left; vertical-align: bottom;" | <div style="{{Transform-rotate|-90}}; width:12px !important;">'''250&nbsp;nm'''</div>
| colspan="3" rowspan="2" style="background-color: #FFF;" |                 || <abbr title="Pentium II based">Drake</abbr>            || 1                                || Jun 1998
|---- style="background-color:#F8EEDD;"
|                                                                                                                         Tanner                                   || 1                                || Mar 1999
|---- style="background-color:#FFF8EE;"
| rowspan="2" style="text-align:left; vertical-align: bottom;" | <div style="{{Transform-rotate|-90}}; width:12px !important;">'''180&nbsp;nm'''</div>
|        Cascades (256 KB L2 cache)              || 1                                || Oct 1999  ||   Cascades (700 and 900&nbsp;MHz models only)                      || 1                                || May&nbsp;2000
|---- style="background-color:#FFF8EE;"
| <abbr title="Pentium 4 based">Foster</abbr>                             || 1                                || May&nbsp;2001     || <abbr title="Pentium 4 based">Foster MP</abbr>                 || 1                                || Mar 2002
|---- style="background-color:#F8F6F8;"
| rowspan="2" style="text-align:left; vertical-align: bottom;" | <div style="{{Transform-rotate|-90}}; width:12px !important;">'''130&nbsp;nm'''</div>
| Prestonia                                || 1                                || Feb 2002     || colspan="3" style="background-color: #FFF; border-width:0;"|
|---- style="background-color:#F8F6F8;"
|                         Gallatin DP                              || 1                                || Jul 2003     || Gallatin                                 || 1                                || Nov&nbsp;2002
|---- style="background-color:#EEF6EE;"
| rowspan="4" style="text-align:left; vertical-align:center;" | <div style="{{Transform-rotate|-90}}; width:12px !important;">'''90&nbsp;nm'''</div>
| <abbr title="64 bit Architecture">Nocona</abbr>                             || 1               || Jun 2004    
|| <abbr title="64 bit Architecture">Cranford</abbr>                           || 1   || Mar 2005 
|---- style="background-color:#EEF8EE;"
| colspan="3" style="background-color: #FFF;" |                                                                       || Potomac                                  || 1                                || Mar 2005
|---- style="background-color:#EEF8EE;"
|                         <abbr title="64 bit Architecture">Irwindale</abbr>                          || 1                                                             || Feb 2005     || colspan="3" style="background-color: #FFF; border-width:0;" |
|---- style="background-color:#EEF8EE;"
|                         Paxville DP                              || 2                                || Oct 2005     || Paxville                                 || 2                                || Nov 2005
|---- style="background-color:#EEF8F8;"
| rowspan="7" style="text-align:left; vertical-align: center;" | <div style="{{Transform-rotate|-90}}; width:12px !important;">'''65&nbsp;nm'''</div>
| Dempsey                                  || 2                                || May 2006     || Tulsa                                    || 2                                || Aug 2006
|---- style="background-color:#EEF8F8;"
|                         Sossaman                                 || 2                                || Mar 2006 || colspan="3" rowspan="3" style="background-color: #FFF; border-width:0;" |
|---- style="background-color:#EEF8F8;"
|                         Woodcrest                                || 2                                || Jun 2006     
|---- style="background-color:#EEF8F8;"
|                         Conroe                                   || 2                                || Oct 2006     
|---- style="background-color:#EEF8F8;"
|                         Clovertown                               || 4                                || Nov 2006 || Tigerton/Tigerton QC                                 || 2/4                                || Sep 2007
|---- style="background-color:#EEF8F8;"
|                         Allendale                                || 2                                || Jan 2007 || colspan="3" rowspan="3" style="background-color: #FFF; border-width:0;" |
|---- style="background-color:#EEF8F8;"
|                         Kentsfield                               || 4                                || Jan 2007     
|---- style="background-color:#EEF5FF;"
| rowspan="8" style="text-align:left; vertical-align: center;" | <div style="{{Transform-rotate|-90}}; width:12px !important;">'''45&nbsp;nm'''</div>
| Wolfdale DP                              || 2                                || Nov 2007     
|---- style="background-color:#EEF5FF;"
|                         Harpertown                               || 4                                || Nov 2007 || Dunnington QC/Dunnington                               || 4/6                              || Sep 2008
|---- style="background-color:#EEF5FF;"
|                         Wolfdale                                 || 2                                || Feb 2008 || colspan="3" rowspan="5" style="background-color: #FFF; border-width:0;" |
|---- style="background-color:#EEF5FF;"
|                         Yorkfield                                || 4                                || Mar 2008     
|---- style="background-color:#EEF5FF;"
|                         Bloomfield (W35xx)                         || 4                                || Mar 2009
|---- style="background-color:#EEF5FF;"
|                         Gainestown (55xx)                         || 2/4                              || Mar 2009 
|---- style="background-color:#EEF5FF;"
|                         Lynnfield (34xx)                         || 4                                || Sep 2009
|---- style="background-color:#EEF5FF;"
|                         Beckton (65xx)                     || 4/6/8                            || Mar 2010     || Beckton (75xx)                     || 4-8                            || Mar 2010
|---- style="background-color:#EEEEFF;"
| rowspan="5" style="text-align:left; vertical-align: center;" | <div style="{{Transform-rotate|-90}}; width:12px !important;">'''32&nbsp;nm'''</div>
| Westmere-EP (56xx)                 || 2-6                            || Mar 2010        || colspan="3" rowspan="3" style="background-color: #FFF; border-width:0;" |
|---- style="background-color:#EEEEFF;"
| Gulftown (W36xx)               || 6                              || Mar 2010
|---- style="background-color:#EEEEFF;"
| Clarkdale (L34xx)               || 2                              || Mar 2010
|---- style="background-color:#EEEEFF;"
| Westmere-EX (E7-2xxx)              || 6-10                           || Apr 2011     || Westmere-EX (E7-4xxx/8xxx)         || 6-10                           || Apr 2011
|---- style="background-color:#EEEEFF;"
|                         Sandy Bridge-DT/EN/EP                          || 2-8                          || Mar 2012     || Sandy Bridge-EP (E5-46xx)          || 4-8                            || May 2012
|---- style="background-color:#F8ECFC;"
| rowspan="4" style="text-align:left; vertical-align:center;" | <div style="{{Transform-rotate|-90}}; width:12px !important;">'''22&nbsp;nm'''</div>
| Ivy Bridge (E3/E5-1xxx/E5-2xxx v2) || 2-12                    || Sep 2013     || Ivy Bridge-EP (E5-46xx v2)         || 4-12                      || Mar 2014
|---- style="background-color:#F8ECFC;"
|                         Ivy Bridge-EX (E7-28xx v2)         || 12/15                            || Feb 2014     || Ivy Bridge-EX (E7-48xx/88xx v2)    || 6-12/15                     || Feb 2014
|---- style="background-color:#F8ECFC;"
|                         Haswell (E3/E5-1xxx/E5-2xxx v3)    || 2-18                    || Sep 2014     || Haswell-EP (E5-46xx v3)            || 6-18                || Jun 2015
|---- style="background-color:#F8ECFC;"
| colspan="3" style="background-color: #FFF;" |                                                              || Haswell-EX (E7-48xx/88xx v3)       || 4-18                 || May 2015
|---- style="background-color:#F8EEDD;"
| rowspan="6" style="text-align:left; vertical-align:center;" | <div style="{{Transform-rotate|-90}}; width:12px !important;">'''14&nbsp;nm'''</div>
|                         Broadwell (E3/E5-1xxx/E5-2xxx v4)  || 4-22                    || Jun 2015     || colspan="3" style="background-color: #FFF; border-width:0;" rowspan="3" |
|---- style="background-color:#F8EEDD;"
|                         Skylake-S/H (E3-1xxx v5)                 || 4                       || Oct 2015
|---- style="background-color:#F8EEDD;"
|                         Kaby Lake-S/H (E3-1xxx v6)               || 4                       || Mar 2017
|---- style="background-color:#F8EEDD;"
|                         Skylake-W/SP (Bronze and Silver) || 4-28 || Jun 2017 || Skylake-SP (Gold and Platinum) || 4-28 || Jul 2017
|---- style="background-color:#F8EEDD;"
|     {{nowrap|Cascade Lake-W/SP (Bronze/Silver/R/U)}} || 4-28 || Apr 2019 || {{nowrap|Cascade Lake-SP (Gold (non-R/U)/Platinum)}} || 4-28 || Apr 2019
|---- style="background-color:#F8EEDD;"
| colspan="3" style="background-color: #FFF;" |               || Cooper Lake-SP || 8-28 || Jun 2020
|---- style="background-color:#FAF2C8;"
| rowspan="2" style="text-align:left; vertical-align:bottom;" | <div style="{{Transform-rotate|-90}}; width:12px !important;">'''10&nbsp;nm'''</div>
| Ice Lake-SP/W || 8-40 || Apr 2021 || colspan="3" rowspan="2" style="background-color: #FFF; border-width:0;" |
|---- style="background-color:#FAF2C8;"
| Ice Lake-D || 2-20 || Feb 2022 
|---- style="background-color:#FDFFC2;" 
| rowspan="2" | <div style="{{Transform-rotate|-90}}; width:12px !important;">'''Intel&nbsp;7'''</div> || Sapphire Rapids-SP/WS/HBM || 6-56 || Jan 2023 || Sapphire Rapids-SP || 8-60 || Jan 2023
|---- style="background-color:#FDFFC2;"
| Emerald Rapids-SP || 8-64 || Dec 2023 || colspan="3" style="background-color: #FFF; border-width:0;" |
|----
! colspan="7" | [[List of Intel Xeon processors]]
|}

==P6-based Xeon==

==={{Anchor|Drake}}Pentium II Xeon===
{{main|List of Intel P6-based Xeon microprocessors#"Drake" (250 nm)}}
[[File:Pentium II Xeon 450 512.jpg|thumb|upright=1.4|left|450 MHz Pentium II Xeon with 512&nbsp;KB L2 cache: The cartridge cover has been removed.]]
The first Xeon-branded processor was the Pentium II Xeon (code-named "'''Drake'''"). It was released in 1998, replacing the [[Pentium Pro]] in Intel's high-end server lineup. The Pentium II Xeon was a "''[[Deschutes (microprocessor)|Deschutes]]''" [[Pentium II]] (and shared the same product code: 80523) with a full-speed 512&nbsp;kB (1&nbsp;kB = 1024 B), 1&nbsp;MB (1&nbsp;MB = 1024&nbsp;kB = 1024<sup>2</sup> B), or 2&nbsp;MB [[CPU cache|L2 cache]]. The L2 cache was implemented with custom 512&nbsp;kB SRAMs developed by Intel. The number of SRAMs depended on the amount of cache. A 512&nbsp;kB configuration required one SRAM, a 1&nbsp;MB configuration: two SRAMs, and a 2&nbsp;MB configuration: four SRAMs on both sides of the PCB. Each SRAM was a 12.90&nbsp;mm by 17.23&nbsp;mm (222.21&nbsp;mm{{sup|2}}) die fabricated in a 0.35&nbsp;μm four-layer metal CMOS process and packaged in a cavity-down wire-bonded [[land grid array]] (LGA).<ref>{{cite conference |last=Bateman |first=B. |title=A 450MHz 512 kB Second-Level Cache with a 3.6GB/s Data Bandwidth |conference=[[International Solid-State Circuits Conference]] | date=February 1998 |pages=358–359 |doi=10.1109/ISSCC.1998.672528 |isbn=0-7803-4344-1 |s2cid=21384417 |display-authors=etal}}</ref> The additional cache required a larger module and thus the Pentium II Xeon used a larger slot, [[Slot 2]]. It was supported by the [[Intel 440GX|i440GX]] dual-processor workstation [[chipset]] and the [[Intel 450NX|i450NX]] quad- or octo-processor server chipset.

==={{Anchor|Tanner|Cascades}}Pentium III Xeon===
{{main|List of Intel P6-based Xeon microprocessors#"Tanner" (250 nm)|List of Intel P6-based Xeon microprocessors#"Cascades" (180 nm)|l2=§ "Cascades" (180 nm)}}
[[File:Intel Pentium III Xeon 550 MHz Slot 2 geoeffnet.jpg|thumb|Back of a Pentium III Xeon with its cover set aside; there is a heatsink on the front side (underneath) of the circuit board.]]
[[File:Intel pentium iii xeon 800 sl4h8 observe.png|thumb|Front of a Pentium III Xeon circuit board without its heatsink]]
[[File:Intel@180nm@P6@Cascades@Pentium III Xeon@SL4XW DSCx1 polysilicon microscope stitched@5x (24203772488).jpg|thumb|Die shot of a Cascades Pentium III Xeon]]
In 1999, the [[Pentium II]] Xeon was replaced by the [[Pentium III]] Xeon. Reflecting the incremental changes from the Pentium II "''[[Deschutes (microprocessor)|Deschutes]]''" core to the Pentium III "''[[Katmai (microprocessor)|Katmai]]''" core, the first Pentium III Xeon, named "'''Tanner'''", was just like its predecessor except for the addition of [[Streaming SIMD Extensions]] (SSE) and a few cache controller improvements. The product codes for '''Tanner''' mirrored that of ''Katmai''; 80525.

The second version, named "'''Cascades'''", was based on the Pentium III "''[[Coppermine (microprocessor)|Coppermine]]''" core. The "'''Cascades'''" Xeon used a 133&nbsp;MT/s front side bus and relatively small 256&nbsp;kB on-die L2 cache resulting in almost the same capabilities as the [[Slot 1]] ''Coppermine'' processors, which were capable of dual-processor operation but not quad-processor or octa-processor operation.

To improve this situation, Intel released another version, officially also named "'''Cascades'''", but often referred to as "'''Cascades 2&nbsp;MB'''". That came in two variants: with 1&nbsp;MB or 2&nbsp;MB of L2 cache. Its bus speed was fixed at 100&nbsp;MT/s, though in practice the cache was able to offset this. The product code for '''Cascades''' mirrored that of ''Coppermine''; 80526.

== NetBurst-based Xeon {{anchor|Netburst-based Xeon}} ==
=== Xeon (DP) and Xeon MP (32-bit) ===
==== Foster ====
{{main|List of Intel NetBurst-based Xeon microprocessors#"Foster" (180 nm)|List of Intel NetBurst-based Xeon microprocessors#"Foster MP" (180 nm)|l2=§ "Foster MP" (180 nm)}}
In mid-2001, the Xeon brand was introduced ("Pentium" was dropped from the name). The initial variant that used the new [[NetBurst|NetBurst microarchitecture]], "'''Foster'''", was slightly different from the desktop [[Pentium 4]] ("''[[Pentium 4#Willamette|Willamette]]''"). It was a decent{{Clarify|date=March 2017}} chip for workstations, but for server applications it was almost always outperformed by the older Cascades cores with a 2&nbsp;MB L2 cache and AMD's [[Athlon|Athlon MP]]{{Examples|date=March 2017}}. Combined with the need to use expensive [[RDRAM|Rambus Dynamic RAM]], the Foster's sales were somewhat unimpressive{{Examples|date=March 2017}}.

At most two Foster processors could be accommodated in a [[symmetric multiprocessing]] (SMP) system built with a mainstream chipset, so a second version ('''Foster MP''') was introduced with 512&nbsp;KB or 1&nbsp;MB L3 cache and the Jackson [[Hyper-threading|Hyper-Threading]] capacity. This improved performance slightly, but not enough to lift it out of third place. It was also priced much higher than the dual-processor (DP) versions. The ''Foster'' shared the 80528 product code with Willamette.

==== Prestonia ====
{{main|List of Intel NetBurst-based Xeon microprocessors#"Prestonia" (130 nm)}}
In 2002 Intel released a [[130 nanometer|130&nbsp;nm]] version of Xeon branded CPU, codenamed "'''Prestonia'''". It supported Intel's new Hyper-Threading technology and had a 512&nbsp;kB L2 cache. This was based on the "''[[Pentium 4#Northwood|Northwood]]''" Pentium 4 core. A new server chipset, [[Intel Xeon chipsets#NetBurst-based Xeon chipsets|E7500]] (which allowed the use of dual-channel [[DDR SDRAM]]), was released to support this processor in servers, and soon the bus speed was boosted to 533&nbsp;MT/s (accompanied by a new socket and two new chipsets: the E7501 for servers and the E7505 for workstations). The ''Prestonia'' performed much better than its predecessor and noticeably better than Athlon MP. The support of new features in the E75xx series also gave it a key advantage over the Pentium III Xeon and Athlon MP branded CPUs (both stuck with rather old chipsets), and it quickly became the top-selling server/workstation processor.

==== {{Anchor|Gallatin}} Gallatin ====
{{Infobox CPU
| name           = Gallatin
| image =Xeon_DP_Gallatin_(SL7AE),_Socket_604.jpg
| caption        =
| produced-start = March 2003
| produced-end   = 2004
| slowest        = 1.50
| fastest        = 3.20
| slow-unit      = GHz
| fast-unit      = GHz
| fsb-slowest    = 400
| fsb-fastest    = 533
| fsb-slow-unit  = MT/s
| fsb-fast-unit  = MT/s
| size-from      = 130&nbsp;nm
| size-to        =
| soldby         =
| designfirm     =
| manuf1         =
| core1          =
| sock1          =
| pack1          = [[Socket 603]] [[Socket 604]]
| code           = 80537
| cpuid          = 0F7x
| brand1         = Xeon
| arch           = [[x86-16]], [[IA-32]]
| microarch      = [[NetBurst]]
| numcores       = 1
| l1cache        = 8 kB + 12 kuOps trace cache
| l2cache        = 512&nbsp;kB
| l3cache        = 1 MB, 2&nbsp;MB, 4&nbsp;MB
| application    = DP and MP Server
}}
{{main|List of Intel NetBurst-based Xeon microprocessors#"Gallatin" (130 nm)|List of Intel NetBurst-based Xeon microprocessors#"Gallatin" (130 nm) 2|l2=§ "Gallatin" MP (130 nm)}}
Subsequent to the ''Prestonia'' was the "'''Gallatin'''", which had an L3 cache of 1&nbsp;MB or 2&nbsp;MB. Its Xeon MP version, which succeeded ''Foster MP'', was popular in servers. Later experience with the 130&nbsp;nm process allowed Intel to create the Xeon MP branded ''Gallatin'' with 4&nbsp;MB cache. The Xeon branded ''Prestonia'' and ''Gallatin'' were designated 80532, like Northwood.

===Xeon (DP) and Xeon MP (64-bit)===

====Nocona and Irwindale====
{{main|Pentium 4#Prescott|List of Intel NetBurst-based Xeon microprocessors#"Nocona" (90 nm)|List of Intel NetBurst-based Xeon microprocessors#"Irwindale" (90 nm)|l3=§ "Irwindale" (90 nm)}}

Due to a lack of success with Intel's [[Itanium]] and Itanium 2 processors, AMD was able to introduce [[x86-64]], a 64-bit extension to the [[x86 architecture]]. Intel followed suit by including [[Intel 64]] (formerly EM64T; it is almost identical to [[AMD64]]) in the [[90 nanometer|90&nbsp;nm]] version of the Pentium 4 ("''[[Pentium 4#Prescott|Prescott]]''"), and a Xeon version codenamed "'''Nocona'''" with 1&nbsp;MB L2 cache was released in 2004. Released with it were the E7525 (workstation), E7520 and E7320 (both server) chipsets, which added support for [[PCI Express#PCI Express 1.0a|PCI Express 1.0a]], [[DDR2 SDRAM|DDR2]] and [[SATA#SATA revision 1.0 (1.5 Gbit/s, 150 MB/s, Serial ATA-150)|Serial ATA 1.0a]]. The Xeon was noticeably slower than AMD's Opteron, although it could be faster in situations where Hyper-Threading came into play.

A slightly updated core called "'''Irwindale'''" was released in early 2005, with 2&nbsp;MB L2 cache and the ability to have its clock speed reduced during low processor demand. Although it was a bit more competitive than the ''Nocona'' had been, independent [https://web.archive.org/web/20051228212744/http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2591 tests] showed that AMD's Opteron still outperformed ''Irwindale''. Both of these Prescott-derived Xeons have the product code 80546.

==== Cranford and Potomac ====
{{main|Pentium 4#Prescott|List of Intel NetBurst-based Xeon microprocessors#"Cranford" (90 nm)|List of Intel NetBurst-based Xeon microprocessors#"Potomac" (90 nm)|l3=§ "Potomac" (90 nm)}}

64-bit Xeon MPs were introduced in April 2005. The cheaper "'''Cranford'''" was an MP version of ''Nocona'', while the more expensive "'''Potomac'''" was a ''Cranford'' with 8&nbsp;MB of L3 cache. Like Nocona and Irwindale, they also have product code 80546.

=== Dual-Core Xeon ===
==== "Paxville DP" ====
{{main|List of Intel NetBurst-based Xeon microprocessors#"Paxville DP" (90 nm)|Pentium D#Smithfield}}
{{Infobox CPU
| name           = Paxville
| image          =
| image_size     =
| caption        =
| produced-start = October 2005
| produced-end   = August 2008
| slowest        = 2.667
| fastest        = 3.0
| slow-unit      = GHz
| fast-unit      = GHz
| fsb-slowest    = 667
| fsb-fastest    = 800
| fsb-slow-unit  = MT/s
| fsb-fast-unit  = MT/s
| size-from      = 90&nbsp;nm
| size-to        =
| soldby         =
| designfirm     =
| manuf1         =
| core1          =
| sock1          =
| pack1          = [[Socket 604]]
| code           = 80551, 80560
| cpuid          = 0F48
| brand1         = Xeon
| arch           = [[x86-16]], [[IA-32]], [[x86-64]]
| microarch      = [[NetBurst]]
| numcores       = 2
| l1cache        =
| l2cache        = 2×2&nbsp;MB
| l3cache        =
| application    = DP Server, MP Server
}}

The first [[Multi-core (computing)|dual-core]] CPU branded Xeon, codenamed '''Paxville DP''', product code 80551, was released by Intel on October 10, 2005. Paxville DP had [[NetBurst|NetBurst microarchitecture]], and was a dual-core equivalent of the single-core [[#Nocona and Irwindale|Irwindale]] (related to the [[Pentium D]] branded "[[Pentium D#Smithfield|Smithfield]]") with 4&nbsp;MB of L2 cache (2&nbsp;MB per core). The only Paxville DP model released ran at 2.8&nbsp;GHz, featured an 800&nbsp;MT/s front side bus, and was produced using a [[90 nanometer|90&nbsp;nm process]].

==== 7000-series "Paxville MP" ====
{{main|List of Intel NetBurst-based Xeon microprocessors#"Paxville MP" (90 nm)}}
An MP-capable version of Paxville, codenamed '''Paxville MP''', product code 80560, was released on November 1, 2005. There are two versions: one with 2&nbsp;MB of L2 cache (1&nbsp;MB per core), and one with 4&nbsp;MB of L2 (2&nbsp;MB per core). Paxville MP, called the dual-core Xeon 7000-series, was produced using a 90&nbsp;nm process. Paxville MP clock ranges between 2.67&nbsp;GHz and 3.0&nbsp;GHz (model numbers 7020–7041), with some models having a 667&nbsp;MT/s FSB, and others having an 800&nbsp;MT/s FSB.

{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed
! scope="col" | L2 cache
! scope="col" | FSB
! scope="col" | TDP
|-
| 7020
| 2.66&nbsp;GHz
| rowspan="2" | 2&nbsp;×&nbsp;1&nbsp;MB
| 667&nbsp;MT/s
| rowspan="4" | 165 W
|-
| 7030
| 2.80&nbsp;GHz
| 800&nbsp;MT/s
|-
| 7040
| rowspan="2" | 3.00&nbsp;GHz
| rowspan="2" | 2&nbsp;×&nbsp;2&nbsp;MB
| 667&nbsp;MT/s
|-
| 7041
| 800&nbsp;MT/s
|}

====7100-series "Tulsa"====
{{main|List of Intel NetBurst-based Xeon microprocessors#"Tulsa" (65 nm)}}
{{Infobox CPU
| name           = Tulsa
| image          =
| image_size     =
| caption        =
| produced-start = August 2006
| produced-end   = August 2008
| slowest        = 2.50
| fastest        = 3.50
| slow-unit      = GHz
| fast-unit      = GHz
| fsb-slowest    = 667
| fsb-fastest    = 800
| fsb-slow-unit  = MT/s
| fsb-fast-unit  = MT/s
| size-from      = 65&nbsp;nm
| size-to        =
| soldby         =
| designfirm     =
| manuf1         =
| core1          =
| sock1          =
| pack1          = [[Socket 604]]
| code           = 80550
| cpuid          = 0F68
| brand1         = Xeon 71xx
| arch           = [[x86-16]], [[IA-32]], [[x86-64]]
| microarch      = [[NetBurst]]
| numcores       = 2
| l1cache        =
| l2cache        = 2×1&nbsp;MB
| l3cache        = 16&nbsp;MB
| application    = MP Server
}}

Released on August 29, 2006,<ref>{{cite press release|url=https://newsroom.intel.com/news-releases/new-high-end-intel-server-processors-expand-performance-leadership|title=New High-End Intel Server Processors Expand Performance Leadership|publisher=Intel|date=August 29, 2006}}</ref> the 7100 series, codenamed '''Tulsa''' (product code 80550), is an improved version of Paxville MP, built on a 65&nbsp;nm process, with 2&nbsp;MB of L2 cache (1&nbsp;MB per core) and up to 16&nbsp;MB of L3 cache. It uses [[Socket 604]].<ref>{{cite web|url=https://www.intel.com/Assets/PDF/specupdate/314554.pdf|title=Intel Xeon Processor 7100 Series Specification Update|date=March 2010|website=Intel}}</ref> Tulsa was released in two lines: the N-line uses a 667&nbsp;MT/s FSB, and the M-line uses an 800&nbsp;MT/s FSB. The N-line ranges from 2.5&nbsp;GHz to 3.5&nbsp;GHz (model numbers 7110N-7150N), and the M-line ranges from 2.6&nbsp;GHz to 3.4&nbsp;GHz (model numbers 7110M-7140M). L3 cache ranges from 4&nbsp;MB to 16&nbsp;MB across the models.<ref>{{cite web|url=http://www.theinquirer.net/default.aspx?article=31990|title=Intel prices up Woodcrest, Tulsa server chips|website=The Inquirer|date=May 26, 2006|url-status=unfit|archive-url=https://web.archive.org/web/20070103213811/http://www.theinquirer.net/default.aspx?article=31990|archive-date=January 3, 2007}}</ref>

{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed
! scope="col" | L2 cache
! scope="col" | L3 cache
! scope="col" | FSB
! scope="col" | TDP
|-
| 7110N
| 2.50&nbsp;GHz
| rowspan="9" | 2 MB
| rowspan="4" | 4 MB
| 667&nbsp;MT/s
| rowspan="4" | {{0}}95 W
|-
| 7110M
| 2.60&nbsp;GHz
| 800&nbsp;MT/s
|-
| 7120N
| rowspan="2" | 3.00&nbsp;GHz
| 667&nbsp;MT/s
|-
| 7120M
| 800&nbsp;MT/s
|-
| 7130N
| 3.16&nbsp;GHz
| rowspan="2" | 8 MB
| 667&nbsp;MT/s
| rowspan="5" | 150 W
|-
| 7130M
| 3.20&nbsp;GHz
| 800&nbsp;MT/s
|-
| 7140N
| 3.33&nbsp;GHz
| rowspan="3" | 16 MB
| 667&nbsp;MT/s
|-
| 7140M
| 3.40&nbsp;GHz
| 800&nbsp;MT/s
|-
| 7150N
| 3.50&nbsp;GHz
| 667&nbsp;MT/s
|}

==== {{Anchor|Dempsey}}5000-series "Dempsey" ====
{{main|List of Intel NetBurst-based Xeon microprocessors#"Dempsey" (65 nm)}}
{{Infobox CPU
| name           = Dempsey
| image          =
| image_size     =
| caption        =
| produced-start = May 2006
| produced-end   = August 2008
| slowest        = 2.50
| fastest        = 3.73
| slow-unit      = GHz
| fast-unit      = GHz
| fsb-slowest    = 667
| fsb-fastest    = 1066
| fsb-slow-unit  = MT/s
| fsb-fast-unit  = MT/s
| size-from      = 65nm
| size-to        =
| soldby         =
| designfirm     =
| manuf1         =
| core1          =
| sock1          =
| pack1          = [[LGA 771]]
| brand1         = Xeon 50xx
| arch           = [[x86-16]], [[IA-32]], [[x86-64]]
| microarch      = [[NetBurst]]
| numcores       = 2
| l1cache        =
| l2cache        = 4&nbsp;MB
| l3cache        =
| application    = DP Server
}}

On May 23, 2006, Intel released the dual-core CPU (Xeon branded 5000 series) codenamed '''Dempsey''' (product code 80555). Released as the Dual-Core Xeon 5000-series, Dempsey is a [[NetBurst|NetBurst microarchitecture]] processor produced using a [[65 nanometer|65&nbsp;nm process]], and is virtually identical to Intel's "[[Pentium D#Presler|Presler]]" [[Pentium Extreme Edition]], except for the addition of SMP support, which lets Dempsey operate in dual-processor systems. Dempsey ranges between 2.50&nbsp;GHz and 3.73&nbsp;GHz (model numbers 5020–5080). Some models have a 667&nbsp;MT/s FSB, and others have a 1066&nbsp;MT/s FSB. Dempsey has 4&nbsp;MB of L2 cache (2&nbsp;MB per core). A Medium Voltage model, at 3.2&nbsp;GHz and 1066&nbsp;MT/s FSB (model number 5063), has also been released. Dempsey also introduces a new interface for Xeon processors: [[LGA 771]], also known as '''Socket J'''. Dempsey was the first Xeon core in a long time to be somewhat competitive with its Opteron-based counterparts, although it could not claim a decisive lead in any performance metric – that would have to wait for its successor, the Woodcrest.

{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed (GHz)
! scope="col" | L2 cache
! scope="col" | FSB
! scope="col" | TDP
|-
| 5020
| 2.50 GHz
| rowspan="8" | 2&nbsp;×&nbsp;2&nbsp;MB
| rowspan="4" | 667 MT/s
| rowspan="4" | 95 W
|-
| 5030
| 2.66 GHz
|-
| 5040
| 2.83 GHz
|-
| 5050
| 3.00 GHz
|-
| 5060
| rowspan="2" | 3.20 GHz
| rowspan="4" | 1.07 GT/s
| 130 W
|-
| 5063
| 95 W
|-
| 5070
| 3.46 GHz
| rowspan="2" | 130 W
|-
| 5080
| 3.73 GHz
|}

== Pentium M (Yonah) based Xeon ==
=== {{Anchor|Sossaman}}LV (ULV), "Sossaman" ===
{{main|List of Intel Pentium M (Yonah)-based Xeon microprocessors#"Sossaman" (65 nm)}}
{{Infobox CPU
| name           = Sossaman
| image =2.00_GHz_Xeon_LV_Sossaman_processor.jpg
| caption        =
| produced-start = 2006
| produced-end   = 2008
| slowest        = 1.667
| slow-unit      = GHz
| fastest        = 2.167
| fast-unit      = GHz
| fsb-slowest    = 667
| fsb-fastest    =
| fsb-slow-unit  = MT/s
| fsb-fast-unit  = MT/s
| size-from      = 65&nbsp;nm
| size-to        =
| soldby         =
| designfirm     =
| manuf1         =
| core1          =
| sock1          =
| pack1          = [[Socket M]]
| code           = 80539
| cpuid          = 06Ex
| brand1         = Xeon
| arch           = [[x86-16]], [[IA-32]], [[x86-64]]
| microarch      = [[Enhanced Pentium M (microarchitecture)|Enhanced Pentium M]]
| numcores       = 2
| l1cache        =
| l2cache        = 2&nbsp;MB
| l3cache        =
| application    = DP Server
}}

On March 14, 2006, Intel released a dual-core processor codenamed '''Sossaman''' and branded as ''Xeon'' LV (low-voltage). Subsequently, an ULV (ultra-low-voltage) version was released. The ''Sossaman'' was a low-/ultra-low-power and double-processor capable CPU (like [[AMD Quad FX platform|AMD Quad FX]]), based on the "''[[Yonah (microprocessor)|Yonah]]''" processor, for ultradense non-consumer environment (i.e., targeted at the blade-server and embedded markets), and was rated at a [[Thermal Design Power|thermal design power]] (TDP) of 31 W (LV: 1.66&nbsp;GHz, 2&nbsp;GHz and 2.16&nbsp;GHz) and 15 W (ULV: 1.66&nbsp;GHz).<ref>{{cite web |title=Intel drops 32-bit dual-core LV processors |url=http://www.tgdaily.com/content/view/33150/135/ |publisher=TG Daily |access-date=July 31, 2007}}</ref> As such, it supported most of the same features as earlier Xeons: Virtualization Technology, 667&nbsp;MT/s front side bus, and dual-core processing, but did not support 64-bit operations, so it could not run 64-bit server software, such as [[Microsoft Exchange Server]] 2007, and therefore was limited to 16&nbsp;GB of memory. A planned successor, codenamed "''[[Merom (microprocessor)|Merom]] MP''" was to be a drop-in upgrade to enable ''Sossaman''-based servers to upgrade to 64-bit capability. However, this was abandoned in favor of low-voltage versions of the ''[[#5100-series "Woodcrest"|Woodcrest LV]]'' processor leaving the ''Sossaman'' at a dead-end with no upgrade path.

{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed
! scope="col" | L2 cache
! scope="col" | FSB
! scope="col" | TDP
|-
| ULV 1.66
| rowspan="2" | 1.66 GHz
| rowspan="4" | 2 MB
| rowspan="4" | 667 MT/s
| 15 W
|-
| LV 1.66
| rowspan="3" | 31 W
|-
| LV 2.00
| 2.00 GHz
|-
| LV 2.16
| 2.16 GHz
|}

== Core-based Xeon ==
=== Dual-Core ===
==== {{Anchor|Conroe}}3000-series "Conroe" ====
{{main|Conroe (microprocessor)|List of Intel Core-based Xeon microprocessors#"Conroe" (65 nm)}}
The 3000 series, codenamed '''Conroe''' (product code 80557) dual-core Xeon (branded) CPU,<ref>{{cite web |last=Huynh |first=Anh Tuan |date=July 19, 2006 |title=Intel Adds Low End Xeons to Roadmap |url=http://www.dailytech.com/article.aspx?newsid=3381 |website=DailyTech |archive-url=https://web.archive.org/web/20160402063126/http://www.dailytech.com/article.aspx?newsid=3381 |archive-date=April 2, 2016 |url-status=dead}}</ref> released at the end of September 2006, was the first Xeon for single-CPU operation and is designed for entry-level uniprocessor servers. The same processor is branded as [[Intel Core 2|Core 2 Duo]] or  as [[Pentium Dual-Core]] and [[Celeron]], with varying features disabled. They use [[LGA 775]] (Socket T), operate on a 1066&nbsp;MT/s front-side bus, support Enhanced Intel [[SpeedStep]] Technology and Intel Virtualization Technology but do not support hyper-threading. Conroe processors with a number ending in "5" have a 1333&nbsp;MT/s FSB.<ref>{{cite web |title=Intel Readies New Xeons and Price Cuts |url=http://winbeta.org/comments.php?id=6530&catid=1 |website=WinBeta.org |archive-url=https://web.archive.org/web/20070927034447/http://winbeta.org/comments.php?id=6530&catid=1 |archive-date=September 27, 2007 |url-status=dead}}</ref>

{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed
! scope="col" | L2 cache
! scope="col" | FSB
! scope="col" | TDP
|-
| 3040
| 1.86 GHz
| rowspan="2" | 2 MB
| rowspan="4" | 1066 MT/s
| rowspan="9" | 65 W
|-
| 3050
| rowspan="2" | 2.13 GHz
|-
| 3055*
| rowspan="7" | 4 MB
|-
| 3060
| 2.4 GHz
|-
| 3065
| 2.33 GHz
| 1333 MT/s
|-
| 3070
| rowspan="2" | 2.66 GHz
| 1066 MT/s
|-
| 3075
| 1333 MT/s
|-
| 3080*
| 2.93 GHz
| 1066 MT/s
|-
| 3085
| 3.00 GHz
| 1333 MT/s
|}

* Models marked with an asterisk (*) are not present in Intel's Ark database.<ref>{{cite web|url=http://processorfinder.intel.com/|title=ARK - Your Source for Intel® Product Information|work=Intel® ARK (Product Specs)}}</ref>

===={{Anchor|Wolfdale}}3100-series "Wolfdale"====
{{main|Wolfdale (microprocessor)|List of Intel Core-based Xeon microprocessors#"Wolfdale" (45 nm)|List of Intel Core-based Xeon microprocessors#"Wolfdale-CL" (45 nm)|l3=§ "Wolfdale-CL" (45 nm)}}

The 3100 series, codenamed '''Wolfdale''' (product code 80570) dual-core Xeon (branded) CPU, was just a rebranded version of the Intel's mainstream [[Intel Core 2|Core 2 Duo]] E7000/E8000 and [[Pentium Dual-Core]] E5000 processors, featuring the same [[45 nanometer|45&nbsp;nm process]] and 6&nbsp;MB of L2 cache. Unlike most Xeon processors, they only support single-CPU operation. They use [[LGA 775]] (Socket T), operate on a 1333&nbsp;MT/s front-side bus, support Enhanced Intel [[SpeedStep]] Technology and Intel Virtualization Technology but do not support Hyper-Threading.

{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed
! scope="col" | L2 cache
! scope="col" | FSB
! scope="col" | TDP
|-
| E3110
| rowspan="2" | 3.00 GHz
| rowspan="3" | 6 MB
| rowspan="3" | 1333 MT/s
| 65 W
|-
| L3110
| 45 W
|-
| E3120
| 3.16 GHz
| 65 W
|}

==== {{Anchor|Woodcrest}}5100-series "Woodcrest" ====
{{main|List of Intel Core-based Xeon microprocessors#"Woodcrest" (65 nm)}}
{{Infobox CPU
| name           = Woodcrest
| image          = File:Intel Xeon DP 5110 Woodcrest.jpeg
| image_size     = 250
| caption        = 
| produced-start = {{Start date and age|2006}}
| produced-end   = {{End date and age|2009}}
| slowest        = 1.60
| slow-unit      = GHz
| fastest        = 3.0
| fast-unit      = GHz
| fsb-slowest    = 1066
| fsb-slow-unit  = MT/s
| fsb-fastest    = 1333
| fsb-fast-unit  = MT/s
| size-from      = [[65 nm process|65nm]]
| size-to        = 
| soldby         = [[Intel]]
| designfirm     = Intel
| manuf1         = Intel
| core1          = 
| sock1          = [[LGA 771]]
| pack1          = 
| code           = 80556
| cpuid          = 06Fx
| brand1         = Xeon 51xx
| arch           = [[x86-16]], [[IA-32]], [[x86-64]]
| microarch      = [[Intel Core (microarchitecture)|Core/Merom]]
| numcores       = 2
| l1cache        =128&nbsp;KB (64&nbsp;KB (32&nbsp;KB instruction + 32&nbsp;KB data) x 2)
| l2cache        = 4{{nbsp}}MB
| l3cache        =
| application    = DP Server
|predecessor=[[#5000-series "Dempsey"|Dempsey]]|successor=[[#5200-series "Wolfdale-DP|Wolfdale-DP]]|variant1=Clovertown|variant2=Tigerton}}

On June 26, 2006, Intel released the dual-core CPU (Xeon branded 5100 series) codenamed '''Woodcrest''' (product code 80556); it was the first Intel [[Intel Core (microarchitecture)|Core/Merom microarchitecture]] processor to be launched on the market. It is a dual-processor server and workstation version of the [[Intel Core 2|Core 2]] processor. Intel claimed that it provides an 80% boost in performance, while reducing power consumption by 20% relative to the 5000 series ''Dempsey''.

Most models have a 1333{{nbsp}}MT/s FSB, except for the 5110 and 5120, which have a 1066{{nbsp}}MT/s FSB. The fastest processor (5160) operates at 3.0{{nbsp}}GHz. All Woodcrest processors use the [[LGA 771]] (Socket J) socket and all except two models have a TDP of 65{{nbsp}}W. The 5160 has a TDP of 80{{nbsp}}W and the 5148LV (2.33{{nbsp}}GHz) has a TDP of 40{{nbsp}}W. The previous generation Xeons had a TDP of 130{{nbsp}}W. All models support Intel 64 (Intel's x86-64 implementation), the [[NX bit|XD bit]], and [[x86 virtualization|Virtualization Technology]], with the [[Demand-based switching]] power management option only on Dual-Core Xeon 5140 or above. Woodcrest has 4&nbsp;MB of shared L2 cache.

{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed
! scope="col" | L2 cache
! scope="col" | FSB
! scope="col" | TDP
|-
| 5110
| 1.60 GHz
| rowspan="9" | 4 MB
| rowspan="3" | 1066 MT/s
| rowspan="2" | 65 W
|-
| 5120
| rowspan="2" | 1.83 GHz
|-
| 5128
| 40 W
|-
| 5130
| 2.0 GHz
| 1333 MT/s
| 65 W
|-
| 5138
| 2.13 GHz
| 1066 MT/s
| 35 W
|-
| 5140
| rowspan="2" | 2.33 GHz
| rowspan="4" | 1333 MT/s
| 65 W
|-
| 5148
| 40 W
|-
| 5150
| 2.66 GHz
| 65 W
|-
| 5160
| 3.00 GHz
| 80 W
|}

===={{Anchor|Wolfdale-DP}}5200-series "Wolfdale-DP"====
{{main|List of Intel Core-based Xeon microprocessors#"Wolfdale-DP" (45 nm)}}
{{Infobox CPU
| name           = Wolfdale-DP
| image          =
| image_size     =
| caption        =
| produced-start = 2007
| produced-end   = present
| slowest        = 1.866
| fastest        = 3.50
| slow-unit      = GHz
| fast-unit      = GHz
| fsb-slowest    = 1066
| fsb-fastest    = 1600
| fsb-slow-unit  = MT/s
| fsb-fast-unit  = MT/s
| size-from      = 45&nbsp;nm
| size-to        =
| soldby         =
| designfirm     =
| manuf1         =
| core1          =
| sock1          =
| pack1          = [[LGA 771]]
| code           = 80573
| cpuid          = 1067x
| brand1         = Xeon 52xx
| arch           = [[x86-16]], [[IA-32]], [[x86-64]]
| microarch      = [[Penryn (microarchitecture)|Penryn]]
| numcores       = 2
| l1cache        =
| l2cache        = 6&nbsp;MB
| l3cache        =
| application    = DP Server
}}

On November 11, 2007, Intel released the dual-core CPU (Xeon branded 5200 series) codenamed '''Wolfdale-DP''' (product code 80573).<ref>{{cite web|url=https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/dual-core-xeon-5200-datasheet.pdf|title=Dual-Core Intel Xeon Processor 5200 Series|date=August 2008|publisher=Intel}}</ref> It is built on a [[45 nanometer|45&nbsp;nm process]] like the desktop Core 2 Duo and Xeon [[Wolfdale (microprocessor)|Wolfdale]], featuring Intel 64 (Intel's x86-64 implementation), the [[NX bit|XD bit]], and [[x86 virtualization|Virtualization Technology]]. It is unclear whether the [[Demand-based switching]] power management is available on the L5238.<ref>{{cite press release |title=Intel Ships New Processors for Embedded, Communications and Storage Markets Based on New Transistors, Manufacturing |url=https://www.intel.com/pressroom/archive/releases/2008/20080227comp.htm |location=Santa Clara, CA |website=Intel |language=en-US |date=February 27, 2008 |access-date=December 10, 2022}}</ref> Wolfdale has 6&nbsp;MB of shared L2 cache.

{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed (GHz)
! scope="col" | L2 cache
! scope="col" | FSB
! scope="col" | TDP
|-
| E5205
| 1.86 GHz
| rowspan="6" | 6 MB
| 1066 MT/s
| 65 W
|-
| L5238
| 2.66 GHz
| rowspan="4" | 1333 MT/s
| 35 W
|-
| L5240
| 3.00 GHz
| 40 W
|-
| X5260
| 3.33 GHz
| rowspan="3" | 80 W
|-
| X5270
| 3.50 GHz
|-
| X5272
| 3.40 GHz
| 1600 MT/s
|}

===={{Anchor|Tigerton-DC}}7200-series "Tigerton"====
{{main|List of Intel Core-based Xeon microprocessors#"Tigerton-DC" (65 nm)}}

The 7200 series, codenamed '''Tigerton''' (product code 80564) is an MP-capable processor, similar to the [[#Tigerton|7300]] series, but, in contrast, there is a single dual-core die.<ref>{{cite web|url=https://www.theregister.com/2006/10/23/intel_shows_tigerton/|title=Intel bares Tigerton|website=[[The Register]]}}</ref><ref>{{cite web|url=https://www.engadget.com/2006/10/23/intel-previews-quad-core-xeon-tigerton-server-processor/|title=Intel previews quad-core Xeon "Tigerton" server processor|author=Donald Melanson|publisher=AOL|work=Engadget|date=October 23, 2006 }}</ref><ref>{{cite web|url=http://theinquirer.net/default.aspx?article=38970 |title=Rap meets tech at IDF yo |work=theinquirer.net |url-status=unfit |archive-url=https://web.archive.org/web/20070419030713/http://www.theinquirer.net/default.aspx?article=38970 |archive-date=April 19, 2007 }}</ref><ref>{{cite web |title=Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series Datasheet |date=September 2007 |publisher=Intel |url=http://download.intel.com/design/xeon/datashts/318080.pdf |access-date=September 19, 2007 |url-status=dead |archive-url=https://web.archive.org/web/20071025183559/http://download.intel.com/design/xeon/datashts/318080.pdf |archive-date=October 25, 2007 }}</ref>

{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed
! scope="col" | L2 cache
! scope="col" | FSB
! scope="col" | TDP
|-
| E7210
| 2.40 GHz
| rowspan="2" | 4 MB
| rowspan="2" | 1066 MT/s
| rowspan="2" | 80 W
|-
| E7220
| 2.93 GHz
|}

=== Quad-Core and Six-Core Xeon ===
==== {{Anchor|Kentsfield}}3200-series "Kentsfield "====
{{main|Kentsfield (microprocessor)|List of Intel Core-based Xeon microprocessors#"Kentsfield" (65 nm)}}
Intel released rebranded versions of its quad-core (2×2) Core 2 Quad processor as the Xeon 3200-series (product code 80562) on January 7, 2007.<ref>{{cite web |last=Huynh |first=Anh Tuan |date=January 7, 2007 |title=Intel Hard-Launches Three New Quad-core Processors |url=http://www.dailytech.com/article.aspx?newsid=5595 |website=DailyTech |archive-url=https://web.archive.org/web/20160405061432/http://www.dailytech.com/article.aspx?newsid=5595 |archive-date=April 5, 2016 |url-status=dead}}</ref> The 2&nbsp;×&nbsp;2 "quad-core" (dual-die dual-core<ref>{{cite web |title=Intel Clovertowns step up, reduce power |url=http://www.tgdaily.com/content/view/33708/135/ |publisher=TG Daily |access-date=September 5, 2007 |url-status=dead |archive-url=https://web.archive.org/web/20070911222341/http://www.tgdaily.com/content/view/33708/135/ |archive-date=September 11, 2007 |df=dmy-all }}</ref>) comprised two separate dual-core die next to each other in one CPU package. The models are the X3210, X3220 and X3230, running at 2.13&nbsp;GHz, 2.4&nbsp;GHz and 2.66&nbsp;GHz, respectively.<ref name="dailytech_quad-xeon">{{cite web |last=Huynh |first=Anh Tuan |date=September 21, 2006 |title=Quad-core Xeon Details Unveiled |url=http://www.dailytech.com/article.aspx?newsid=4253 |website=DailyTech |archive-url=https://web.archive.org/web/20171216175126/http://www.dailytech.com/article.aspx?newsid=4253 |archive-date=December 16, 2017 |url-status=dead}}</ref> Like the 3000-series, these models only support single-CPU operation and operate on a 1066&nbsp;MT/s front-side bus. It is targeted at the "blade" market. The X3220 is also branded and sold as [[List of Intel Core 2 microprocessors#.22Kentsfield.22 .2865 nm.29|Core2 Quad Q6600]], the X3230 as Q6700.

{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed
! scope="col" | L2 cache
! scope="col" | FSB
! scope="col" | TDP
|-
| X3210
| 2.13 GHz
| rowspan="3" | 4 MB&nbsp;×&nbsp;2 
| rowspan="3" | 1066 MT/s
| rowspan="2" | 100/105 W
|-
| X3220
| 2.40 GHz
|-
| X3230
| 2.66 GHz
| 100 W
|}

==== {{Anchor|Yorkfield}}3300-series "Yorkfield" ====
{{main|Yorkfield (microprocessor)|List of Intel Core-based Xeon microprocessors#"Yorkfield" (45 nm)|List of Intel Core-based Xeon microprocessors#"Yorkfield-CL" (45 nm)|l3=§ "Yorkfield-CL" (45 nm)}}
Intel released relabeled versions of its quad-core [[List of Intel Core 2 microprocessors#.22Yorkfield.22 .2845 nm.29|Core 2 Quad Yorkfield]] Q9300, Q9400, Q9x50 and QX9770 processors as the Xeon 3300-series (product code 80569). This processor comprises two separate dual-core dies next to each other in one CPU package and manufactured in a [[45 nanometer|45&nbsp;nm process]]. The models are the X3320, X3330, X3350, X3360, X3370 and X3380, being rebadged Q9300, Q9400, Q9450, Q9550, Q9650, QX9770, running at 2.50&nbsp;GHz, 2.66&nbsp;GHz, 2.66&nbsp;GHz, 2.83&nbsp;GHz, 3.0&nbsp;GHz, and 3.16&nbsp;GHz, respectively. The L2 cache is a unified 6&nbsp;MB per die (except for the X3320 and X3330 with a smaller 3&nbsp;MB L2 cache per die), and a front-side bus of 1333&nbsp;MHz. All models feature Intel 64 (Intel's x86-64 implementation), the [[NX bit|XD bit]], and [[x86 virtualization|Virtualization Technology]], as well as [[Demand-based switching]].

The [[Yorkfield (microprocessor)#Yorkfield CL|Yorkfield-CL]] (product code 80584) variant of these processors are X3323, X3353 and X3363. They have a reduced TDP of 80W and are made for single-CPU [[LGA 771]] systems instead of [[LGA 775]], which is used in all other Yorkfield processors. In all other respects, they are identical to their Yorkfield counterparts.

===={{Anchor|Clovertown}}5300-series "Clovertown"====
{{main|List of Intel Core-based Xeon microprocessors#"Clovertown" (65 nm)}}
{{Infobox CPU
| name           = Clovertown
| image          = File:Xeon X5355 Clovertown.jpg
| image_size     = 250
| caption        =
| produced-start = 2006
| produced-end   = present
| slowest        = 1.60
| fastest        = 3.0
| slow-unit      = GHz
| fast-unit      = GHz
| fsb-slowest    = 1066
| fsb-fastest    = 1333
| fsb-slow-unit  = MT/s
| fsb-fast-unit  =
| size-from      = 65&nbsp;nm
| size-to        =
| soldby         =
| designfirm     =
| manuf1         =
| core1          =
| sock1          =
| pack1          = [[LGA 771]]
| code           = 80563
| cpuid          = 06Fx
| brand1         = Xeon 53xx
| arch           = [[x86-16]], [[IA-32]], [[x86-64]]
| microarch      = [[Core (microarchitecture)|Core]]
| numcores       = 4
| l1cache        =
| l2cache        = 2×4&nbsp;MB
| l3cache        =
| application    = DP Server
}}

A quad-core (2×2) successor of the Woodcrest for DP segment, consisting of two dual-core Woodcrest chips in one package similarly to the dual-core Pentium D branded CPUs (two single-core chips) or the quad-core [[Kentsfield (microprocessor)|Kentsfield]]. All Clovertowns use the [[LGA 771]] package. The Clovertown has been usually implemented with two Woodcrest dies on a [[Multi-Chip Module|multi-chip module]], with 8&nbsp;MB of L2 cache (4&nbsp;MB per die). Like Woodcrest, lower models use a 1066&nbsp;MT/s FSB, and higher models use a 1333&nbsp;MT/s FSB. Intel released '''Clovertown''', product code 80563, on November 14, 2006<ref>{{cite press release |url=http://www.intel.com/pressroom/archive/releases/20061114comp.htm |title=Intel Ignites Quad-Core Era |publisher=[[Intel]]}}</ref> with models E5310, E5320, E5335, E5345, and X5355, ranging from 1.6&nbsp;GHz to 2.66&nbsp;GHz. All models support MMX, SSE, SSE2, SSE3, SSSE3, Intel 64, XD bit (an NX bit implementation), [[Intel VT]]. The E and X designations are borrowed from Intel's Core 2 model numbering scheme; an ending of -0 implies a 1066&nbsp;MT/s FSB, and an ending of -5 implies a 1333&nbsp;MT/s FSB.<ref name="dailytech_quad-xeon"/> All models have a TDP of 80&nbsp;W with the exception of the X5355, which has a TDP of 120&nbsp;W, and the X5365, which has a TDP of 150&nbsp;W. A low-voltage version of Clovertown with a TDP of 50&nbsp;W has a model numbers L5310, L5320 and L5335 (1.6&nbsp;GHz, 1.86&nbsp;GHz and 2.0&nbsp;GHz respectively). The 3.0&nbsp;GHz X5365 arrived in July 2007, and became available in the [[Apple Inc.|Apple]] [[Mac Pro]]<ref>{{cite web |url=http://www.apple.com/macpro/ |title=Apple - Mac Pro - The fastest, most powerful Mac ever. |archive-url=https://web.archive.org/web/20130602111641/http://www.apple.com/macpro/ |archive-date=2013-06-02 |url-status=dead}}</ref> on April 4, 2007.<ref>{{cite web |url=http://www.tgdaily.com/2006/09/26/intel_core_2_quad_announcement/ |title=Intel CEO announces Core 2 Quad |first1=Wolfgang |last1=Gruener |first2=Humphrey |last2=Cheung |date=September 26, 2006 |website=TG Daily |archive-url=https://web.archive.org/web/20061026105909/http://www.tgdaily.com/2006/09/26/intel_core_2_quad_announcement/ |archive-date=26 October 2006 |url-status=dead}}</ref><ref>{{cite web |url=http://www.dailytech.com/Intel+Readies+New+Xeons+and+Price+Cuts/article6493.htm |title=Intel Readies New Xeons and Price Cuts |website=[[DailyTech]] |archive-url=https://web.archive.org/web/20160612081525/http://www.dailytech.com/Intel+Readies+New+Xeons+and+Price+Cuts/article6493.htm |archive-date=June 12, 2016 |url-status=dead}}</ref> The X5365 performs up to around 38&nbsp;[[GFLOPS]] in the LINPACK benchmark.<ref>{{cite web |url=http://www.intel.com/performance/server/xeon/hpcapp.htm |title=Intel® Xeon® Processor E5-2600 v4 Family World Record}}</ref>

{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed
! scope="col" | L2 cache
! scope="col" | FSB
! scope="col" | TDP
|-
| E5310
| rowspan="2" | 1.60 GHz
| rowspan="9" | 4 MB&nbsp;×&nbsp;2
| rowspan="4" | 1066 MT/s
| 80 W
|-
| L5310
| 50 W
|-
| E5320
| rowspan="2" | 1.86 GHz
| 80 W
|-
| L5320
| 50 W
|-
| E5335
| rowspan="2" | 2.00 GHz
| rowspan="5" | 1333 MT/s
| 80 W
|-
| L5335
| 50 W
|-
| E5345
| 2.33 GHz
| 80 W
|-
| X5355
| 2.66 GHz
| 120 W
|-
| X5365
| 3.00 GHz
| 150 W
|}

==== {{Anchor|Harpertown}}5400-series "Harpertown" ====
{{main|List of Intel Core-based Xeon microprocessors#"Harpertown" (45 nm)}}
{{Infobox CPU
| name           = Harpertown
| image          =
| image_size     =
| caption        =
| produced-start = 2007
| produced-end   = present
| slowest        = 2.0
| fastest        = 3.40
| slow-unit      = GHz
| fast-unit      = GHz
| fsb-slowest    = 1066
| fsb-fastest    = 1600
| fsb-slow-unit  = MT/s
| fsb-fast-unit  =
| size-from      = 45&nbsp;nm
| size-to        =
| soldby         =
| designfirm     =
| manuf1         =
| core1          =
| sock1          =
| pack1          = [[LGA 771]]
| code           = 80574
| cpuid          = 1067x
| brand1         = Xeon 54xx
| brand2         = [[Intel Core 2|Core 2 Quad]] QX9775
| arch           = [[x86-16]], [[IA-32]], [[x86-64]]
| microarch      = [[Penryn (microarchitecture)|Penryn]]
| numcores       = 4
| l1cache        =
| l2cache        = 2&nbsp;×&nbsp;6&nbsp;MB
| l3cache        =
| application    = DP Server
}}

On November 11, 2007 Intel presented [[Yorkfield]]-based Xeons – called Harpertown (product code 80574) – to the public.<ref>{{cite web|url=https://www.intel.com/Assets/PDF/datasheet/318589.pdf|title=Quad-Core Intel Xeon Processor 5400 Series|date=August 2008|website=Intel}}</ref> This family consists of dual die quad-core CPUs manufactured on a [[45 nanometer|45&nbsp;nm process]] and featuring 1066&nbsp;MHz, 1333&nbsp;MHz, 1600&nbsp;MHz front-side buses, with TDP rated from 40&nbsp;W to 150&nbsp;W depending on the model. These processors fit in the [[LGA 771]] package. All models feature Intel 64 (Intel's x86-64 implementation), the [[NX bit|XD bit]], and [[x86 virtualization|Virtualization Technology]]. All except the E5405 and L5408 also feature [[Demand-based switching]]. The supplementary character in front of the model-number represents the thermal rating: an L depicts a TDP of 40&nbsp;W or 50&nbsp;W, an E depicts 80&nbsp;W whereas an X is 120&nbsp;W TDP or above. The speed of 3.00&nbsp;GHz comes as four models, two models with 80&nbsp;W TDP two other models with 120&nbsp;W TDP with 1333&nbsp;MHz or 1600&nbsp;MHz front-side bus respectively. The fastest Harpertown is the X5492 whose TDP of 150&nbsp;W is higher than those of the Prescott-based Xeon DP but having twice as many cores. (The X5482 is also sold under the name "Core 2 Extreme QX9775" for use in the [[Intel Skulltrail]] system.)

Intel 1.6&nbsp;GT/s front-side bus Xeon processors will drop into the Intel 5400 (Seaburg) chipset whereas several mainboards featuring the Intel 5000/5200-chipset are enabled to run the processors with a 1333&nbsp;MHz front-side bus speed. Seaburg features support for dual {{nowrap|PCIe 2.0 x16}} slots and up to 128&nbsp;GB of memory.<ref>{{cite web |url=http://www.dailytech.com/Intel+Readies+1600+MHz+FrontSide+Bus+Xeons/article8656.htm |title=Intel Readies 1600&nbsp;MHz Front-Side Bus Xeons |website=[[DailyTech]] |archive-url=https://web.archive.org/web/20160401180832/http://www.dailytech.com/Intel+Readies+1600+MHz+FrontSide+Bus+Xeons/article8656.htm |archive-date=April 1, 2016 |url-status=dead}}</ref><ref>{{cite web |url=http://www.trustedreviews.com/cpu-memory/news/2007/08/30/Intel-Xeons-Coming-With-1600MHz-FSB/p1 |title=Intel Xeons Coming With 1600MHz FSB |website=[[TrustedReviews]]}}</ref>

{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed
! scope="col" | L2 cache
! scope="col" | FSB
! scope="col" | TDP
|-
| E5405
| 2.00 GHz
| rowspan="18" | 2&nbsp;×&nbsp;6&nbsp;MB
| 1333 MT/s
| 80 W
|-
| L5408
| 2.13 GHz
| 1066 MT/s
| 40 W
|-
| E5410
| rowspan="2" | 2.33 GHz
| rowspan="11" | 1333 MT/s
| 80 W
|-
| L5410
| 50 W
|-
| E5420
| rowspan="2" | 2.50 GHz
| 80 W
|-
| L5420
| 50 W
|-
| E5430
| rowspan="2" | 2.66 GHz
| 80 W
|-
| L5430
| 50 W
|-
| E5440
| 2.83 GHz
| 80 W
|-
| X5450
| rowspan="2" | 3.00 GHz
| 120 W
|-
| E5450
| 80 W
|-
| X5460
| 3.16 GHz
| rowspan="2" | 120 W
|-
| X5470
| 3.33 GHz
|-
| E5462
| 2.80 GHz
| rowspan="5" | 1600 MT/s
| rowspan="2" | 80 W
|-
| E5472
| rowspan="2" | 3.00 GHz
|-
| X5472
| 120 W
|-
| X5482
| 3.20 GHz
| rowspan="2" | 150 W
|-
| X5492
| 3.40 GHz
|}

==== {{Anchor|Tigerton}}7300-series "Tigerton QC" ====
{{main|List of Intel Core-based Xeon microprocessors#"Tigerton" (65 nm)}}
{{Infobox CPU
| name           = Tigerton
| image          =
| image_size     =
| caption        =
| produced-start = 2007
| produced-end   = present
| slowest        = 1.60
| fastest        = 2.933
| slow-unit      = GHz
| fast-unit      = GHz
| fsb-slowest    = 1066
| fsb-fastest    =
| fsb-slow-unit  = MT/s
| fsb-fast-unit  =
| size-from      = 65&nbsp;nm
| size-to        =
| soldby         =
| designfirm     =
| manuf1         =
| core1          =
| sock1          =
| pack1          = [[Socket 604|mPGA604]]
| code           = 80564<br />80565
| cpuid          = 06Fx
| brand1         = Xeon 72xx
| brand2         = Xeon 73xx
| arch           = [[x86-16]], [[IA-32]], [[x86-64]]
| microarch      = [[Core (microarchitecture)|Core]]
| numcores       = 4
| l1cache        =
| l2cache        = 2×2 or 2×4&nbsp;MB
| l3cache        =
| application    = MP Server
}}

The 7300 series, codenamed '''Tigerton QC''' (product code 80565) is a four-socket (packaged in [[Socket 604]]) and more capable [[quad-core processor]], consisting of two [[dual core]] Core 2 architecture silicon chips on a single ceramic module, similar to Intel's Xeon 5300 series Clovertown processor modules.<ref>{{cite press release |title=Intel Launches First Industry-Standard Quad-Core Products for High-End, Multi-Processor Servers |url=https://www.intel.com/pressroom/archive/releases/2007/20070905comp.htm |location=Santa Clara, CA |website=Intel |language=en-US |date=September 5, 2007 |access-date=November 13, 2022}}</ref>

The 7300 series uses Intel's Caneland (Clarksboro) platform.

Intel claims the 7300 series Xeons offer more than twice the performance per watt as Intel's previous generation 7100 series. The 7300 series' Caneland chipset provides a point to point interface allowing the full front side bus bandwidth per processor.

The 7xxx series is aimed at the large server market, supporting configurations of up to 32&nbsp;CPUs per host.
{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed
! scope="col" | L2 cache
! scope="col" | FSB
! scope="col" | TDP
|-
| E7310
| 1.60 GHz
| rowspan="2" | 2×2 MB
| rowspan="6" | 1066 MT/s
| rowspan="4" | 80 W
|-
| E7320
| 2.13 GHz
|-
| E7330
| rowspan="2" | 2.40 GHz
| 2×3 MB
|-
| E7340
| rowspan="3" | 2×4 MB
|-
| L7345
| 1.86 GHz
| 50 W
|-
| X7350
| 2.93 GHz
| 130 W
|}

==== {{Anchor|Dunnington}}7400-series "Dunnington" ====
{{main|List of Intel Core-based Xeon microprocessors#"Dunnington" (45 nm)}}
{{Infobox CPU
| name           = Dunnington
| image          =
| image_size     =
| caption        =
| produced-start = 2008
| produced-end   = present
| slowest        = 2.133
| fastest        =2.66
| slow-unit      = GHz
| fast-unit      = GHz
| fsb-slowest    = 1066
| fsb-fastest    =
| fsb-slow-unit  = MT/s
| fsb-fast-unit  =
| size-from      = 45&nbsp;nm
| size-to        =
| soldby         =
| designfirm     =
| manuf1         =
| core1          =
| sock1          =
| pack1          = [[Socket 604|mPGA604]]
| code           = 80582
| cpuid          = 106D1
| brand1         = Xeon 74xx
| arch           = [[x86-16]], [[IA-32]], [[x86-64]]
| microarch      = [[Penryn (microarchitecture)|Penryn]]
| numcores       = 6
| l1cache        = 6&nbsp;× 96&nbsp;KB
| l2cache        = 3&nbsp;× 3&nbsp;MB
| l3cache        = 16&nbsp;MB
| application    = MP Server
}}

'''Dunnington'''<ref>{{cite news | first=Theo | last=Valich | title=Intel six-core coming in 2008 | date=February 25, 2008 | publisher=Tigervision Media | url = http://www.tgdaily.com/content/view/36198/135/ | work =TG Daily | access-date = February 26, 2008 | archive-url=https://web.archive.org/web/20080227234318/http://www.tgdaily.com/content/view/36198/135/ |archive-date = February 27, 2008}}</ref> – the last CPU of the Penryn generation and Intel's first [[multi-core]] (above two) die – features a single-die six- (or ''hexa-'') core design with three unified 3&nbsp;MB L2 caches (resembling three merged [[45 nanometer|45&nbsp;nm]] dual-core Wolfdale-3M dies), and 96&nbsp;kB L1 cache (Data) and 16&nbsp;MB of L3 cache. It features a 1.07&nbsp;GT/s [[Front Side Bus|FSB]], fits into the Tigerton's mPGA604 socket, and is compatible with both the Intel Caneland and IBM X4 chipsets. These processors support DDR2-1066 (533&nbsp;MHz), and have a maximum [[Thermal Design Power|TDP]] below 130&nbsp;W. They are intended for blades and other stacked computer systems. Availability was scheduled for the second half of 2008. It was followed shortly by the [[Nehalem (microarchitecture)|Nehalem microarchitecture]]. Total transistor count is 1.9 billion.<ref>{{cite web |last=Prickett Morgan |first=Timothy |date=September 15, 200|title=Chipzilla unveils six-core 'Dunnington' Xeons |url=https://www.theregister.com/2008/09/15/intel_dunnington_xeon/ |website=The Register |language=en-US |access-date=December 10, 2022}}</ref>

Announced on September 15, 2008.<ref>{{cite web |title=Intel® Xeon® Processor E7 Family |url=http://www.intel.com/products/processor/xeon7000/index.htm?iid=servproc+body_xeon7400subtitle |website=Intel |language=en-US |archive-url=https://web.archive.org/web/20081230170821/http://www.intel.com/products/processor/xeon7000/index.htm?iid=servproc+body_xeon7400subtitle |archive-date=December 30, 2008 |url-status=dead}}</ref>
{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed
! scope="col" | L3 cache
! scope="col" | FSB
! scope="col" | TDP
! scope="col" | Cores
|-
| E7420
| rowspan="2" | 2.13 GHz
| 8 MB
| rowspan="7" | 1066 MT/s
| rowspan="3" | 90 W
| rowspan="4" | 4
|-
| E7430
| 12 MB
|-
| E7440
| 2.40 GHz
| 16 MB
|-
| L7445
| 2.13 GHz
| rowspan="3" | 12 MB
| 50 W
|-
| E7450
| 2.40 GHz
| 90 W
| rowspan="3" | 6
|-
| L7455
| 2.13 GHz
| 65 W
|-
| X7460
| 2.66 GHz
| 16 MB
| 130 W
|}

== Nehalem-based Xeon ==
=== {{Anchor|Lynnfield}}3400-series "Lynnfield" ===
{{main|Lynnfield (microprocessor)|List of Intel Nehalem-based Xeon microprocessors#"Lynnfield" (45 nm)}}

Xeon 3400-series processors based on '''Lynnfield''' are designed for entry-level servers compared to Bloomfield, which is designed for uniprocessor workstations. Like Bloomfield, they are quad-core single-package processors based on the [[Nehalem (microarchitecture)|Nehalem microarchitecture]], but were introduced almost a year later, in September 2009. The same processors are marketed for mid-range to high-end desktops systems as [[Core i5]] and [[Core i7]]. They have two integrated memory channels as well as [[PCI Express]] and [[Direct Media Interface]] (DMI) links, but no [[Intel QuickPath Interconnect|QuickPath Interconnect]] (QPI) interface.

=== {{Anchor|Clarkdale}}3400-series "Clarkdale" ===
{{main|Clarkdale (microprocessor)|List of Intel Nehalem-based Xeon microprocessors#"Clarkdale" (MCP, 32 nm)}}
At low end of the 3400-series is not a Lynnfield but a '''Clarkdale''' processor, which is also used in the Core i3-500 and Core i5-600 processors as well as the Celeron G1000 and G6000 Pentium series. A single model was released in March 2010, the Xeon L3406. Compared to all other Clarkdale-based products, this one does not support integrated graphics, but has a much lower thermal design power of just 30 W. Compared to the Lynnfield-based Xeon 3400 models, it only offers two cores.

=== {{Anchor|Bloomfield}}W3500-series "Bloomfield" ===
{{main|Bloomfield (microprocessor)|List of Intel Nehalem-based Xeon microprocessors#"Bloomfield" (45 nm)}}
'''Bloomfield''' (or '''Nehalem-E''') is the codename for the successor to the Xeon 3300 series, is based on the [[Nehalem (microarchitecture)|Nehalem microarchitecture]] and uses the same [[45 nanometer|45&nbsp;nm]] manufacturing methods as Intel's [[Penryn (microprocessor)|Penryn]]. The first processor released with the Nehalem architecture is the high-end desktop [[List of Intel Core i7 processors|Core i7]], which was released in November 2008. This is the server version for single CPU systems.
This is a '''single-socket''' Intel Xeon processor designed for uniprocessor workstations.

The performance improvements over the previous Xeon 3300 series are based mainly on:
* Integrated [[memory controller]] supporting three memory channels of [[DDR3]] UDIMM (Unbuffered) or RDIMM (Registered)
* A new point-to-point processor interconnect ''[[QuickPath]]'', replacing the legacy front side bus
* Simultaneous multithreading by multiple cores and [[hyper-threading]] (2× per core).
* [[Turbo Boost]], an overclocking technology that allows the CPU to run at a clock speed higher than the base speed as needed

{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed
! scope="col" | L3 cache
! scope="col" | QPI speed
! scope="col" | DDR3 speed
! scope="col" | TDP
! scope="col" | Cores
! scope="col" | Threads
! scope="col" | [[Intel Turbo Boost|Turbo-Boost]]
|-
| W3503 || 2.40 GHz || rowspan="2" | 4 MB || rowspan="7" | 4.8 GT/s || rowspan="7" | 1066 MT/s || rowspan="9" | 130 W || colspan="2" rowspan="2" | 2 || rowspan="2" | No
|-
| W3505 || 2.53 GHz 
|-
| W3520 || 2.66 GHz || rowspan="7" | 8 MB || rowspan="7" | 4 || rowspan="7" | 8 || rowspan="7" | Yes
|-
| W3530 || 2.80 GHz 
|-
| W3540 || 2.93 GHz 
|-
| W3550 || 3.06 GHz 
|-
| W3565 || 3.20 GHz 
|-
| W3570 || 3.2 GHz  || rowspan="2" | 6.4 GT/s || rowspan="2" | 1333 MT/s 
|-
| W3580 || 3.33 GHz 
|}

=== {{Anchor|Gainestown|5500-series "Gainestown"|Gainestown|Nehalem-EP}}5500-series "Gainestown" ===
{{main|List of Intel Nehalem-based Xeon microprocessors#"Gainestown" (45 nm)}}
{{Infobox CPU
| name           = Gainestown
| image          =
| image_size     = 31
| caption        =
| produced-start = 2008
| produced-end   = present
| slowest        = 1.866
| fastest        = 3.333
| slow-unit      = GHz
| fast-unit      = GHz
| fsb-slowest    =
| fsb-fastest    =
| fsb-slow-unit  =
| fsb-fast-unit  =
| size-from      = 45&nbsp;nm
| size-to        =
| soldby         =
| designfirm     =
| manuf1         =
| core1          =
| sock1          =
| pack1          = [[LGA 1366]]
| brand1         = Xeon 55xx
| arch           = [[x86-16]], [[IA-32]], [[x86-64]]
| microarch      = [[Nehalem (microarchitecture)|Nehalem]]
| cpuid          = 106Ax
| code           = 80602
| numcores       = 4
| l1cache        =
| l2cache        = 4×256&nbsp;kB
| l3cache        = 8&nbsp;MB
| application    = DP Server
}}

'''Gainestown''' or '''Nehalem-EP''' (Efficient Performance), the successor to Wolfdale-DP, and  Harpertown, is based on the [[Nehalem (microarchitecture)|Nehalem microarchitecture]] and uses the same [[45 nanometer|45&nbsp;nm]] manufacturing methods. The first processor released with the Nehalem microarchitecture is the high-end desktop [[List of Intel Core i7 processors|Core i7]], which was released in November 2008. Server processors of the Xeon 55xx range were first supplied to testers in December 2008.<ref>{{cite web |last=De Gelas |first=Johan |date=December 16, 2008 |title=Intel Xeon 5570: Smashing SAP records |url=https://www.anandtech.com/show/3474 |website=AnandTech |language=en-US |access-date=December 10, 2022}}</ref>

The performance improvements over Wolfdale-DP and Harpertown processors are based mainly on:
* Monolithic design for quad-core models
* Integrated [[memory controller]] supporting three memory channels of [[DDR3 SDRAM|DDR3]] memory with ECC support.
* A new point-to-point processor interconnect ''[[Intel QuickPath Interconnect|QuickPath]]'', replacing the legacy front side bus. Gainestown has two QuickPath interfaces.
* [[Hyper-threading]] (2× per core, starting from 5518), that was already present in NetBurst-based processors
* [[Intel Turbo Boost|Turbo Boost]], an overclocking technology that allows the CPU to run at a clock speed higher than the base speed as needed

{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed
! scope="col" | L3 cache
! scope="col" | QPI speed
! scope="col" | DDR3 speed
! scope="col" | TDP
! scope="col" | Cores
! scope="col" | Threads
! scope="col" | Turbo-Boost
|-
| E5502
| 1.87 GHz
| rowspan="6" | 4 MB
| rowspan="6" | 4.8 GT/s
| rowspan="6" | 800 MT/s
| rowspan="4" | 80 W
| colspan="2" rowspan="2" | 2
| rowspan="6" | No
|-
| E5503
| rowspan="2" | 2.00 GHz
|-
| E5504
| rowspan="15" | 4
| rowspan="4" | 4
|-
| E5506
| rowspan="2" | 2.13 GHz
|-
| L5506
| 60 W
|-
| E5507
| 2.26 GHz
| 80 W
|-
| L5518
| 2.13 GHz
| rowspan="11" | 8 MB
| rowspan="6" | 5.86 GT/s
| rowspan="6" | 1066 MT/s
| 60 W
| rowspan="11" | 8
| rowspan="11" | Yes
|-
| E5520
| rowspan="2" | 2.26 GHz
| 80 W
|-
| L5520
| 60 W
|-
| E5530
| rowspan="2" | 2.40 GHz
| 80 W
|-
| L5530
| 60 W
|-
| E5540
| 2.53 GHz
| 80 W
|-
| X5550
| 2.66 GHz
| rowspan="5" | 6.4 GT/s
| rowspan="5" | 1333 MT/s
| rowspan="3" | 95 W
|-
| X5560
| 2.80 GHz
|-
| X5570
| 2.93 GHz
|-
| W5580
| 3.20 GHz
| rowspan="2" | 130 W
|-
|W5590
|3.33 GHz
|}

=== {{Anchor|Jasper Forest|C3500/C5500-Series "Jasper Forest"}}C3500/C5500-series "Jasper Forest" ===
{{main|List of Intel Nehalem-based Xeon microprocessors#"Jasper Forest" (45 nm)}}
{{Infobox CPU
| name           = Jasper Forest
| image          =
| image_size     =
| caption        =
| produced-start = 2010
| produced-end   = present
| slowest        = 1.733
| fastest        = 2.40
| slow-unit      = GHz
| fast-unit      = GHz
| fsb-slowest    =
| fsb-fastest    =
| fsb-slow-unit  =
| fsb-fast-unit  =
| size-from      = 45&nbsp;nm
| size-to        =
| soldby         =
| designfirm     =
| manuf1         =
| core1          =
| sock1          =
| pack1          = [[LGA 1366]]
| brand1         = Xeon C35xx (UP)
| brand2         = Xeon C55xx (DP)
| brand3         = Celeron P1xxx (UP)
| arch           = [[x86-16]], [[IA-32]], [[x86-64]]
| microarch      = [[Nehalem (microarchitecture)|Nehalem]]
| cpuid          = 106Ex
| code           = 80612
| numcores       = 4
| l1cache        =
| l2cache        = 4×256&nbsp;kB
| l3cache        = 8&nbsp;MB
| application    = UP/DP Server
}}

'''Jasper Forest''' is a Nehalem-based embedded processor with [[PCI Express]] connections on-die, core counts from 1 to 4 cores and power envelopes from 23 to 85 watts.<ref>{{cite web|url=https://www.theregister.com/2009/04/08/idf_beijing_2009/|title=Intel demos Moorestown, embeds Nehalem|website=[[The Register]]}}</ref>

The uni-processor version without QPI comes as LC35xx and EC35xx, while the dual-processor version is sold as LC55xx and EC55xx and uses QPI for communication between the processors. Both versions use a DMI link to communicate with the 3420 that is also used in the 3400-series Lynfield Xeon processors, but use an [[LGA 1366]] package that is otherwise used for processors with QPI but no DMI or PCI Express links. The CPUID code of both Lynnfield and Jasper forest is 106Ex, i.e., family 6, model 30.

The [[Celeron]] P1053 belongs into the same family as the LC35xx series, but lacks some [[Reliability, availability and serviceability (computer hardware)|RAS]] features that are present in the Xeon version.

=== {{Anchor|Gulftown|Westmere-EP}}W3600/5600-series "Gulftown" & "Westmere-EP" ===
{{main|Gulftown (microprocessor)|List of Intel Nehalem-based Xeon microprocessors#"Gulftown" (32 nm)|List of Intel Nehalem-based Xeon microprocessors#"Westmere-EP" (32 nm)|l3=§ "Westmere-EP" (32 nm)}}

'''Gulftown''' and '''Westmere-EP''', six-core 32&nbsp;nm architecture [[Westmere (microarchitecture)|Westmere]]-based processors, are the basis for the Xeon 36xx and 56xx series and the [[Core i7]]-980X. It launched in the first quarter of 2010. The 36xx-series follows the 35xx-series Bloomfield uni-processor model while the 56xx-series follows the 55xx-series Gainestown dual-processor model and both are socket compatible to their predecessors.
{| class="wikitable sortable"
|-
! scope="col" | Model
! scope="col" | Speed
! scope="col" | L3 cache
! scope="col" | QPI speed
! scope="col" | DDR3 speed
! scope="col" | TDP
! scope="col" | Cores
! scope="col" | Threads
! scope="col" | Turbo-Boost
|-
| W3670 || 3.20 GHz || rowspan="3" | 12 MB || 4.8 GT/s || 1066 MT/s || rowspan="3" | 130 W || rowspan="3" | 6 || rowspan="3" | 12 || rowspan="3" | Yes
|-
| W3680 || 3.33 GHz || rowspan="2" | 6.4 GT/s || rowspan="2" | 1333 MT/s 
|-
| W3690 || 3.46 GHz 
|-
| E5603 || 1.60 GHz || 4 MB || rowspan="4" | 4.8 GT/s || 800 MT/s || rowspan="3" | 80 W || rowspan="8" | 4 || rowspan="4" | 4 || rowspan="4" | No
|-
| E5606 || 2.13 GHz || rowspan="2" | 8 MB || rowspan="7" | 1066 MT/s 
|-
| E5607 || 2.26 GHz 
|-
| L5609 || rowspan="2" | 1.86 GHz || rowspan="24" | 12 MB || rowspan="2" | 40 W 
|-
| L5618 || rowspan="11" | 5.86 GT/s || rowspan="4" | 8 || rowspan="22" | Yes
|-
| E5620 || 2.40 GHz || 80 W 
|-
| L5630 || 2.13 GHz || 40 W 
|-
| E5630 || 2.53 GHz || 80 W 
|-
| L5638 || 2.00 GHz || rowspan="3" | 1333 MT/s || rowspan="3" | 60 W || rowspan="3" | 6 || rowspan="3" | 12 
|-
| L5639 || 2.13 GHz 
|-
| L5640 || 2.26 GHz 
|-
| E5640 || 2.66 GHz || 1066 MT/s || 80 W || 4 ||  8 
|-
| L5645 || rowspan="2" | 2.40 GHz || rowspan="10" | 1333 MT/s || 60 W || rowspan="5" | 6 || rowspan="5" | 12 
|-
| E5645 || rowspan="2" | 80 W 
|-
| E5649 || 2.53 GHz 
|-
| X5650 || 2.66 GHz || rowspan="12" | 6.4 GT/s || rowspan="6" | 95 W 
|-
| X5660 || 2.80 GHz 
|-
| X5667 || 3.06 GHz || 4 || 8 
|-
| X5670 || 2.93 GHz || 6 || 12 
|-
| X5672 || 3.20 GHz || 4 || 8 
|-
| X5675 || 3.06 GHz || 6 || 12 
|-
| X5677 || 3.46 GHz || 130 W || 4 || 8 
|-
| X5679 || 3.20 GHz|| 1066 MT/s || 115 W || rowspan="2" | 6 || rowspan="2" | 12 
|-
| X5680 || 3.33 GHz || rowspan="3" | 1333 MT/s || rowspan="4" | 130 W 
|-
| X5687 || 3.60 GHz || 4 || 8 
|-
| X5690 || 3.46 GHz || 6 || 12 
|-
| X5698 || 4.40 GHz || 1066 MT/s || 2 || 4 
|No
|}

=== {{Anchor|Beckton|Nehalem-EX}}6500/7500-series "Beckton" ===
{{main|List of Intel Nehalem-based Xeon microprocessors#"Beckton" (45 nm)}}
{{Infobox CPU
| name           = Beckton
| image          = Xeon Beckton with and without heat spreader.jpg
| image_size     =
| caption        = Xeon E7530 (with and without the heat spreader)
| produced-start = {{Start date and age|2010|03|30}}
| produced-end   = Q4 2012
| slowest        = 1.733
| slow-unit      = GHz
| fastest        = 2.667
| fast-unit      = GHz
| fsb-slowest    =
| fsb-fastest    =
| fsb-slow-unit  =
| fsb-fast-unit  =
| size-from      = 45&nbsp;nm
| size-to        =
| soldby         = [[Intel]]
| designfirm     = [[Intel]]
| manuf1         = [[Intel]]
| core1          =
| sock1          =
| pack1          = [[LGA 1567]]
| brand1         = Xeon 65xx (DP)
| brand2         = Xeon 75xx (MP)
| arch           = [[x86-16]], [[IA-32]], [[x86-64]]
| microarch      = [[Nehalem (microarchitecture)|Nehalem]]
| cpuid          = 206Ex
| code           = 80604
| numcores       = 4-8
| l1cache        =
| l2cache        = 256{{nbsp}}KB per core
| l3cache        = Up to 24{{nbsp}}MB
| application    = DP/MP Server
|qpi-slowest=6.4|qpi-slow-unit=GT/s}}

'''Beckton''' or '''Nehalem-EX''' (Expandable server market) is a Nehalem-based processor with up to eight cores and uses buffering inside the chipset to support up to 16 standard DDR3 DIMMs per CPU socket without requiring the use of FB-DIMMs.<ref>{{cite web |last=Shimpi |first=Anand Lal |date=May 27, 2009 |title=Nehalem-EX: 2.3 billion transistors, eight cores, one die |url=https://www.anandtech.com/show/3540 |website=AnandTech |language=en-US |access-date=December 10, 2022}}</ref> Unlike all previous Xeon MP processors, Nehalem-EX uses the new [[LGA 1567]] (Socket LS) package, replacing the [[Socket 604]] used in the previous models, up to Xeon [[#7400-series "Dunnington"|7400 "Dunnington"]]. The 75xx models have four QuickPath interfaces, so it can be used in up-to eight-socket configurations, while the 65xx models are only for up to two sockets. Designed by the Digital Enterprise Group (DEG) Santa Clara and Hudson Design Teams, Beckton is manufactured on the P1266 (45&nbsp;nm) technology. Its launch in March 2010 coincided with that of its direct competitor, AMD's [[Opteron]] 6xxx "Magny-Cours".<ref>{{cite web |last=Novakovic |first=Nebojsa |date=February 12, 2009 |title=Intel's next bunch of fun CPUs moves to 2010 |url=http://www.theinquirer.net/inquirer/opinion/976/1050976/intel-bunch-fun-cpus-moves-2010 |work=The Inquirer |url-status=unfit |archive-url=https://web.archive.org/web/20090304215925/http://www.theinquirer.net/inquirer/opinion/976/1050976/intel-bunch-fun-cpus-moves-2010 |archive-date=March 4, 2009}}</ref>

Most models limit the number of cores and QPI links as well as the L3 cache size in order to get a broader range of products out of the single chip design.

==={{Anchor|Westmere-EX}}E7-x8xx-series "Westmere-EX"===
{{main|List of Intel Nehalem-based Xeon microprocessors#"Westmere-EX" (32 nm) Expandable}}

'''Westmere-EX''' is the follow-on to Beckton/Nehalem-EX and the first Intel processor to have ten CPU cores. The microarchitecture is the same as in the six-core Gulftown/Westmere-EP processor, but it uses the [[LGA 1567]] package like Beckton to support up to eight sockets.

Starting with Westmere-EX, the naming scheme has changed once again, with "E7-xxxx" now signifying the high-end line of Xeon processors using a package that supports larger than two-CPU configurations, formerly the 7xxx series. Similarly, the 3xxx uniprocessor and 5xxx dual-processor series turned into E3-xxxx and E5-xxxx, respectively, for later processors.

==Sandy Bridge- and Ivy Bridge-based Xeon==

=== {{Anchor|Sandy Bridge|E3}}E3-12xx-series "Sandy Bridge" ===
{{main|Sandy Bridge|List of Intel Sandy Bridge-based Xeon microprocessors#"Sandy Bridge" (32 nm)}}

The '''Xeon E3-12xx''' line of processors, introduced in April 2011, uses the [[Sandy Bridge]] chips that are also the base for the Core i3/i5/i7-2xxx and Celeron/Pentium Gxxx products using the same [[LGA 1155]] socket, but with a different set of features disabled. Notably, the Xeon variants include support for [[ECC memory]], [[VT-d]] and [[trusted execution]] that are not present on the consumer models, while only some Xeon E3 enable the integrated [[GPU]] that is present on Sandy Bridge. Like its Xeon 3400-series predecessors, the Xeon E3 only supports operation with a single CPU socket and is targeted at entry-level workstations and servers. The CPUID of this processor is 0206A7h, the product code is 80623.

=== {{Anchor|Ivy Bridge|E3-V2}}E3-12xx v2-series "Ivy Bridge" ===
{{main|Ivy Bridge (microarchitecture)|List of Intel Ivy Bridge-based Xeon microprocessors#"Ivy Bridge" (22 nm)}}
'''Xeon E3-12xx v2''' is a minor update of the Sandy Bridge-based E3-12xx, using the 22&nbsp;nm shrink, and providing slightly better performance while remaining backwards compatible. They were released in May 2012 and mirror the desktop Core i3/i5/i7-3xxx parts.

=== {{Anchor|E5}}E5-14xx/24xx series "Sandy Bridge-EN" and  E5-16xx/26xx/46xx-series "Sandy Bridge-EP" ===
{{main|Sandy Bridge-E|List of Intel Sandy Bridge-based Xeon microprocessors#"Sandy Bridge-E" (32 nm)|List of Intel Sandy Bridge-based Xeon microprocessors#"Sandy Bridge-EN" (32 nm) Entry|l3=§ "Sandy Bridge-EN" (32 nm) Entry|List of Intel Sandy Bridge-based Xeon microprocessors#"Sandy Bridge-EP" (32 nm) Efficient Performance|l4=§ "Sandy Bridge-EP" (32 nm) Efficient Performance}}

The '''Xeon E5-16xx''' processors follow the previous Xeon 3500/3600-series products as the high-end single-socket platform, using the [[LGA 2011]] package introduced with this processor. They share the Sandy Bridge-E platform with the single-socket Core i7-38xx and i7-39xx processors. The CPU chips have no integrated GPU but eight CPU cores, some of which are disabled in the entry-level products. The '''Xeon E5-26xx''' line has the same features but also enables multi-socket operation like the earlier Xeon 5000-series and Xeon 7000-series processors.

=== {{Anchor|E5-V2}}E5-14xx v2/24xx v2 series "Ivy Bridge-EN" and  E5-16xx v2/26xx v2/46xx v2 series "Ivy Bridge-EP" ===
{{main|Ivy Bridge-EN|l1=Ivy Bridge-EN/EP|List of Intel Ivy Bridge-based Xeon microprocessors#Xeon E5-1xxx v2 (uniprocessor)|List of Intel Ivy Bridge-based Xeon microprocessors#Xeon E5-2xxx v2 (dual-processor)|l3=§ Xeon E5-2xxx v2 (dual-processor)|List of Intel Ivy Bridge-based Xeon microprocessors#Xeon E5-4xxx v2 (quad-processor)|l4=§ Xeon E5-4xxx v2 (quad-processor)}}

The '''Xeon E5 v2''' line was an update, released in September 2013 to replace the original Xeon E5 processors with a variant based on the Ivy Bridge shrink. The maximum number of CPU cores was raised to 12 per processor module and the total L3 cache was upped to 30&nbsp;MB.<ref>{{Cite news |last=Prickett Morgan |first=Timothy |date=September 10, 2013 |title=Intel carves up Xeon E5-2600 v2 chips for two-socket boxes |url= https://www.theregister.com/2013/09/10/intel_ivy_bridge_xeon_e5_2600_v2_launch/ |website=The Register |language=en-US |access-date= November 13, 2022 }}</ref><ref>{{Cite news |title=Intel Introduces Highly Versatile Datacenter Processor Family Architected for New Era of Services |url=http://newsroom.intel.com/community/intel_newsroom/blog/2013/09/10/intel-introduces-highly-versatile-datacenter-processor-family-architected-for-new-era-of-services |work=Intel Newsroom |date=September 10, 2013 |access-date=September 13, 2013}}</ref> The consumer version of the Xeon E5-16xx v2 processor is the [[List of Intel Core i7 processors#"Ivy Bridge-E" (22 nm)|Core i7-48xx and 49xx]].

=== {{Anchor|E7-V2}}E7-28xx v2/48xx v2/88xx v2 series "Ivy Bridge-EX" ===
{{main|Ivy Bridge-EX|List of Intel Ivy Bridge-based Xeon microprocessors#Xeon E7-28xx v2 (dual-processor)|List of Intel Ivy Bridge-based Xeon microprocessors#Xeon E7-48xx v2 (quad-processor)|l3=§ Xeon E7-48xx v2 (quad-processor)|List of Intel Ivy Bridge-based Xeon microprocessors#Xeon E7-88xx v2 (octa-processor)|l4=§ Xeon E7-88xx v2 (octa-processor)}}

The '''Xeon E7 v2''' line was an update, released in February 2014 to replace the original Xeon E7 processors with a variant based on the Ivy Bridge shrink. There was no Sandy Bridge version of these processors but rather a Westmere version.

== Haswell-based Xeon ==
{{main|Haswell (microarchitecture)#Server processors}}

=== {{Anchor|E3-V3}}E3-12xx v3 series "Haswell-WS" ===
{{main|List of Intel Haswell-based Xeon microprocessors#"Haswell-WS" (22 nm)}}
[[File:Intel Xeon E3-1241 v3 CPU.jpg|thumb|Intel Xeon E3-1241 v3 CPU, sitting atop the inside part of its retail box that contains an OEM fan-cooled [[heatsink]] ]]
[[File:Intel Xeon E3 1220v3 pin side.jpg|thumb|Intel Xeon E3-1220 v3 CPU, pin side]]
Introduced in May 2013, '''Xeon E3-12xx&nbsp;v3''' is the first Xeon series based on the Haswell microarchitecture. It uses the new [[LGA&nbsp;1150]] socket, which was introduced with the desktop Core i5/i7 Haswell processors, incompatible with the LGA 1155 that was used in Xeon&nbsp;E3 and E3&nbsp;v2. As before, the main difference between the desktop and server versions is added support for ECC memory in the Xeon-branded parts. The main benefit of the new microarchitecture is better power efficiency.

=== {{Anchor|E5-V3|HASWELL-EP}}E5-16xx/26xx v3 series "Haswell-EP" ===
{{main|List of Intel Haswell-based Xeon microprocessors#"Haswell-EN" (22 nm) Entry|List of Intel Haswell-based Xeon microprocessors#"Haswell-EP" (22 nm) Efficient Performance|l2=§ "Haswell-EP" (22 nm) Efficient Performance}}
[[File:Intel Xeon E5-1650 v3 CPU.jpg|thumb|Intel Xeon E5-1650 v3 CPU; its retail box contains no OEM heatsink.]]

Introduced in September 2014, '''Xeon E5-16xx&nbsp;v3''' and '''Xeon E5-26xx&nbsp;v3''' series use the new [[LGA&nbsp;2011-v3]] socket, which is incompatible with the LGA&nbsp;2011 socket used by earlier Xeon&nbsp;E5 and E5&nbsp;v2 generations based on Sandy Bridge and Ivy Bridge microarchitectures. Some of the main benefits of this generation, compared to the previous one, are improved power efficiency, higher core counts, and bigger [[last level cache]]s (LLCs). Following the already used nomenclature, Xeon E5-26xx v3 series allows dual-socket operation.

One of the new features of this generation is that Xeon E5&nbsp;v3 models with more than 10 cores support [[cluster on die]] (COD) operation mode, allowing CPU's multiple columns of cores and LLC slices to be logically divided into what is presented as two [[non-uniform memory access]] (NUMA) CPUs to the operating system. By keeping data and instructions local to the "partition" of CPU which is processing them, thus decreasing the LLC access latency, COD brings performance improvements to NUMA-aware operating systems and applications.<ref>{{cite web |last=De Gelas |first=Johan |date=September 8, 2014 |title=Intel Xeon E5 Version 3, Up to 18 Haswell EP Cores: The Magic Inside the Uncore |url=http://www.anandtech.com/show/8423/intel-xeon-e5-version-3-up-to-18-haswell-ep-cores-/4 |website=AnandTech |language=en-US |access-date=September 9, 2014}}</ref>

=== {{Anchor|E7-V3}}E7-48xx/88xx v3 series "Haswell-EX" ===
{{main|List of Intel Haswell-based Xeon microprocessors#"Haswell-EX" (22 nm) Expandable}}
Introduced in May 2015, '''Xeon E7-48xx&nbsp;v3''' and '''Xeon E7-88xx&nbsp;v3''' series provide higher core counts, higher per-core performance and improved reliability features, compared to the previous Xeon E7&nbsp;v2 generation. Following the usual SKU nomenclature, Xeon E7-48xx&nbsp;v3 and E7-88xx&nbsp;v3 series allow multi-socket operation, supporting up to quad- and eight-socket configurations, respectively.<ref name="cpu-world-2015050701">{{cite web |last=Shvets |first=Anthony |date=May 7, 2015 |title=Intel launches Xeon E7 v3 server processors |url=http://www.cpu-world.com/news_2015/2015050701_Intel_launches_Xeon_E7_v3_server_processors.html |website=CPU-World |language=en-US |access-date=May 16, 2015}}</ref><ref name="anandtech-9193">{{cite web |last=De Gelas |first=Johan |date=May 8, 2015 |title=The Intel Xeon E7-8800 v3 Review: The POWER8 Killer? |url=http://www.anandtech.com/show/9193/the-xeon-e78800-v3-review |website=AnandTech |language=en-US |access-date=May 16, 2015}}</ref> These processors use the LGA&nbsp;2011 (R1) socket.<ref>{{cite web |last=Mujtaba |first= Hassan |date=May 6, 2015 | title = Intel Unleashes Haswell-EX Xeon E7 V3 Processors – Up to 18 Cores, 45 MB L3 Cache, 12&nbsp;TB DDR4 Memory Support and 5.7 Billion Transistors |url=http://wccftech.com/intel-unleashes-haswell-ex-xeon-e7-v3-processors-18-cores-45-mb-l3-cache-12-tb-ddr4-memory-support-57-billion-transistors/ |website=Wccftech |language=en-US |access-date=January 29, 2016}}</ref>

Xeon E7-48xx&nbsp;v3 and E7-88xx&nbsp;v3 series contain a quad-channel [[integrated memory controller]] (IMC), supporting both DDR3 and DDR4 [[LRDIMM]] or [[RDIMM]] memory modules through the use of ''Jordan Creek'' (DDR3) or ''Jordan Creek 2'' (DDR4) memory buffer chips. Both versions of the memory buffer chip connect to the processor using version 2.0 of the Intel [[Scalable Memory Interconnect]] (SMI) interface, while supporting [[lockstep memory]] layouts for improved reliability. Up to four memory buffer chips can be connected to a processor, with up to six DIMM slots supported per each memory buffer chip.<ref name="cpu-world-2015050701" /><ref name="anandtech-9193" />

Xeon E7-48xx&nbsp;v3 and E7-88xx&nbsp;v3 series also contain functional bug-free support for [[Transactional Synchronization Extensions]] (TSX), which was disabled via a [[microcode]] update in August 2014 for Haswell-E, Haswell-WS (E3-12xx v3) and Haswell-EP (E5-16xx/26xx v3) models, due to a bug that was discovered in the TSX implementation.<ref name="cpu-world-2015050701" /><ref name="anandtech-9193" /><ref>{{cite web |last=Cutress |first=Ian |date=August 12, 2014 | title = Intel Disables TSX Instructions: Erratum Found in Haswell, Haswell-E/EP, Broadwell-Y |url=http://www.anandtech.com/show/8376/intel-disables-tsx-instructions-erratum-found-in-haswell-haswelleep-broadwelly |website=AnandTech |language=en-US |access-date=August 30, 2014}}</ref><ref>{{cite web |title=Transactional Synchronization in Haswell |url=http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell |website=Intel |language=en-US |date=February 7, 2012 |access-date=February 7, 2012 |archive-url=https://web.archive.org/web/20120208215723/http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell/ |archive-date=2012-02-08 |url-status=dead}}</ref><ref>{{cite web |last=Wasson |first=Scott |date=August 12, 2014 |title=Errata prompts Intel to disable TSX in Haswell, early Broadwell CPUs |url=http://techreport.com/news/26911/errata-prompts-intel-to-disable-tsx-in-haswell-early-broadwell-cpus |website=Tech Report |access-date=August 12, 2014}}</ref><ref>{{cite web |title=Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium Processor Family, and Desktop Intel Celeron Processor Family: Specification Update (Revision 039US) |url=https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf |website=Intel |language=en-US |date=April 2020 |access-date=November 13, 2022 |page=46 |quote=Under a complex set of internal timing conditions and system events, software using the Intel TSX (Transactional Synchronization Extensions) instructions may observe unpredictable system behavior.}}</ref>

== Broadwell-based Xeon ==
{{main|Broadwell (microarchitecture)#Server processors}}

=== {{Anchor|E3-V4}}E3-12xx v4 series "Broadwell-H" ===
Introduced in June 2015, '''Xeon E3-12xx&nbsp;v4''' is the first Xeon series based on the Broadwell microarchitecture. It uses [[LGA&nbsp;1150]] socket, which was introduced with the desktop Core i5/i7 Haswell processors. As before, the main difference between the desktop and server versions is added support for ECC memory in the Xeon-branded parts. The main benefit of the new microarchitecture is the new lithography process, which results in better power efficiency.

== Skylake-based Xeon ==
{{main|Skylake (microarchitecture)#Server processors}}

=== {{Anchor|E3-V5}}E3-12xx v5 series "Skylake-S" ===
Introduced in October 2015, '''Xeon E3-12xx&nbsp;v5''' is the first Xeon series based on the Skylake microarchitecture. It uses new [[LGA&nbsp;1151]] socket, which was introduced with the desktop Core i5/i7 Skylake processors. Although it uses the same socket as consumer processors, it is limited to the C200 server chipset series and will not work with consumer chipsets like Z170. As before, the main difference between the desktop and server versions is added support for ECC memory in the Xeon-branded parts.
== Kaby Lake-based Xeon ==
{{main|Kaby Lake}}

=== {{Anchor|E3-V5}}E3-12xx v6 series ===
Introduced in January 2017, '''Xeon E3-12xx&nbsp;v6''' is the first Xeon series based on the Kaby Lake microarchitecture. It uses the same [[LGA&nbsp;1151]] socket, which was introduced with the desktop Core i5/i7 Kaby Lake processors. As before, the main difference between the desktop and server versions is added support for ECC memory and improved energy efficiency in the Xeon-branded parts.

== Coffee Lake-based Xeon ==
{{main|Coffee Lake}}

=== Coffee Lake-E (Server/Workstation) ===
{| class="wikitable" style="text-align: center;"
|-
! Processor<br />branding
! Model
! [[CPU core|Cores]]
([[Thread (computing)|Threads]])
! Base CPU<br />[[clock rate]]
! Max. [[Intel Turbo Boost|Turbo]]
clock rate
! [[Intel HD and Iris Graphics|GPU]]
! max [[Graphics processing unit#Integrated graphics|GPU]]<br />clock rate
! L3<br />cache <ref group="note">MiB = MB = 1024&nbsp;kB</ref>
! TDP
! Memory<br />support
! Price<br />(USD)
|-
| rowspan="11" | Xeon E
| [https://ark.intel.com/content/www/us/en/ark/products/134855/intel-xeon-e2186g-processor-12m-cache-up-to-4-70-ghz.html 2186G]
| rowspan="2" | 6 (12)
| 3.8&nbsp;GHz
| rowspan="3" | 4.7&nbsp;GHz
| rowspan="5" | [[Intel Graphics Technology#Kaby Lake Refresh / Amber Lake / Coffee Lake / Coffee Lake Refresh / Whiskey Lake / Comet Lake|UHD P630]]
| rowspan="5" | 1.20&nbsp;GHz
| rowspan="2" | 12 MB
| 95 W
| rowspan="11" |Up to 64 GB<ref group="note">128&nbsp;GB after BIOS update</ref><br />DDR4 2666<br />[[ECC memory]]<br />supported
| $506
|-
| [https://ark.intel.com/content/www/us/en/ark/products/134860/intel-xeon-e2176g-processor-12m-cache-up-to-4-70-ghz.html 2176G]
| 3.7&nbsp;GHz
| 80 W
| $406
|-
| [https://ark.intel.com/content/www/us/en/ark/products/134864/intel-xeon-e2174g-processor-8m-cache-up-to-4-70-ghz.html 2174G]
| 4 (8)
| 3.8&nbsp;GHz
| 8 MB
| 71 W
| $370
|-
| [https://ark.intel.com/content/www/us/en/ark/products/134866/intel-xeon-e2146g-processor-12m-cache-up-to-4-50-ghz.html 2146G]
| 6 (12)
| 3.5&nbsp;GHz
| rowspan="6" | 4.5&nbsp;GHz
| 12 MB
| 80 W
| $350
|-
| [https://ark.intel.com/content/www/us/en/ark/products/134862/intel-xeon-e2144g-processor-8m-cache-up-to-4-50-ghz.html 2144G]
| 4 (8)
| 3.6&nbsp;GHz
| 8 MB
| 71 W
| $306
|-
| [https://ark.intel.com/content/www/us/en/ark/products/134857/intel-xeon-e2136-processor-12m-cache-up-to-4-50-ghz.html 2136]
| 6 (12)
| 3.3&nbsp;GHz
| colspan="2" rowspan="2" | N/A
| 12 MB
| 80 W
| $319
|-
| [https://ark.intel.com/content/www/us/en/ark/products/134858/intel-xeon-e2134-processor-8m-cache-up-to-4-50-ghz.html 2134]
| 4 (8)
| 3.5&nbsp;GHz
| 8 MB
| 71 W
| $281
|-
| [https://ark.intel.com/content/www/us/en/ark/products/134863/intel-xeon-e2126g-processor-12m-cache-up-to-4-50-ghz.html 2126G]
| 6 (6)
| 3.3&nbsp;GHz
| rowspan="2" | [[Intel Graphics Technology#Kaby Lake Refresh / Amber Lake / Coffee Lake / Coffee Lake Refresh / Whiskey Lake / Comet Lake|UHD P630]]
| rowspan="2" | 1.20&nbsp;GHz
| 12 MB
| 80 W
| $286
|-
| [https://ark.intel.com/content/www/us/en/ark/products/134854/intel-xeon-e2124g-processor-8m-cache-up-to-4-50-ghz.html 2124G]
| rowspan="3" | 4 (4)
| 3.4&nbsp;GHz
| rowspan="3" | 8 MB
| rowspan="2" | 71 W
| $245
|-
| [https://ark.intel.com/content/www/us/en/ark/products/134856/intel-xeon-e2124-processor-8m-cache-up-to-4-30-ghz.html 2124]
| 3.3&nbsp;GHz
| 4.3&nbsp;GHz
| colspan="2" | N/A
| $217
|-
| [https://ark.intel.com/content/www/us/en/ark/products/134929/intel-xeon-e2104g-processor-8m-cache-3-20-ghz.html 2104G]
| 3.2&nbsp;GHz
| N/A
| [[Intel Graphics Technology#Kaby Lake Refresh / Amber Lake / Coffee Lake / Coffee Lake Refresh / Whiskey Lake / Comet Lake|UHD P630]]
| 1.20&nbsp;GHz
| 65 W
| $193
|}

=== Coffee Lake-E Refresh (Server/Workstation) ===
{| class="wikitable" style="text-align: center;"
|-
! Processor<br />branding
! Model
![[CPU core|Cores]]
([[Thread (computing)|Threads]])
! Base CPU<br />[[clock rate]]
! Max. [[Intel Turbo Boost|Turbo]]
clock rate
![[Intel HD and Iris Graphics|GPU]]
! max [[Graphics processing unit#Integrated graphics|GPU]]<br />clock rate
! L3<br />cache <ref group="note">MiB = MB = 1024&nbsp;kB</ref>
! TDP
! Memory<br />support
! Price<br />(USD)
|-
| rowspan="12" |Xeon E
|[https://ark.intel.com/content/www/us/en/ark/products/193743/intel-xeon-e-2288g-processor-16m-cache-3-70-ghz.html 2288G]
|8 (16)
|3.7&nbsp;GHz
|5.0&nbsp;GHz
| rowspan="7" |[[Intel Graphics Technology#Kaby Lake Refresh / Amber Lake / Coffee Lake / Coffee Lake Refresh / Whiskey Lake / Comet Lake|UHD P630]]
| rowspan="7" |1.20&nbsp;GHz
|16 MiB
| rowspan="2" |95 W
| rowspan="12" |Up to 128&nbsp;GB<ref group="note">GB = 1024&nbsp;MB = 1024^2&nbsp;kB = 1024^3 B</ref><br />DDR4 2666<br />[[ECC memory]]<br />supported
|$539
|-
|[https://ark.intel.com/content/www/us/en/ark/products/191033/intel-xeon-e-2286g-processor-12m-cache-4-00-ghz.html 2286G]
|6 (12)
|4.0&nbsp;GHz
|4.9&nbsp;GHz
|12 MiB
|$450
|-
|[https://ark.intel.com/content/www/us/en/ark/products/193745/intel-xeon-e-2278g-processor-16m-cache-3-40-ghz.html 2278G]
|8 (16)
|3.4&nbsp;GHz
|5.0&nbsp;GHz
|16 MiB
| rowspan="2" |80 W
|$494
|-
|[https://ark.intel.com/content/www/us/en/ark/products/191035/intel-xeon-e-2276g-processor-12m-cache-3-80-ghz.html 2276G]
|6 (12)
|3.8&nbsp;GHz
| rowspan="2" |4.9&nbsp;GHz
|12 MiB
|$362
|-
|[https://ark.intel.com/content/www/us/en/ark/products/191042/intel-xeon-e-2274g-processor-8m-cache-4-00-ghz.html 2274G]
|4 (8)
|4.0&nbsp;GHz
|8 MiB
|83 W
|$328
|-
|[https://ark.intel.com/content/www/us/en/ark/products/191043/intel-xeon-e-2246g-processor-12m-cache-3-60-ghz.html 2246G]
|6 (12)
|3.6&nbsp;GHz
| rowspan="4" |4.8&nbsp;GHz
|12 MiB
|80 W
|$311
|-
|[https://ark.intel.com/content/www/us/en/ark/products/191041/intel-xeon-e-2244g-processor-8m-cache-3-80-ghz.html 2244G]
|4 (8)
|3.8&nbsp;GHz
|8 MiB
|71 W
|$272
|-
|[https://ark.intel.com/content/www/us/en/ark/products/191040/intel-xeon-e-2236-processor-12m-cache-3-40-ghz.html 2236]
|6 (12)
|3.4&nbsp;GHz
| colspan="2" rowspan="2" |N/A
|12 MiB
|80 W
|$284
|-
|[https://ark.intel.com/content/www/us/en/ark/products/191039/intel-xeon-e-2234-processor-8m-cache-3-60-ghz.html 2234]
|4 (8)
|3.6&nbsp;GHz
|8 MiB
|71 W
|$250
|-
|[https://ark.intel.com/content/www/us/en/ark/products/191038/intel-xeon-e-2226g-processor-12m-cache-3-40-ghz.html 2226G]
|6 (6)
|3.4&nbsp;GHz
| rowspan="2" |4.7&nbsp;GHz
| rowspan="2" |[[Intel Graphics Technology#Kaby Lake Refresh / Amber Lake / Coffee Lake / Coffee Lake Refresh / Whiskey Lake / Comet Lake|UHD P630]]
| rowspan="2" |1.20&nbsp;GHz
|12 MiB
|80 W
|$255
|-
|[https://ark.intel.com/content/www/us/en/ark/products/191037/intel-xeon-e-2224g-processor-8m-cache-3-50-ghz.html 2224G]
| rowspan="2" |4 (4)
|3.5&nbsp;GHz
| rowspan="2" |8 MiB
| rowspan="2" |71 W
|$213
|-
|[https://ark.intel.com/content/www/us/en/ark/products/191036/intel-xeon-e-2224-processor-8m-cache-3-40-ghz.html 2224]
|3.4&nbsp;GHz
|4.6&nbsp;GHz
| colspan="2" |N/A
|$193
|}

== Comet Lake-based Xeon ==
{{Main|Comet Lake}}

== Cascade Lake-based Xeon ==
{{main|List of Intel Cascade Lake-based Xeon microprocessors}}

===Variants===
*Server: Cascade Lake-SP (Scalable Performance; meaning multi physical processors configuration), Cascade Lake-AP (Advanced Performance)
*Workstation: Cascade Lake-W
*Enthusiast: Cascade Lake-X

== Cooper Lake-based Xeon ==
{{main|Cooper Lake (microprocessor)}}The 3rd generation Xeon SP processors for 4S and 8S.

== Ice Lake-based Xeon ==
{{main|Ice Lake (microprocessor)}}The 3rd generation Xeon SP processors for WS, 1S and 2S.

== Rocket Lake-based Xeon ==
{{main|Rocket Lake}}

== Sapphire Rapids-based Xeon ==
{{main|Sapphire Rapids (microprocessor)}}Introduced in 2023, the '''4th generation Xeon Scalable''' processors ('''Sapphire Rapids-SP''' and '''Sapphire Rapids-HBM''') and '''Xeon W-2400''' and '''W-3400''' series ('''Sapphire Rapids-WS''') provide large performance enhancements over the prior generation.

=== Features ===

==== CPU ====
{{Further information|Golden Cove (microarchitecture)}}

* Up to 60 [[Golden Cove]] CPU cores per package
* [[AVX-512#FP16|AVX512-FP16]]
* [[Transactional Synchronization Extensions#TSX Suspend Load Address Tracking|TSX Suspend Load Address Tracking (<code>TSXLDTRK</code>)]]
* [[Advanced Matrix Extensions]] (AMX)
* Trust Domain Extensions (TDX), a collection of technologies to help deploy hardware-isolated virtual machines (VMs) called trust domains (TDs)
* In-Field Scan (IFS), a technology that allows for testing the processor for potential hardware faults without taking it completely offline
* Data Streaming Accelerator (DSA), allows for speeding up data copy and transformation between different kinds of storage
* QuickAssist Technology (QAT), allows for improved performance of compression and encryption tasks
* Dynamic Load Balancer (DLB), allows for offloading tasks of load balancing, packet prioritization and queue management
* In-Memory Analytics Accelerator (IAA), allows accelerating in-memory databases and big data analytics

Not all accelerators are available in all processor models. Some accelerators are available under the Intel On Demand program, also known as Software Defined Silicon (SDSi), where a license is required to activate a given accelerator that is physically present in the processor. The license can be obtained as a one-time purchase or as a paid subscription. Activating the license requires support in the operating system. A driver with the necessary support was added in Linux kernel version 6.2.

==== I/O ====

* [[PCI Express#PCI Express 5.0|PCI Express 5.0]]
* [[Direct Media Interface|Direct Media Interface 4.0]]
* 8-channel [[DDR5 SDRAM|DDR5]] memory support up to DDR5-4800, up to 2 DIMMs per channel
* On-package [[High Bandwidth Memory|High Bandwidth Memory 2e]] memory as L4 cache on Xeon Max models
* [[Compute Express Link]] 1.1

== Emerald Rapids-based Xeon ==
{{main|Emerald Rapids}}

== Granite Rapids-based Xeon ==
{{main|Granite Rapids}}

==Supercomputers==

By 2013 Xeon processors were ubiquitous in supercomputers—more than 80% of the [[TOP500]] machines in 2013 used them. For the fastest machines, much of the performance comes from compute accelerators; Intel's entry into that market was the [[Xeon Phi]], the first machines using it appeared in June 2012 and by June 2013 it was used in the fastest computer in the world.

* The first Xeon-based machines in the top-10 appeared in November 2002, two clusters at [[Lawrence Livermore National Laboratory]] and at [[National Oceanic and Atmospheric Administration|NOAA]].
* The first Xeon-based machine to be in the first place of the TOP500 was the Chinese [[Tianhe-I]]A in November 2010, which used a mixed Xeon-Nvidia GPU configuration; it was overtaken by the Japanese [[K computer]] in 2012, but the [[Tianhe-2]] system using 12-core Xeon E5-2692 processors and [[Xeon Phi]] cards occupied the first place in both TOP500 lists of 2013.
* The [[SuperMUC]] system, using eight-core Xeon E5-2680 processors but no accelerator cards, managed fourth place in June 2012 and had dropped to tenth by November 2013
* Xeon processor-based systems are among the top 20 fastest systems by memory bandwidth as measured by the STREAM benchmark.<ref>{{cite web |last=McCalpin |first=John D. |title=STREAM benchmark |url=http://www.cs.virginia.edu/stream/ |work=University of Virginia |language=en-US |access-date=December 10, 2022}}</ref>
* An Intel Xeon virtual SMP system using ScaleMP's Versatile SMP (vSMP) architecture with 128 cores and 1&nbsp;[[Tebibyte|TiB]] RAM.<ref>{{cite web |title=STREAM "Top20" results |url=http://www.cs.virginia.edu/stream/top20/Bandwidth.html |work=University of Virginia |language=en-US |access-date=December 10, 2022}}</ref> This system aggregates 16 Stoakley platform (Seaburg chipset) systems with total of 32 [[#5400-series "Harpertown"|Harpertown]] processors.

== See also ==
* [[Epyc|AMD Epyc]]
* [[Opteron|AMD Opteron]]
* [[Itanium|Intel Itanium]]
* Intel [[Xeon Phi]], brand name for family of products using the [[Intel MIC]] architecture
* [[List of Intel processors]]
** [[List of Intel Xeon processors]]
* [[List of Macintosh models grouped by CPU type]]

== Notes ==
{{notelist|group=note}}

== References ==
{{reflist|30em}}

== External links ==
{{Commons category|Xeon}}
* [http://www.intel.com/products/server/processors/index.htm Server processors at the Intel website]
* [https://web.archive.org/web/20150402103404/http://www.intel.com/content/dam/technology-provider/secure/us/en/documents/product-marketing-information/tst-grantley-launch-presentation-2014.pdf Intel look inside: Xeon E5 v3 (Grantley) launch], [[Intel]], September 2014

{{Intel processors|*}}

[[Category:Computer-related introductions in 1998]]
[[Category:Intel x86 microprocessors|Xeon]]