View source for VHDL

{{Short description|Hardware description language}}
{{For|Verilog HDL|Verilog}}
{{Multiple issues|
{{more citations needed|date=February 2017}}
{{Lead too short|date=December 2020}}
}}
{{Infobox <!--Hardware Description Language-->programming language
| name = VHDL
| logo = 
| paradigm = [[Concurrent computing|concurrent]], [[Reactive programming|reactive]], [[Dataflow programming|dataflow]]
| family = 
| year = 1980s
| designer = 
| developer = 
| latest_release_version = IEEE 1076-2019
| latest_release_date = {{start date and age|df=yes|2019|12|23}}
| latest_test_version = 
| latest_test_date = 
| typing = [[Strongly typed programming language|strong]]
| implementations = 
| dialects = [[VHDL-AMS]]
| influenced_by = [[Ada (programming language)|Ada]],<ref name="Coelho1989">{{cite book |author=David R. Coelho |title=The VHDL Handbook |url=https://books.google.com/books?id=IxZqlbYMJCIC&q=Ada |date=30 June 1989 |publisher=Springer Science & Business Media |isbn=978-0-7923-9031-2}}</ref> [[Pascal (programming language)|Pascal]]
| influenced = 
| operating_system = 
| license = 
| File extensions = .vhd
| website = [https://opensource.ieee.org/vasg IEEE VASG]
| wikibooks = Programmable Logic/VHDL
}}

[[File:Vhdl signed adder source.svg|thumb|VHDL source for a signed [[Adder (electronics)|adder]]]]

'''VHDL''' ([[VHSIC]] Hardware Description Language) is a [[hardware description language]] that can model the behavior and structure of [[digital systems]] at multiple levels of abstraction, ranging from the system level down to that of [[logic gates]], for design entry, documentation, and verification purposes. The language was developed for the US military VHSIC program in the 1980s, and has been standardized by the [[Institute of Electrical and Electronics Engineers]] (IEEE) as '''IEEE&nbsp;Std&nbsp;1076'''; the latest version of which is '''IEEE&nbsp;Std&nbsp;1076-2019'''. To model [[Analogue electronics|analog]] and [[mixed-signal]] systems, an IEEE-standardized HDL based on VHDL called [[VHDL-AMS]] (officially IEEE&nbsp;1076.1) has been developed.

==History==
In 1983, VHDL was originally developed at the behest of the [[U.S. Department of Defense]] in order to document the behavior of the [[ASIC]] that supplier companies were including in equipment. The standard MIL-STD-454N<ref name="mil454n">{{cite book |title= Military Standard, Standard general requirements for electronic equipment |year = 1992 |author= Department of Defense |url=http://everyspec.com/MIL-STD/MIL-STD-0300-0499/MIL-STD-454N_9160/ |access-date=November 15, 2017}}</ref> in Requirement 64 in section 4.5.1 "ASIC documentation in VHDL" explicitly requires documentation of "Microelectronic Devices" in VHDL.

The idea of being able to simulate the ASICs from the information in this documentation was so obviously attractive that [[Logic simulation|logic simulators]] were developed that could read the VHDL files. The next step was the development of [[logic synthesis]] tools that read the VHDL and output a definition of the physical implementation of the circuit.

Due to the Department of Defense requiring as much of the syntax as possible to be based on Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in the development of Ada,{{citation needed|date=November 2010}} VHDL borrows heavily from the [[Ada programming language]] in both concept and [[syntax]].

The initial version of VHDL, designed to [[IEEE]] standard IEEE 1076–1987,<ref name="originalversion">{{Cite book| title = 1076-1987 – IEEE Standard VHDL Language Reference Manual| doi = 10.1109/IEEESTD.1988.122645| year = 1988| isbn = 0-7381-4324-3}}</ref> included a wide range of data types, including numerical ([[integer]] and [[real data type|real]]), logical ([[bit]] and [[Boolean data type|Boolean]]), [[character (computing)|character]] and [[time]], plus [[Array data type|arrays]] of <code>bit</code> called <code>bit_vector</code> and of <code>character</code> called [[string (computer science)|string]].

A problem not solved by this edition, however, was "multi-valued logic", where a signal's [[drive strength]] (none, weak or strong) and unknown values are also considered. This required [[IEEE 1164|IEEE standard 1164]], which defined the 9-value logic types: scalar <code>std_logic</code> and its vector version <code>std_logic_vector</code>. Being a resolved subtype of its <code>std_Ulogic</code> parent type, <code>std_logic</code>-typed signals allow multiple driving for modeling bus structures, whereby the connected resolution function handles conflicting assignments adequately.

The updated [[IEEE 1076]], in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the <code>character</code> type to allow [[ISO-8859-1]] printable characters, added the <code>xnor</code> operator, etc.{{specify|date=November 2010}}

Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in [[C++]]) and removed some restrictions from port mapping rules.

In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introduced [[Signedness|signed and unsigned]] types to facilitate arithmetical operations on vectors. IEEE standard 1076.1 (known as [[VHDL-AMS]]) provided analog and mixed-signal circuit design extensions.

Some other standards support wider use of VHDL, notably '''VITAL''' (VHDL Initiative Towards ASIC Libraries)<ref>{{cite web |url=http://www.vhdl.renerta.com/mobile/source/vhd00080.htm |title=VHDL - VITAL |website=www.vhdl.renerta.com |url-status=dead |archive-url=https://web.archive.org/web/20111022082340/http://www.vhdl.renerta.com/mobile/source/vhd00080.htm |archive-date=2011-10-22}}</ref> and [[microwave]] circuit design extensions.

In June 2006, the VHDL Technical Committee of [[Accellera]] (delegated by IEEE to work on the next update of the standard) approved so-called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax of ''case'' and ''generate'' statements, incorporation of VHPI (VHDL Procedural Interface) (interface to C/C++ languages) and a subset of PSL ([[Property Specification Language]]). These changes should improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system-level descriptions.

In February 2008, Accellera approved VHDL 4.0, also informally known as VHDL 2008, which addressed more than 90 issues discovered during the trial period for version 3.0 and includes enhanced generic types. In 2008, Accellera released VHDL 4.0 to the IEEE for balloting for inclusion in IEEE 1076–2008. The VHDL standard IEEE 1076-2008<ref>{{Cite book |title = 1076-2008 – IEEE Standard VHDL Language Reference Manual |doi = 10.1109/IEEESTD.2009.4772740 |year = 2009 |isbn = 978-0-7381-6854-8}}</ref> was published in January 2009.

===Standardization===
The [[IEEE]] Standard 1076 defines the [[VHSIC]] [[Hardware Description Language]], or VHDL. It was originally developed under contract F33615-83-C-1003 from the [[United States Air Force]] awarded in 1983 to a team of Intermetrics, Inc. as language experts and prime contractor, [[Texas Instruments]] as chip design experts and [[IBM]] as computer-system design experts. The language has undergone numerous revisions and has a variety of sub-standards associated with it that augment or extend it in important ways.

IEEE Standard 1076 was and continues to be a milestone in the design of electronic systems.<ref>[https://ieee-p1076.gitlab.io/ IEEE P1076 Working Group VHDL Analysis and Standardization Group (VASG)]</ref>

====Revisions====
* IEEE 1076–1987<ref name="originalversion" /> First standardized revision of ver 7.2 of the language from the United States Air Force.
* IEEE 1076–1993<ref>{{Cite book |title = 1076-1993 – IEEE Standard VHDL Language Reference Manual |doi = 10.1109/IEEESTD.1994.121433 |year = 1994 |isbn = 0-7381-0986-X}}</ref> (also published with {{ISBN|1-55937-376-8}}). Significant improvements resulting from several years of feedback. Probably the most widely used version with the greatest vendor tool support.
* IEEE 1076–2000.<ref>{{Cite book |title = 1076-2000 – IEEE Standard VHDL Language Reference Manual |doi = 10.1109/IEEESTD.2000.92297 |year = 2000 |isbn = 0-7381-1948-2}}</ref> Minor revision. Introduces the use of ''protected types''.
* IEEE 1076–2002.<ref>{{Cite book |title = 1076-2002 – IEEE Standard VHDL Language Reference Manual |doi = 10.1109/IEEESTD.2002.93614 |year = 2002 |isbn = 0-7381-3247-0}}</ref> Minor revision of 1076–2000. Rules with regard to ''buffer ports'' are relaxed.
** IEC 61691-1-1:2004.<ref>{{Cite book |doi = 10.1109/IEEESTD.2004.95752 |title = IEC 61691-1-1 First edition 2004-10; IEEE 1076 — IEC/IEEE Behavioural Languages – Part 1-1: VHDL Language Reference Manual (Adoption of IEEE Std 1076-2002) |year = 2004 |isbn = 2-8318-7691-5}}</ref> IEC adoption of IEEE 1076–2002.
* IEEE 1076c–2007.<ref>{{Cite book |title = 1076c-2007 – IEEE Standard VHDL Language Reference Manual Amendment 1: Procedural Language Application Interface |doi = 10.1109/IEEESTD.2007.4299594 |year = 2007 |isbn = 978-0-7381-5523-4}}</ref> Introduced VHPI, the VHDL procedural interface, which  provides software with the means to access the VHDL model. The VHDL language required minor modifications to accommodate the VHPI.
* IEEE 1076–2008 (previously referred to as 1076–200x). Major revision released on 2009-01-26. Among other changes, this standard incorporates a basic subset of PSL, allows for generics on packages and subprograms and introduces the use of ''external names''.
** IEC 61691-1-1:2011.<ref>{{Cite book |doi = 10.1109/IEEESTD.2011.5967868 |title = 61691-1-1-2011 — Behavioural languages – Part 1-1: VHDL Language Reference Manual |year = 2011 |isbn = 978-0-7381-6605-6}}</ref> IEC adoption of IEEE 1076–2008.
* IEEE 1076–2019. Major revision.

====Related standards====
* IEEE 1076.1 VHDL Analog and Mixed-Signal ([[VHDL-AMS]])
* IEEE 1076.1.1 VHDL-AMS Standard Packages (stdpkgs)
* IEEE 1076.2 VHDL Math Package
* IEEE 1076.3 VHDL Synthesis Package (vhdlsynth) ([[numeric std]])
* IEEE 1076.3 VHDL Synthesis Package – Floating Point (fphdl)
* IEEE 1076.4 Timing (VHDL Initiative Towards ASIC Libraries: VITAL)
* IEEE 1076.6 VHDL Synthesis Interoperability (withdrawn in 2010)<ref>{{Cite web|url=https://standards.ieee.org/ieee/1076.6/3466/|title = IEEE 1076.6-2004 - IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis}}</ref>
* [[IEEE 1164]] VHDL Multivalue Logic (std_logic_1164) Packages

==Design==
VHDL is generally used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a ''testbench''.

A VHDL simulator is typically an [[Event-driven architecture|event-driven]] simulator.<ref>{{cite web|title=ELEC3017 - Simulation|url=http://users.ecs.soton.ac.uk/mz/elec3017/vhdlsim.pdf |archive-url=https://web.archive.org/web/20170223213703/http://users.ecs.soton.ac.uk/mz/elec3017/vhdlsim.pdf |archive-date=2017-02-23 |url-status=live|publisher=University of Southampton|access-date=23 February 2017}}</ref> This means that each transaction is added to an event queue for a specific scheduled time. For example, if a signal assignment should occur after 1 nanosecond, the event is added to the queue for time +1ns. Zero delay is also allowed, but still needs to be scheduled: for these cases [[delta delay]] is used, which represent an infinitely small time step. The simulation alters between two modes: statement execution, where triggered statements are evaluated, and event processing, where events in the queue are processed.

VHDL has constructs to handle the [[parallel computing|parallelism]] inherent in hardware designs, but these constructs (''processes'') differ in syntax from the parallel constructs in Ada (''tasks''). Like Ada, VHDL is [[strongly typed]] and is not [[case sensitive]]. In order to directly represent operations which are common in hardware, there are many features of VHDL which are not found in Ada, such as an extended set of Boolean operators including '''nand''' and '''nor'''.

VHDL has file input and output capabilities, and can be used as a general-purpose language for text processing, but files are more commonly used by a simulation testbench for stimulus or verification data. There are some VHDL compilers which build executable binaries. In this case, it might be possible to use VHDL to write a ''testbench'' to verify the functionality of the design using files on the host computer to define stimuli, to interact with the user, and to compare results with those expected. However, most designers leave this job to the simulator.

It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is the accidental production of [[transparent latch]]es rather than [[Flip-flop (electronics)#D flip-flop|D-type flip-flops]] as storage elements.<ref>{{cite web|title=Why should I care about Transparent Latches?|url=http://www.doulos.com/knowhow/fpga/latches/|publisher=Doulos|access-date=22 December 2012|archive-date=20 January 2013|archive-url=https://web.archive.org/web/20130120063501/http://www.doulos.com/knowhow/fpga/latches/|url-status=dead}}</ref>

One can design hardware in a VHDL IDE (for FPGA implementation such as Xilinx ISE, Altera Quartus, Synopsys Synplify, or Mentor Graphics HDL Designer) to produce the [[Register-transfer level|RTL]] schematic of the desired circuit. After that, the generated schematic can be verified using simulation software which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. To generate an appropriate testbench for a particular circuit or VHDL code, the inputs have to be defined correctly. For example, for clock input, a loop process or an iterative statement is required.<ref>{{Cite web |title=Clock Generation - VHDL Designers Guide |url=http://www.doulos.com/knowhow/vhdl_designers_guide/tips/clock_generation/|publisher=Doulos|access-date=22 December 2012 |archive-date=20 January 2013 |archive-url=https://web.archive.org/web/20130120063313/http://www.doulos.com/knowhow/vhdl_designers_guide/tips/clock_generation/ |url-status=dead}}</ref>

It is important to note that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a [[CPLD]] or [[FPGA]], then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip.

==Advantages==
The key advantage of VHDL, when used for systems design, is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of a [[concurrent system]]. VHDL is a [[dataflow language]] in which every statement is considered for execution simultaneously, unlike procedural computing languages such as BASIC, C, and assembly language, where a sequence of statements is run sequentially one instruction at a time.

A VHDL project is multipurpose. Being created once, a calculation block can be used in many other projects. However, many formational and functional block parameters can be tuned (capacity parameters, memory size, element base, block composition and interconnection structure).

A VHDL project is portable. Being created for one element base, a computing device project can be ported on another element base; for example, [[VLSI]] with various technologies.

A big advantage of VHDL compared to original [[Verilog]] is that VHDL has a full [[type system]]. Designers can use the type system to write much more structured code (especially by declaring [[Record (computer science)|record]] types).<ref>{{cite web |url=http://gaisler.com/doc/structdesign.pdf |archive-url=https://ghostarchive.org/archive/20221010/http://gaisler.com/doc/structdesign.pdf |archive-date=2022-10-10 |url-status=live |access-date=15 November 2017 |title=A structured VHDL Design Method |author=Jiri Gaisler}}</ref>

==Design examples==
{{how-to|section|date=January 2013}}
In VHDL, a design consists at a minimum of an ''entity'' which describes the interface and an ''architecture'' which contains the actual implementation. In addition, most designs import library modules. Some designs also contain multiple architectures and ''configurations''.

A simple [[Logic gate|AND gate]] in VHDL would look something like:
<syntaxhighlight lang="vhdl">
-- (this is a VHDL comment)
/*
    this is a block comment (VHDL-2008)
*/
-- import std_logic from the IEEE library
library IEEE;
use IEEE.std_logic_1164.all;

-- this is the entity
entity ANDGATE is
  port ( 
    I1 : in std_logic;
    I2 : in std_logic;
    O  : out std_logic);
end entity ANDGATE;

-- this is the architecture
architecture RTL of ANDGATE is
begin
  O <= I1 and I2;
end architecture RTL;
</syntaxhighlight>

(Notice that <code>RTL</code> stands for ''[[Register transfer level]]'' design.) While the example above may seem verbose to HDL beginners, many parts are either optional or need to be written only once. Generally, simple functions like this are part of a larger behavioral module, instead of having a separate module for something so simple. In addition, use of elements such as the <code>std_logic</code> type might at first seem to be an overkill. One could easily use the built-in <code>bit</code> type and avoid the library import in the beginning. However, using a form of [[many-valued logic]], specifically [[9-valued logic]] (<code>U</code>,<code>X</code>,<code>0</code>,<code>1</code>,<code>Z</code>,<code>W</code>,<code>H</code>,<code>L</code>,<code>-</code>), instead of simple bits (0,1) offers a very powerful simulation and debugging tool to the designer which currently does not exist in any other HDL.

In the examples that follow, one will see that VHDL code can be written in a very compact form. However, more experienced designers usually avoid these compact forms and use a more verbose coding style for the sake of readability and maintainability.

===Synthesizable constructs and VHDL templates===
VHDL is frequently used for two different goals: simulation of electronic designs and synthesis of such designs. Synthesis is a process where a VHDL is compiled and mapped into an implementation technology such as an FPGA or an ASIC.

Not all constructs in VHDL are suitable for synthesis. For example, most constructs that explicitly deal with timing such as <code>wait for 10 ns;</code> are not synthesizable despite being valid for simulation. While different synthesis tools have different capabilities, there exists a common ''synthesizable subset'' of VHDL that defines what language constructs and idioms map into common hardware for many synthesis tools. IEEE 1076.6 defines a subset of the language that is considered the official synthesis subset. It is generally considered a "best practice" to write very idiomatic code for synthesis as results can be incorrect or suboptimal for non-standard constructs.

===MUX template===
The [[multiplexer]], or 'MUX' as it is usually called, is a simple construct very common in hardware design. The example below demonstrates a simple two to one MUX, with inputs <code>A</code> and <code>B</code>, selector <code>S</code> and output <code>X</code>. Note that there are many other ways to express the same MUX in VHDL.<ref>{{cite web |url=https://www.fpgatutorial.com/vhdl-logical-operators-and-signal-assignments-for-combinatorial-logic/#vhdl-mux |title=VHDL Logical Operators and Signal Assignments for Combinatorial Logic |website=FPGAtutorial |date=16 May 2020 |access-date=2020-08-23}}</ref>
<syntaxhighlight lang="VHDL">X <= A when S = '1' else B;</syntaxhighlight>

A more complex example of a MUX with 4×3 inputs and a 2-bit selector:
<syntaxhighlight lang="vhdl">
library IEEE;
use IEEE.std_logic_1164.all;
entity mux4 is
  port(
    a1      : in  std_logic_vector(2 downto 0);
    a2      : in  std_logic_vector(2 downto 0);
    a3      : in  std_logic_vector(2 downto 0);
    a4      : in  std_logic_vector(2 downto 0);
    sel     : in  std_logic_vector(1 downto 0);
    b       : out std_logic_vector(2 downto 0)
  );
end mux4;
architecture rtl of mux4 is
  -- declarative part: empty
begin
  p_mux : process(a1,a2,a3,a4,sel)
  begin
    case sel is
      when "00" => b <= a1 ;
      when "01" => b <= a2 ;
      when "10" => b <= a3 ;
      when others => b <= a4 ;
    end case;
  end process p_mux;
end rtl;
</syntaxhighlight>

===Latch template===
A [[transparent latch]] is basically one bit of memory which is updated when an enable signal is raised. Again, there are many other ways this can be expressed in VHDL.

<syntaxhighlight lang="vhdl">
-- latch template 1:
Q <= D when Enable = '1' else Q;

-- latch template 2:
process(all)
begin
    Q <= D when(Enable);
end process;
</syntaxhighlight>

===D-type flip-flops===
The D-type [[Flip-flop (electronics)|flip-flop]] samples an incoming signal at the rising (or falling) edge of a clock. This example has an asynchronous, active-high reset, and samples at the rising clock edge.
<syntaxhighlight lang="vhdl">
DFF : process(all) is
begin
  if RST then
    Q <= '0';
  elsif rising_edge(CLK) then
    Q <= D;
  end if;
end process DFF;
</syntaxhighlight>

Another common way to write edge-triggered behavior in VHDL is with the 'event' signal attribute. A single apostrophe has to be written between the signal name and the name of the attribute.
<syntaxhighlight lang="vhdl">
DFF : process(RST, CLK) is
begin
  if RST then
    Q <= '0';
  elsif CLK'event and CLK = '1' then
    Q <= D;
  end if;
end process DFF;
</syntaxhighlight>

VHDL also lends itself to "one-liners" such as:
<syntaxhighlight lang="VHDL">
DFF : Q <= '0' when RST = '1' else D when rising_edge(clk);
</syntaxhighlight>

or:

<syntaxhighlight lang="vhdl">
DFF : process(all) is 
begin
  if rising_edge(CLK) then
    Q <= D;
  end if;
  if RST then
    Q <= '0';
  end if;
end process DFF;

</syntaxhighlight>
or:<syntaxhighlight lang="vhdl">
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity RisingEdge_DFlipFlop_SyncReset is
  port(
    Q          :   out std_logic;    
    Clk        : in    std_logic;  
    sync_reset : in    std_logic;  
    D          : in    std_logic    
  );
end RisingEdge_DFlipFlop_SyncReset;

architecture Behavioral of RisingEdge_DFlipFlop_SyncReset is
begin
  process(Clk)
  begin 
    if (rising_edge(Clk)) then
      if (sync_reset='1') then 
        Q <= '0';
      else 
        Q <= D; 
      end if;
    end if;       
  end process;  
end Behavioral;
</syntaxhighlight>Which can be useful if not all signals (registers) driven by this process should be reset.

===Example: a counter===
The following example is an up-counter with asynchronous reset, parallel load and configurable width. It demonstrates the use of the 'unsigned' type, type conversions between 'unsigned' and 'std_logic_vector' and VHDL ''generics''. The generics are very close to arguments or templates in other traditional programming languages like C++. The example is in VHDL 2008 language.
<syntaxhighlight lang="vhdl">
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;    -- for the unsigned type

entity COUNTER is
  generic (
    WIDTH : in natural := 32);
  port (
    RST   : in std_logic;
    CLK   : in std_logic;
    LOAD  : in std_logic;
    DATA  : in std_logic_vector(WIDTH-1 downto 0);
    Q     : out std_logic_vector(WIDTH-1 downto 0));
end entity COUNTER;

architecture RTL of COUNTER is

begin

  process(all) is
  begin
    if RST then
      Q <= (others => '0');
    elsif rising_edge(CLK) then
      if LOAD='1' then
        Q <= DATA;
      else
        Q <= std_logic_vector(unsigned(Q) + 1);
      end if;
    end if;
  end process;

end architecture RTL;
</syntaxhighlight>

More complex counters may add if/then/else statements within the <code>rising_edge(CLK) elsif</code> to add other functions, such as count enables, stopping or rolling over at some count value, and generating output signals like terminal count signals. Care must be taken with the ordering and nesting of such controls if used together, in order to produce the desired priorities and minimize the number of logic levels needed.

===Simulation-only constructs===
A large subset of VHDL cannot be translated into hardware. This subset is known as the non-synthesizable or the simulation-only subset of VHDL and can only be used for prototyping, simulation and debugging. For example, the following code will generate a clock with a frequency of 50&nbsp;MHz. It can, for example, be used to drive a clock input in a design during simulation. It is, however, a simulation-only construct and cannot be implemented in hardware. In actual hardware, the clock is generated externally; it can be scaled down internally by user logic or dedicated hardware.
<syntaxhighlight Lang="VHDL">
process
begin
  CLK <= '1'; wait for 10 NS;
  CLK <= '0'; wait for 10 NS;
end process;
</syntaxhighlight>

The simulation-only constructs can be used to build complex waveforms in a very short time. Such waveforms can be used, for example, as test vectors for a complex design or as a prototype of some synthesizer logic that will be implemented in the future.
<syntaxhighlight Lang="VHDL">
process
begin
  wait until START = '1'; -- wait until START is high
  
  for i in 1 to 10 loop -- then wait for a few clock periods...
    wait until rising_edge(CLK);
  end loop;

  for i in 1 to 10 loop 	-- write numbers 1 to 10 to DATA, 1 every cycle
    DATA <= to_unsigned(i, 8);
    wait until rising_edge(CLK);
  end loop;

  -- wait until the output changes
  wait on RESULT;
  
  -- now raise ACK for clock period
  ACK <= '1';
  wait until rising_edge(CLK);
  ACK <= '0';

  -- and so on...
end process;
</syntaxhighlight>

== VHDL-2008 Features==

===Hierarchical Aliases===
<syntaxhighlight lang="vhdl">
library ieee;
use ieee.std_logic_1164.all;

entity bfm is end entity;
architecture beh of bfm is
    signal en   :std_logic;
begin
    -- insert implementation here
end architecture;

//------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity test1 is end entity;
architecture beh of test1 is
begin

    ibfm: entity work.bfm;
	
    -- The testbench process
    process
      alias probe_en   is <<signal .test1.ibfm.en :std_logic>>;
    begin
        probe_en   <= '1';
        wait for 100 ns;
        probe_en   <= '0';		
        wait for 100 ns;
        probe_en   <= '1';		
        wait for 100 ns;        
        std.env.stop(0);
    end process;
	
end architecture;
</syntaxhighlight>

== Standard libraries ==
Also referred as standard packages.

=== IEEE Standard Package ===
The IEEE Standard Package includes the following:<ref>{{Cite web|last=Chiusano|first=Silvia|date=April 5, 2011|title=VHDL Data types and Operators available in the IEEE Standard Packages|url=http://www-micro.deis.unibo.it/~drossi/Dida02/lezioni/IEEE_Standard_Packages.pdf |archive-url=https://ghostarchive.org/archive/20221010/http://www-micro.deis.unibo.it/~drossi/Dida02/lezioni/IEEE_Standard_Packages.pdf |archive-date=2022-10-10|url-status=live|publisher=[[Polytechnic University of Turin]]}}</ref>

* '''[[numeric_std]]'''
* [[Std logic|'''std_logic_1164''']]
** std_logic_arith
** std_logic_unsigned
** std_logic_signed
** std_logic_misc

==VHDL simulators==
{{Main|List of HDL simulators}}
Commercial:
* Aldec [[Aldec#Software|Active-HDL]]
* [[Cadence Design Systems|Cadence]] [[NCSim|Incisive]]
* Mentor Graphics [[ModelSim]]
* Mentor Graphics [[QuestaSim|Questa Advanced Simulator]]
* [[Synopsys]] VCS-MX<ref>{{cite web
 |title = VCS: Industry's Highest Performance Simulation Solution
 |website = synopsis.com
 |url = https://www.synopsys.com/verification/simulation/vcs.html
}}</ref>
* [[Xilinx]] [[Xilinx Vivado|Vivado Design Suite]] (features the Vivado Simulator)
Other:
* [http://www.edaplayground.com EDA Playground] is a free web-based VHDL IDE (uses Synopsys VCS, Cadence Incisive, Aldec [[Aldec#Software|Riviera-PRO]] and GHDL for VHDL simulation)
* [http://ghdl.free.fr/ GHDL] is an [[open-source software|open source]]<ref>{{cite web
 |title = Copyrights {{!}} Licenses
 |work = GHDL Documentation -- GHDL 0.36-dev documentation
 |publisher = readthedocs.io
 |url = https://ghdl.readthedocs.io/en/latest/licenses.html
 }}{{Dead link|date=September 2025 |bot=InternetArchiveBot }}</ref> VHDL compiler that can execute VHDL programs. ({{GitHub|ghdl/GHDL}})
* [http://www.freerangefactory.org/boot.html boot] by freerangefactory.org is a VHDL compiler and simulator based on GHDL and [https://gtkwave.sourceforge.net/ GTKWave].
* {{web archive |url=https://web.archive.org/web/20071002043112/http://www.symphonyeda.com/ |title=Simili by Symphony EDA is a free commercial VHDL simulator}}
* [https://github.com/nickg/nvc nvc] by Nick Gasson is an open source VHDL compiler and simulator.<ref>{{cite web
 |title = Writing a VHDL compiler
 |last = Gasson |first = Nick
 |date = November 5, 2011
 |url = https://www.doof.me.uk/2011/11/05/writing-a-vhdl-compiler/
}}</ref><ref>{{cite web
 |title = NVC - VHDL Compiler and Simulator
 |last = Gasson |first = Nick
 |date = July 22, 2023
 |access-date = July 23, 2023
 |url = https://www.nickg.me.uk/nvc/
}}</ref>
* [http://freehdl.seul.org/ freehdl] by Edwin Naroska was an open source VHDL simulator, abandoned since 2001.<ref>{{cite web
 |title = freehdl: By Thread
 |url = https://list.gatech.edu/archives/freehdl/
 |archive-url = https://web.archive.org/web/20020210120248/https://list.gatech.edu/archives/freehdl/
 |archive-date = February 10, 2002
 |url-status = dead
}}</ref>

==See also==
{{cmn|
* [[Altera Hardware Description Language]] (AHDL)
* [[Chisel (programming language)|Chisel]]
* [[Gezel]]
* [[numeric std]], a standard package which provides arithmetic functions for vectors
* [[SystemC]]
* [[SystemVerilog]]
* [[Verilog]]
* [[List of HDL simulators]]
}}

==References==
{{Reflist}}
;Notes
{{Refbegin}}
*{{Cite book| title = 1076/INT-1991 – IEEE Standards Interpretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual| doi = 10.1109/IEEESTD.1992.101084| year = 1992| isbn = 0-7381-0987-8}}
{{Refend}}

==Further reading==
* {{cite book |first=Peter J. |last=Ashenden |title=The Designer's Guide to VHDL, Third Edition (Systems on Silicon) |year=2008 |isbn=978-0-1208-8785-9}} (The VHDL reference book written by one of the lead developers of the language)
* Bryan Mealy, Fabrizio Tappero (February 2012). [https://web.archive.org/web/20150213223327/http://www.freerangefactory.org/dl/free_range_vhdl.pdf]. The no-frills guide to writing powerful VHDL code for your digital implementations. Archived from the original [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL] on 2015-02-13.
* {{cite news|title=Comparing Verilog to VHDL Syntactically and Semantically|author=Johan Sandstrom|publisher=EE Times|date=October 1995|work=Integrated System Design|url=http://www.sandstrom.org/systemde.htm}} &mdash; Sandstrom presents a table relating VHDL constructs to [[Verilog]] constructs.
* {{cite web|url=https://www.isy.liu.se/edu/kurs/TSEA83/kursmaterial/vhdl/vhdlqrc.pdf|title=VHDL quick reference card|publisher=Qualis Design Corporation|author=Qualis Design Corporation|date=2000-07-20|version=1.1|archive-url=https://web.archive.org/web/20031210094512/http://www.eda.org/rassp/vhdl/guidelines/vhdlqrc.pdf|archive-date=2003-12-10}}
* {{cite web|url=https://www.ece.ualberta.ca/~elliott/cmpe480/refcards/1164qrc.pdf|title=1164 packages quick reference card|publisher=Qualis Design Corporation|author=Qualis Design Corporation|date=2000-07-20|version=1.0|archive-url=https://web.archive.org/web/20160314065505/http://eda.org/rassp/vhdl/guidelines/1164qrc.pdf|archive-date=2016-03-14}}
* Janick Bergeron, "Writing Testbenches: Functional Verification of HDL Models", 2000, {{ISBN|0-7923-7766-4}}. (The HDL Testbench Bible)
*{{cite book |last1=Krolikoski |first1=S.J. |chapter=Standardizing ASIC libraries in VHDL using VITAL: A tutorial |title=Proceedings of the IEEE 1995 Custom Integrated Circuits Conference |date=May 1995 |pages=603–610 |doi=10.1109/CICC.1995.518256 |isbn=0-7803-2584-2 |language=en}}
*{{cite web |last1=Vreeland |first1=Russell E. |title=Connecting the System to the Chip: Using VHDL/VITAL for Board-level Simulation |url=https://freemodelfoundry.com/pdf/hsesdc.pdf |access-date=12 May 2025}}
*{{cite book |last1=Rushton |first1=Andrew |title=VHDL for logic synthesis |date=2011 |publisher=[[Wiley (publisher)|Wiley]] |location=Chichester, West Sussex, U.K |isbn=9780470977972 |page=4 |edition=3rd}}
*{{cite web |last1=Vreeland |first1=Russell E. |title=Board-level component modeling using VITAL |url=https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=acb2ac5719a7020dd8e2f6e7ecb723f0d5173c57 |access-date=12 May 2025}}
*{{cite book |last1=Tuzov |first1=Ilya |last2=Ruiz |first2=Juan-Carlos |last3=de Andrés |first3=David |chapter=Accurately Simulating the Effects of Faults in VHDL Models Described at the Implementation-Level |title=2017 13th European Dependable Computing Conference (EDCC) |date=September 2017 |pages=10–17 |doi=10.1109/EDCC.2017.26 |publisher=[[Institute of Electrical and Electronics Engineers]] |isbn=978-1-5386-0602-5 }}

==External links==
{{Commons category}}
{{Wikibooks|Programmable Logic|VHDL}}
* {{Official website|http://www.vhdl.org/}}
* [http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome VHDL Analysis and Standardization Group (VASG)]

{{IEEE standards}}
{{Programmable Logic}}
{{Authority control}}

{{DEFAULTSORT:Vhdl}}
[[Category:Hardware description languages]]
[[Category:IEEE standards]]
[[Category:IEC standards]]
[[Category:Ada programming language family]]
[[Category:Domain-specific programming languages]]
[[Category:Programming languages created in 1983]]