View source for Unified Power Format

{{short description|IEEE standard}}
'''Unified Power Format''' (UPF) is the popular name of the  [[Institute of Electrical and Electronics Engineers]] (IEEE)  standard for specifying power intent in [[Power optimization (EDA)|power optimization]] of [[electronic design automation]]. The '''IEEE 1801'''-2009 release of the standard was based on a donation from the [[Accellera]] organization. The current release is IEEE 1801-2024.

==History==
A Unified Power Format technical committee was formed by the [[Accellera]] organization, chaired by Stephen Bailey of [[Mentor Graphics]].
As a reaction to the Power Forward Initiative the group was proposed in July 2006 and met on September 13, 2006.<ref>{{cite news |title= Accellera rolls power plan |author= Richard Goering |date= September 18, 2006 |work= EE Times |url= http://www.eetimes.com/electronics-news/4065349/Accellera-rolls-power-plan |access-date= July 7, 2011 }}</ref>
It submitted its first draft in January 2007, and a version 1.0 was approved to be published on February 26, 2007.<ref>{{cite web |title= Documents from Group 'Unified Power Format Technical Committee' |work= Accellera public groups area |url= http://www.accellera.org/apps/group_public/documents.php?wg_abbrev=upf |access-date= July 7, 2011 }}</ref>
Joe Daniels was technical editor.<ref>{{cite web |title= Unified Power Format (UPF) Standard Version 1.0 |publisher= Accellera |url= http://www.accellera.org/apps/group_public/download.php/989/upf.v1.0.pdf |access-date= August 7, 2011 }}</ref>

Files written to this standard annotate an electric design with the power and power control intent of that design. Elements of that annotation include:
* Power Supplies: supply nets, supply sets, power states
* Power Control: power switches
* Additional Protection: level shifters and isolation
* Memory retention during times of limited power: retention strategies and supply set power states
* Refinable descriptions of the potential power applied to the electronic system: power states, transitions, a set of simstate{{typo help inline|date=November 2021}}, power/ground pin type (pg_type) and function attributes of nets, and the -update argument to support the progressive refinement of the power intent.
The standard describes extensions to the [[Tcl|Tool Command Language]] (Tcl): commands and arguments for annotating a design hierarchy which has been read into a tool.
Semantics for inferring additional elements in the design from the intent are provided in the standard.
Digital designers, IP Block providers, Physical Designers, and Verification engineers make use of this standard language to communicate their design intent and implementation with respect to the variable power of an electronic system.

The [[Design Automation Standards Committee]] (DASC) of the [[IEEE Standards Association]] sponsored working group 1801, with the project authorization approved on May 7, 2007.<ref>{{cite web |title= P1801 - Standard for Design and Verification of Low Power Integrated Circuits |author= Sherry Hampton |publisher= IEEE Standards Association Standards Board |date= May 9, 2007 |url= http://standards.ieee.org/about/sasb/nescom/projects/1801.pdf |archive-url= https://web.archive.org/web/20160304080819/http://standards.ieee.org/about/sasb/nescom/projects/1801.pdf |url-status= dead |archive-date= March 4, 2016 |access-date= July 7, 2011 }}</ref><ref name="hm">{{cite web |title= P1801 Low Power Study Group By Thread |work= Hypermail archive |url= http://www.eda.org/p1801/hm/ |access-date= July 7, 2011 }}</ref>
Goals included:
* clarify the semantics of the intent - this provides portability of design intent across many vendors tools
* Add support for incremental refinement - Platinum source (constraints) from IP vendors, Golden source (configuration) from IP integrators, and Silicon source (implementation choices) from those that realize the instantiations.
* Add support for bottom up and top down design
* add documentation of the support for wildcard and regular expression selection of design instances
* clarify the differences between ports and pins
* provide for convergence capability from both UPF and [[Common Power Format]] of the [[Silicon Integration Initiative]] (Si2)
The IEEE group was initially called the "Low Power Study Group". Proposed standards have the letter "P" in front of them (such as P1801), which is removed and replaced with a dash and year when the standard is ratified.
Accelera's UPF 1.0 was donated to the IEEE as a basis of this standard in June 2006.<ref>{{cite web |title= IEEE P1801 - Unified Power Format Standard |publisher= Accelera Organization Inc.|url= http://www.accellera.org/activities/p1801_upf/ |access-date= July 7, 2011 }}</ref>

After reviewing 14 drafts, on March 27, 2009, the "Standard for Design and Verification of Low Power Integrated Circuits" was published as IEEE Std 1801-2009.<ref>{{cite book |title= 1801-2009 - IEEE Standard for Design and Verification of Low Power Integrated Circuits |url= https://standards.ieee.org/ieee/1801/4189/ |access-date= July 6, 2011 |author= UPF: Standard for Design and Verification of Low Power Integrated Circuits |publisher= IEEE Standards Association |doi=10.1109/IEEESTD.2009.4809845 |date= March 27, 2009 |isbn= 978-0-7381-5930-0 }}</ref> It is sometimes called UPF 2.0.
Bailey was also chairman of the IEEE group.<ref>{{cite news |title= IEEE approves low-power design spec |author= Nic Mokhoff |date= March 20, 2009 |work= EE Times |url= http://www.eetimes.com/electronics-news/4081876/IEEE-approves-low-power-design-spec |access-date= July 7, 2011 }}</ref>
Another notable supporter of the standard was [[Synopsys]].<ref>{{cite web |title= IEEE 1801-2009 ― Unified Power Format (UPF) |publisher= Synopsys |url= http://www.synopsys.com/community/interoperability/pages/upfstandard.aspx |access-date= July 7, 2011 }}</ref>
A follow-on project planned to develop a list of frequently asked questions (FAQ) about the specification.<ref name="hm"/>

== References ==
{{Reflist}}
*{{Cite book| title = 1801-2009 — IEEE Standard for Design and Verification of Low Power Integrated Circuits| doi = 10.1109/IEEESTD.2009.4809845| year = 2009| isbn = 978-0-7381-5929-4}}
*{{Cite book| title = 1801-2013 — IEEE Standard for Design and Verification of Low-Power Integrated Circuits| doi = 10.1109/IEEESTD.2013.6521327| year = 2013| isbn = 978-0-7381-8281-0}}
*{{Cite book| title = 1801-2015 — IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems| doi = 10.1109/IEEESTD.2016.7445797| year = 2016| isbn = 978-1-5044-0105-0}}
*{{Cite book| title = 1801-2018 — IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems| doi = 10.1109/IEEESTD.2019.8686430| year = 2019| isbn = 978-1-5044-5258-8}}

== External links ==
* [https://ieeexplore.ieee.org/document/8686430 IEEE 1801-2018] - free download of the standard.

{{Programmable Logic}}
{{IEEE standards}}

[[Category:Power standards]]
[[Category:IEEE DASC standards]]
[[Category:Electronics standards]]