View source for Unicore

{{For|the grid computing technology|UNICORE}}
{{Infobox CPU architecture
| name       = Unicore
| designer   = Microprocessor Research and Development Center
| bits       = 32-bit
| introduced = 1999
| version    = 
| design     = RISC
| type       = 
| encoding   = Fixed
| branching  = Condition code
| endianness = Little
| page size  = 4 KiB
| extensions = 
| open       = 
| registers  = 
| gpr        = 31
| fpr        = 32
}}
'''Unicore''' is a computer [[instruction set]] architecture designed by the Microprocessor Research and Development Center (MPRC) of [[Peking University]] in the [[People's Republic of China|PRC]]. The computer built on this architecture is called the [[Unity-863]].<ref>{{cite web|url=http://mprc.pku.cn/eng/intro.html |title=Introduction to MPRC |publisher=Microprocessor Research and Develop Center, Peking University}}</ref>
The CPU is integrated into a fully functional SoC to make a PC-like system.<ref>{{Citation |author1=Xu Cheng |author2=Xiaoyin Wang |author3=Junlin Lu |author4=Jiangfang Yi |author5=Dong Tong |author6=Xuetao Guan |author7=Feng Liu |author8=Xianhua Liu |author9=Chun Yang |author10=Yi Feng |title=Research Progress of UniCore CPUs and PKUnity SoCs |journal=Journal of Computer Science and Technology  |date=March 2010 |volume=25 |number=2 |pages=200–213 |doi=10.1007/s11390-010-9317-1 |s2cid=7083916 |url=http://mprc.pku.edu.cn/~guanxuetao/publications/2010-JCST-CX.pdf |access-date=2012-07-11}}</ref>

The processor is very similar to the [[ARM architecture]], but uses a different instruction set.<ref>{{Cite mailing list |url=http://marc.info/?l=linux-kernel&m=134184818409286 |title=Re: &#91;PATCH 00/36&#93; AArch64 Linux kernel port |date=2012-07-09 |access-date=2012-07-11 |mailing-list=linux-kernel |last=Bergmann |first=Arnd |quote=Another interesting example is unicore32, which actually shares more code with arch/arm than the proposed arch/aarch64 does. I think the unicore32 code base would benefit from being merged back into arch/arm as a third instruction set, but the additional maintenance cost for everyone working on ARM makes that unrealistic.}}</ref>{{Better source needed|date=July 2012}}

It is supported by the [[Linux kernel]] as of version 2.6.39.<ref>{{cite web |url=https://lkml.org/lkml/2011/3/29/351 |title=Merge window closed - 2.6.39-rc1 out |publisher=[[Linus Torvalds]]}}</ref>
Support will be removed in [[Linux kernel]] version 5.9 as nobody seems to maintain it and the code is falling behind the rest of the kernel code and compiler requirements.<ref>{{cite web |url=https://lkml.org/lkml/2020/8/3/232 |title=remove unicore32 support|publisher=Mike Rapoport}}</ref>

==Instruction set==
The instructions are almost identical to the standard ARM formats, except that conditional execution has been removed, and the bits reassigned to expand all the register specifiers to 5 bits.<ref>{{Citation |contribution=Doubling the Number of Registers on ARM Processors |contribution-url=http://aces.snu.ac.kr/interact-16/papers/interact-16-paper-1.pdf |author1=Hsu-Hung Chiang |author2=Huang-Jia Cheng |author3=Yuan-Shin Hwan |date=2012-02-25 |title=16th Workshop on Interaction between Compilers and Computer Architectures (INTERACT) |pages=1–8 |isbn=978-1-4673-2613-1 |doi=10.1109/INTERACT.2012.6339620|s2cid=6832041 }}</ref><ref>[https://code.google.com/p/minic/source/browse/trunk/simulator/ Unicore processor simulator source code].  Instruction formats are in decode.c, disassembly in interpret.c, and emulation in instEx.c.</ref>  Likewise, the immediate format is 9 bits rotated by a 5-bit amount (rather than 8 bit rotated by 4), the load/store offset sizes are 14 bits for byte/word and 10 bits for signed byte or half-word.  Conditional moves are provided by encoding the condition in the (unused by ARM) second source register field Rn for MOV and MVN instructions.

{{clear|right}}
{|class="wikitable" style="text-align:center"
|+Unicore32 instruction set overview<ref>[https://github.com/qemu/qemu/blob/HEAD/target/unicore32/translate.c QEMU Unicore32 emulator source code]</ref>
|-
! {{verth|31}} || {{verth|30}} || {{verth|29}} || {{verth|28}} || {{verth|27}} || {{verth|26}} || {{verth|25}} || {{verth|24}} || {{verth|23}} || {{verth|22}} || {{verth|21}} || {{verth|20}} || {{verth|19}} || {{verth|18}} || {{verth|17}} || {{verth|16}} || {{verth|15}} || {{verth|14}} || {{verth|13}} || {{verth|12}} || {{verth|11}} || {{verth|10}} || {{verth|va=top|9}} || {{verth|va=top|8}} || {{verth|va=top|7}} || {{verth|va=top|6}} || {{verth|va=top|5}} || {{verth|va=top|4}} || {{verth|va=top|3}} || {{verth|va=top|2}} || {{verth|va=top|1}} || {{verth|va=top|0}} || Description
|-
| 0 || 0 || 0 ||colspan=4| ''opcode'' || S ||colspan=5| Rn ||colspan=5| Rd ||colspan=5| shift || 0 ||colspan=2| Sh || 0 ||colspan=5| Rm ||align=left| ALU operation, Rd = Rn ''op'' Rm ''shift'' #shift
|-
| 0 || 0 || 0 ||colspan=4| ''opcode'' || S ||colspan=5| Rn ||colspan=5| Rd ||colspan=5| Rs || 0 ||colspan=2| Sh || 1 ||colspan=5| Rm ||align=left| ALU operation, Rd = Rn ''op'' Rm ''shift'' Rs
|-
| 0 || 0 || 1 ||colspan=4| ''opcode'' || S ||colspan=5| Rn ||colspan=5| Rd ||colspan=5| shift ||colspan=9| imm9 ||align=left| ALU operation, Rd = Rn ''op'' #imm9 ROTL #shift
|-
| 0 || 1 || 0 || P || U || B || W || L ||colspan=5| Rn ||colspan=5| Rd ||colspan=5| shift || 0 ||colspan=2| Sh || 0 ||colspan=5| Rm ||align=left| Load/store Rd to address Rn ± Rm ''shift'' #shift
|-
| 0 || 1 || 1 || P || U || B || W || L ||colspan=5| Rn ||colspan=5| Rd ||colspan=14| offset14 ||align=left| Load/store Rd to address Rn ± offset14
|-
| 1 || 0 || 0 || P || U || S || W || L ||colspan=5| Rn ||colspan=10| Bitmap high || 0 || 0 || H ||colspan=6|Bitmap low ||align=left| Load/store multiple registers
|-
| 1 || 0 || 1 ||colspan=4| ''cond'' || L ||colspan=24| offset24 ||align=left| Branch (and link) if condition true
|-
| 1 || 1 || 0 ||colspan=29|  ||align=left| Coprocessor (FPU) instructions
|-
| 1 || 1 || 1 || 1 || 1 || 1 || 1 || 1 ||colspan=24| Trap number ||align=left| Software interrupt
|-
|colspan=33|
|-
| 0 || 0 || 0 || 0 || 0 || 0 || A || S ||colspan=5| Rn ||colspan=5| Rd ||colspan=5| Rs || 1 || 0 || 0 || 1 ||colspan=5| Rm ||align=left| Multiply, Rd = Rm * Rs (+ Rn)
|-
| 0 || 0 || 0 || 1 || 0 || 0 || 0 || L ||colspan=5| 11111 ||colspan=5| 11111 ||colspan=5| 00000 || 1 || 0 || 0 || 1 ||colspan=5| Rm ||align=left| Branch and exchange (BX, BLX)
|-
| 0 || 1 || 0 || P || U || 0 || W || L ||colspan=5| Rn ||colspan=5| Rd ||colspan=5| 00000 || 1 || S || H || 1 ||colspan=5| Rm ||align=left| Load/store Rd to address Rn ± Rm (16-bit)
|-
| 0 || 1 || 0 || P || U || 1 || W || L ||colspan=5| Rn ||colspan=5| Rd ||colspan=5| imm_hi || 1 || S || H || 1 ||colspan=5| imm_lo ||align=left| Load/store Rd to address Rn ± #imm10 (16-bit)
|}

The meaning of various flag bits (such as S=1 enables setting the condition codes) is identical to the ARM instruction set.  The load/store multiple instruction can only access half of the register set, depending on the H bit.  If H=0, the 16 bits indicate R0–R15; if H=1, R16–R31.

==References==
<references/>

{{Clear}}
{{RISC-based processor architectures}}
{{CPU technologies}}

[[Category:Instruction processing]]
[[Category:Instruction set architectures]]
[[Category:Science and technology in China]]

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