View source for Transistor count

{{Short description|Number of transistors in a device}}
{{Use mdy dates|date=January 2015}}
{{Semiconductor manufacturing processes}}

The '''transistor count''' is the number of [[Transistor|transistors]] in an electronic device (typically on a single substrate or silicon [[Die (integrated circuit)|die]]). It is the most common measure of [[integrated circuit]] complexity (although the majority of transistors in modern [[Microprocessor|microprocessors]] are contained in [[CPU cache|cache memories]], which consist mostly of the same [[Memory cell (computing)|memory cell]] circuits replicated many times). The rate at which [[MOSFET|MOS]] transistor counts have increased generally follows [[Moore's law]], which observes that transistor count doubles approximately every two years. However, being directly proportional to the area of a die, transistor count does not represent how advanced the corresponding manufacturing technology is. A better indication of this is transistor density which is the ratio of a semiconductor's transistor count to its die area.

==Records==
{{As of|2023}}, the highest transistor count in flash memory is [[Micron Technology|Micron]]'s 2{{nbsp}}[[terabyte]] ([[3D integrated circuit|3D-stacked]]) 16-die, 232-layer [[V-NAND]] flash [[memory chip]], with 5.3{{nbsp}}trillion [[floating-gate MOSFET]]s ([[Multi-level cell|3{{nbsp}}bits per transistor]]).

The highest transistor count in a single chip processor {{as of|2020|lc=y}} is that of the [[deep learning]] processor [[Cerebras#Technology|Wafer Scale Engine 2]] by [[Cerebras]]. It has 2.6{{nbsp}}trillion MOSFETs in 84 exposed fields (dies) on a wafer, manufactured using [[TSMC]]'s [[7 nm]] FinFET process.<ref name="ExtremeTech-WSE"/><ref name="NextPlatform-WSE"/><ref name="AnandTech-WSE"/><ref name="WikichipFuse-WSE"/><ref name=":1">{{Cite web |last=Everett |first=Joseph |date=August 26, 2020 |title=World's largest CPU has 850,000 7 nm cores that are optimized for AI and 2.6 trillion transistors |url=https://www.techreportarticles.com/news/artificial-intelligence/worlds-largest-cpu-chip-has-850000-7nm-cores-optimized-for-ai-most-powerful-processor/ |website=TechReportArticles}}</ref>

{{As of|2024}}, the [[Graphics processing unit|GPU]] with the highest transistor count is [[Nvidia]]'s [[Blackwell (microarchitecture)|Blackwell]]-based B100 accelerator, built on [[TSMC]]'s custom 4NP process node and totaling 208 billion MOSFETs.

The highest transistor count in a consumer microprocessor {{as of|2025|March|lc=y}} is 184{{nbsp}}billion transistors, in [[Apple Inc.|Apple]]'s [[ARM architecture family|ARM]]-based dual-die [[Apple M3|M3 Ultra]] SoC, which is fabricated using [[TSMC]]'s [[3 nm process|3 nm]] [[semiconductor manufacturing process]].<ref name=m3ultra />

{| class ="wikitable" style="text-align:center" 
|-
! Year 
! Component 
! Name 
! Number of MOSFETs <br/>(in trillions) 
! Remarks
|-
| 2022 
| Flash memory 
| Micron's [[V-NAND]] module
| 5.3 
| style="text-align:left;" | [[Three-dimensional integrated circuit|stacked package]] of sixteen 232-layer [[Flash memory#Vertical NAND|3D NAND]] dies
|-
| 2020 
| any processor 
| [[Cerebras#Technology|Wafer Scale Engine 2]]
| 2.6
| style="text-align:left;" | [[Wafer-scale integration|wafer-scale]] design of 84 exposed fields (dies)
|-
| 2024
| [[graphics processing unit|GPU]]
| Nvidia B100
| 0.208
| style="text-align:left;" | Uses two reticle limit dies, with 104 billion transistors each, joined together and acting as a single large monolithic piece of silicon
|-
| 2025 
| Microprocessor <br /> (consumer)
| [[Apple M3|Apple M3 Ultra]]
| 0.184
| style="text-align:left;" | SoC using two dies joined together with a high-speed bridge
|-
| 2020
| [[Deep learning processor|DLP]]
| [[Graphcore#Products|Colossus Mk2 GC200]]
| 0.059
| style="text-align:left;" | An IPU{{clarify|date=November 2024}} in contrast to [[Central processing unit|CPU]] and [[graphics processing unit|GPU]]
|-
|}

In terms of computer systems that consist of numerous integrated circuits, the [[supercomputer]] with the highest transistor count {{as of|2016|lc=y}} was the Chinese-designed [[Sunway TaihuLight]], which has for all CPUs/nodes combined "about 400 trillion transistors in the processing part of the hardware" and "the [[Dynamic random-access memory|DRAM]] includes about 12 [[quadrillion]] transistors, and that's about 97 percent of all the transistors."<ref name="Quora-Gustafson">{{Cite web |url=https://www.quora.com/How-many-individual-transistors-are-in-the-worlds-most-powerful-supercomputer/answer/John-Gustafson-1 |title=John Gustafson's answer to How many individual transistors are in the world's most powerful supercomputer? |website=[[Quora]] |access-date=2019-08-22}}</ref> To compare, the [[Microcontroller#Smallest computer|smallest computer]], {{as of|2018|lc=y}} dwarfed by a grain of rice, had on the order of 100,000 transistors. Early experimental solid-state computers had as few as 130 transistors but used large amounts of [[diode logic]]. The first [[carbon nanotube computer]] had 178 transistors and was a [[1-bit computing|1-bit]] [[one-instruction set computer]], while a later one is [[16-bit computing|16-bit]] (its [[instruction set]] is 32-bit [[RISC-V]] though).

Ionic transistor chips ("water-based" [[analog computer|analog]] limited processor), have up to hundreds of such transistors.<ref>{{Cite news |first=Francisco |last=Pires |date=2022-10-05 |title=Water-Based Chips Could be Breakthrough for Neural Networking, AI: Wetware has gained an entirely new meaning |url=https://www.tomshardware.com/news/water-based-chips-could-be-breakthrough-for-neural-networking-ai |access-date=2022-10-05 |website=Tom's Hardware |language=en}}</ref>

Estimates of the total numbers of transistors manufactured:
*Up to 2014: {{Val|2.9E21}}
*Up to 2018: {{Val|1.3E22}}<ref>{{cite web
 |url=https://computerhistory.org/blog/13-sextillion-counting-the-long-winding-road-to-the-most-frequently-manufactured-human-artifact-in-history/
 |first=David
 |last=Laws
 |title=13 Sextillion & Counting: The Long & Winding Road to the Most Frequently Manufactured Human Artifact in History
 |website=Computer History Museum
 |date=2018-04-02
}}</ref><ref>{{cite web
 |first=Jim
 |last=Handy
 |url=https://www.forbes.com/sites/jimhandy/2014/05/26/how-many-transistors-have-ever-shipped/
 |title=How Many Transistors Have Ever Shipped?
 |website=Forbes
 |date=2014-05-26
}}</ref>

== Transistor count ==
[[File:Moore's Law Transistor Count 1970-2020.png|thumb|upright=1.9|Plot of [[MOS transistor]] counts for [[microprocessor]]s against dates of in&shy;tro&shy;duction. The curve shows counts doubling every two years, per [[Moore's law]]. ]]

=== Microprocessors ===
{{See also|Microprocessor chronology|Microcontroller}}

{{More citations needed|1=subsection|date=December 2019|talk=Microprocessors - More citations needed}}

A [[microprocessor]] incorporates the functions of a computer's [[central processing unit]] on a single [[integrated circuit]]. It is a multi-purpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and provides results as output.

The development of [[MOS integrated circuit]] technology in the 1960s led to the development of the first microprocessors.<ref name="computerhistory1971">{{cite web |title=1971: Microprocessor Integrates CPU Function onto a Single Chip |url=https://www.computerhistory.org/siliconengine/microprocessor-integrates-cpu-function-onto-a-single-chip/ |website=The Silicon Engine |publisher=[[Computer History Museum]] |access-date=4 September 2019}}</ref> The 20-bit [[MP944]], developed by [[Garrett AiResearch]] for the [[U.S. Navy]]'s [[F-14 Tomcat]] fighter in 1970, is considered by its designer [[Ray Holt (computer scientist)|Ray Holt]] to be the first microprocessor.<ref name="F-14"/> It was a multi-chip microprocessor, fabricated on six MOS chips. However, it was classified by the Navy until 1998. The [[4-bit computing|4-bit]] [[Intel 4004]], released in 1971, was the first single-chip microprocessor.

Modern microprocessors typically include on-chip [[CPU cache|cache memories]]. The number of transistors used for these cache memories typically far exceeds the number of transistors used to implement the logic of the microprocessor (that is, excluding the cache). For example, the last [[DEC Alpha]] chip uses 90% of its transistors for cache.<ref name="DEC Alpha"/>

{| class="wikitable sortable" style="text-align:left;"
! width=300px|[[Microprocessor|Processor]]
! width=130px data-sort-type="number" | Transistor count
! Year
! Designer
! data-sort-type="number" | [[Semiconductor device fabrication|Process]]<br />([[Nanometre|nm]])
! data-sort-type="number" | Area ([[Millimetre|mm]]<sup>2</sup>)
! data-sort-type="number" | Transistor<br>density<br>(tr./mm<sup>2</sup>)
|-
|[[MP944]] (20-bit, 6-chip, 28 chips total)
|74,442 (5,360 excl. ROM & RAM)<ref>{{Cite book|last=Holt|first=Ray M.|title=The F14A Central Air Data Computer and the LSI Technology State-of-the-Art in 1968|year=1998|pages=8}}</ref><ref>{{Cite web|last=Holt|first=Ray M.|date=2013|title=F14 TomCat MOS-LSI Chip Set|url=https://firstmicroprocessor.com/wp-content/uploads/2020/02/2013powerpoint.ppt|url-status=live|archive-url=https://web.archive.org/web/20201106091538/https://firstmicroprocessor.com/wp-content/uploads/2020/02/2013powerpoint.ppt|archive-date=6 November 2020|access-date=6 November 2020|website=First Microprocessor}}</ref>
|1970<ref name="F-14">{{cite web|last1=Holt|first1=Ray|title=World's First Microprocessor|url=https://www.firstmicroprocessor.com/|quote=1st fully integrated chip set microprocessor|access-date=5 March 2016}}</ref>{{efn|[[Declassification|Declassified]] 1998}}
|[[Garrett AiResearch]]
|{{?}}
|{{?}}
|{{?}}
|-
|[[Intel 4004]] (4-bit, 16-pin)<!--  46 instructions (of which 41 were 8 bits wide and 5 were 16 bits wide). Intel 4040 from 1974 had 60 instructions, added 14.-->
|2,250 <!-- according to [[microprocessor chronology]] page. 2,300 according to the [[Intel 4004]] page until I updated it. -->
|1971
|[[Intel]]
|[[10 μm process|10,000&nbsp;nm]]
|12&nbsp;mm<sup>2</sup>
|188
<!--
|-
|PPS-25 (4-bit, 2-chip)
|
|1971<ref>{{harvnb|Ogdin|1975|pp=57–59, 77}}</ref>{{efn|According to {{harvnb|Ogdin|1975}}, the Fairchild PPS-25 was first delivered in 2Q 1971 and the Intel 4004 in 4Q 1971.}}
|[[Fairchild Semiconductor|Fairchild]]
|Likely 10,000 nm
|
-->
|-
|[[Microprocessor#Texas Instruments TMX 1795 (1970-1971)|TMX 1795]] (8-bit, 24-pin)
|3,078<ref name="tmx_shirriff">Ken Shirriff. [https://www.righto.com/2015/05/the-texas-instruments-tmx-1795-first.html "The Texas Instruments TMX 1795: the (almost) first, forgotten microprocessor"]. 2015.</ref>
|1971
|[[Texas Instruments]]
|{{?}}
| 30.64&nbsp;mm<sup>2</sup> <!-- calculated from "212-by-224 mil chip" -->
|100.5
|-
|[[Intel 8008]] (8-bit, 18-pin)
|3,500
|1972
|Intel
|10,000&nbsp;nm
|14&nbsp;mm<sup>2</sup>
|250
<!--Intel D3002 from 1974; 3002 – 2-bit Arithmetic Logic Unit slice 3001 – Microcontrol Unit -->
|-
|[[μCOM-4|NEC μCOM-4]] (4-bit, 42-pin) <!-- 55 (or 58? or 72?) instructions, "DIP28, DIP42", seems DIP42 first. "The μCOM-43 ISA supported the entire μCOM-4 ISA which included 80 instructions." (others subsets) -->
|2,500<ref>{{cite journal |author1=Ryoichi Mori |author2=Hiroaki Tajima |author3=Morihiko Tajima |author4=Yoshikuni Okada |title=Microprocessors in Japan |journal=Euromicro Newsletter |volume=3 |issue=4 |pages=50–7 |date=October 1977 |doi=10.1016/0303-1268(77)90111-0}}</ref><ref name="ucom-4">{{cite web|title=NEC 751 (uCOM-4) |publisher=The Antique Chip Collector's Page |url=http://www.antiquetech.com/chips/NEC751.htm |access-date=2010-06-11 |url-status=dead |archive-url=https://web.archive.org/web/20110525202756/http://www.antiquetech.com/chips/NEC751.htm |archive-date=2011-05-25 }}</ref>
|1973
|[[NEC]]
|7,500&nbsp;nm<ref name="shmj70s">{{cite web |title=1970s: Development and evolution of microprocessors |url=http://www.shmj.or.jp/english/pdf/ic/exhibi748E.pdf |website=Semiconductor History Museum of Japan |access-date=27 June 2019 |url-status=dead |archive-url=https://web.archive.org/web/20190627161417/http://www.shmj.or.jp/english/pdf/ic/exhibi748E.pdf |archive-date=27 June 2019}}</ref>
|{{?}}
|{{?}}
|-
|[[Toshiba TLCS-12]] (12-bit) <!--"the world's first 12-bit microprocessor"-->
|11,000+<!--"about 2,800 logical gates"--><ref name="shmj-1973-toshiba">{{cite web |title=1973: 12-bit engine-control microprocessor (Toshiba) |url=http://www.shmj.or.jp/english/pdf/ic/exhibi739E.pdf |website=Semiconductor History Museum of Japan |access-date=27 June 2019 |url-status=dead |archive-url=https://web.archive.org/web/20190627203018/http://www.shmj.or.jp/english/pdf/ic/exhibi739E.pdf |archive-date=27 June 2019}}</ref>
|1973
|[[Toshiba]]
|[[6 μm process|6,000&nbsp;nm]]
|32.45&nbsp;mm<sup>2</sup>
|340+
|-
|[[Intel 4040]] (4-bit, 16-pin)<!-- 60 instructions, added 14 to Intel 4004 instruction set. Marginally 14 instructions cost roughly 3000-2250 = 750 transistors, or 64 per instruction.-->
|3,000
|1974
|Intel
|10,000&nbsp;nm
|12&nbsp;mm<sup>2</sup>
|250
|-
|[[Motorola 6800]] (8-bit, 40-pin)
|4,100
|1974
|[[Motorola]]
|6,000&nbsp;nm
|16&nbsp;mm<sup>2</sup>
|256
|-
|[[Intel 8080]] (8-bit, 40-pin)
|6,000 <!--according to its article and another, previously here 4,500-->
|1974
|Intel
|6,000&nbsp;nm
|20&nbsp;mm<sup>2</sup>
|300
|-
|[[Texas Instruments TMS1000|TMS 1000]] (4-bit, 28-pin)
|8,000{{efn|The TMS1000 is a microcontroller, the transistor count includes memory and [[input/output]] controllers, not just the CPU.}}
|1974<ref>{{Cite web|url=http://www.ti.com/corp/docs/company/history/lowbandwidthtimelinesemiconductor.shtml?keyMatch=TMS-1000&tisearch=Search-EN-Everything |title=Low Bandwidth Timeline{{Snd}} Semiconductor |website=[[Texas Instruments]] |access-date=2016-06-22}}</ref>
|Texas Instruments
|8,000&nbsp;nm
|11&nbsp;mm<sup>2</sup>
|730
|-
|[[MOS Technology 6502]] (8-bit, 40-pin)
|4,528{{efn|3,510 without depletion mode pull-up transistors}}<ref>{{Cite web|url=https://research.swtch.com/6502|title=<!-- research!rsc: --> The MOS 6502 and the Best Layout Guy in the World|website=research.swtch.com|date=January 3, 2011|access-date=2019-09-03}}</ref> <!-- later replica is smaller "3218 transistors and 1019 resistors" https://monster6502.com/ -->
|1975
|[[MOS Technology]]
|8,000&nbsp;nm
|21&nbsp;mm<sup>2</sup>
|216
|-
|[[Intersil 6100|Intersil IM6100]] (12-bit, 40-pin; <small>clone of [[PDP-8]]</small><!--PDP8/e instruction set compatible, i.e. 6 memory affecting instructions, and rest of 3-bit opcode used for many OPERATE instructions -->) <!-- https://www.hb9aik.ch/computer/6100_datasheet.pdf https://www.hb9aik.ch/computer/6120_datasheet.pdf -->
|4,000 <!-- Clone of: "The 1965 12-bit [[PDP-8]] CPU had 1409 transistors and over 10,000 diodes." See above. -->
|1975 <!--and the Harris version in 1976-->
|[[Intersil]] <!--bought by Harris-->
|{{?}}
|{{?}}<!-- 51.816*13.208=684&nbsp;mm<sup>2</sup> for outer dimension of chip, not die, need to find it; assuming square die size is ([much] smaller than) 174.4&nbsp;mm<sup>2</sup> -->
|{{?}}
|-
|<!--RCA--> [[CDP 1801]] (8-bit, 2-chip, 40-pin)
|5,000
|1975
|[[RCA]]
|{{?}}
|{{?}}
<!-- 1975 BPC Hewlett Packard 10 MHz 16 - 1 6,000 (+ ROM) NMOS [22][23] 1977 8085 Intel 3.0 MHz 8 3 μm 1 6,500 -->
|{{?}}
|-
|[[RCA 1802]] (8-bit, 40-pin) <!-- seemingly dozens of instructions (has 8-bit opcode) -->
|5,000
|1976
|RCA
|5,000&nbsp;nm
|27&nbsp;mm<sup>2</sup>
|185
<!-- i8048 [[Intel MCS-48]] (8-bit) 1976 including "1K × 8 ROM" -->
|-
|[[Zilog Z80]] (8-bit, 4-bit [[arithmetic logic unit|ALU]], 40-pin) <!-- 252 instructions -->
|8,500{{efn|6,813 without depletion mode pull-up transistors}}
|1976
|[[Zilog]]
|4,000&nbsp;nm
|18&nbsp;mm<sup>2</sup>
|470
|-
|[[Intel 8085]] (8-bit, 40-pin)
|6,500
|1976
|Intel
|[[3 μm process|3,000&nbsp;nm]]
|20&nbsp;mm<sup>2</sup>
|325
|-
|[[TMS9900]] (16-bit) <!-- 69 instructions; single-chip version of [[TI-990]] -->
|8,000
|1976
|Texas Instruments
|{{?}}
|{{?}}
|{{?}}
|-
|Bellmac-8 (8-bit<!--, 40-pin?-->)
|7,000
|1977
|[[Bell Labs]]
|5,000&nbsp;nm
|{{?}}
|{{?}}
|-
|[[Motorola 6809]] (8-bit <small>with some 16-bit features</small>, 40-pin)
|9,000
|1978
|Motorola
|5,000&nbsp;nm
|21&nbsp;mm<sup>2</sup>
|430
|-
|[[Intel 8086]] (16-bit, 40-pin)
|29,000<ref>{{cite web |first=Ken |last=Shirriff |title=Counting the transistors in the 8086 processor: it's harder than you might think |date=January 2023 |url=https://www.righto.com/2023/01/counting-transistors-in-8086-processor.html}}</ref>
|1978
|Intel
|3,000&nbsp;nm
|33&nbsp;mm<sup>2</sup>
|880
|-
|[[Zilog Z8000]] (16-bit)
|17,500<ref>{{cite web |title=Digital History: ZILOG Z8000 (APRIL 1979) |url=http://www.old-computers.com/history/detail.asp?n=52 |website=OLD-COMPUTERS.COM : The Museum |access-date=19 June 2019}}</ref>
|1979
|Zilog
|5,000-6,000&nbsp;nm (design rules)
|39.31&nbsp;mm<sup>2</sup> (238x256 mil<sup>2</sup>)
|445
|-
|[[Intel 8088]] (16-bit, 8-bit data bus)
|29,000
|1979
|Intel
|3,000&nbsp;nm
|33&nbsp;mm<sup>2</sup>
|880
|-
|[[Motorola 68000]] (16/32-bit, <small>32-bit registers, 16-bit <!-- data--> [[arithmetic logic unit|ALU]]</small>)
|68,000<ref>{{cite web |title=Chip Hall of Fame: Motorola MC68000 Microprocessor |url=https://spectrum.ieee.org/chip-hall-of-fame-motorola-mc68000-microprocessor |website=[[IEEE Spectrum]] |publisher=[[Institute of Electrical and Electronics Engineers]] |access-date=19 June 2019 |date=30 June 2017}}</ref>
|1979
|Motorola
|3,500&nbsp;nm
|44&nbsp;mm<sup>2</sup>
|1,550
|-
|[[Intel MCS-51|Intel 8051]] (8-bit, 40-pin) <!-- spell as i8051? From comment (later corrected): "The original 8051 had about 50,000 transistors" https://community.arm.com/developer/tools-software/tools/f/keil-forum/38268/new-microcontroller-selection-after-8051-please-do-not-ignore -->
|50,000
|1980
|Intel
|{{?}}
|{{?}}
|{{?}}
|-
|[[WDC 65C02]]
|11,500<ref name="Christiansen">[http://icarus.cs.weber.edu/home/dferro/ada/Christiansen_Report_Finished/Finishedmicroprocessors.doc ''Microprocessors: 1971 to 1976''] {{Webarchive|url=https://web.archive.org/web/20131203015458/http://icarus.cs.weber.edu/home/dferro/ada/Christiansen_Report_Finished/Finishedmicroprocessors.doc |date=December 3, 2013 }} Christiansen</ref>
|1981
|[[Western Design Center|WDC]]
|3,000&nbsp;nm
|6&nbsp;mm<sup>2</sup>
|1,920
|-
<!-- [[IBM 801]] operational in summer 1980, missing here (24-bit registers?), their first RISC, was basis for IBM ROMP and lessons learned from it to make IBM POWER-->
|[[IBM ROMP|ROMP]] (32-bit) <!-- 118 instructions, unusual for RISC, variable length, either 2 or 4 bytes -->
|45,000
|1981
|[[IBM]]
|2,000&nbsp;nm
|58.52&nbsp;mm<sup>2</sup>
|770
|-
|[[Intel 80186]] (16-bit, 68-pin)
|55,000 <!-- 80188 has as many, is the same just with 8-bit data bus and as many transistors and pins so probably same die -->
|1982
|Intel
|3,000&nbsp;nm
|60&nbsp;mm<sup>2</sup>
|920
|-
|[[Intel 80286]] (16-bit, 68-pin)
|134,000
|1982
|Intel
|[[1.5 μm process|1,500&nbsp;nm]]
|49&nbsp;mm<sup>2</sup>
|2,730
|-
|[[WDC 65C816]] (8/16-bit)
|22,000<ref>{{cite web |url=http://icarus.cs.weber.edu/home/dferro/ada/Christiansen_Report_Finished/Finishedmicroprocessors.doc |title=Microprocessors 1976 to 1981 |publisher=weber.edu |access-date=2014-08-09 |archive-date=December 3, 2013 |archive-url=https://web.archive.org/web/20131203015458/http://icarus.cs.weber.edu/home/dferro/ada/Christiansen_Report_Finished/Finishedmicroprocessors.doc |url-status=dead }}</ref>
|1983
|WDC
|3,000&nbsp;nm<ref>{{Cite web|url=http://www.westerndesigncenter.com/wdc/w65c816s-core.cfm|title=W65C816S 16-bit Core|website=www.westerndesigncenter.com|access-date=2017-09-12}}</ref>
|9&nbsp;mm<sup>2</sup>
|2,400
|-
|[[NEC V20]]
|63,000
|1984
|NEC
|{{?}}
|{{?}}
|{{?}}
|-
|[[Motorola 68020]] (32-bit; 114 pins used) <!-- [[Pin grid array|PGA 169]] (114 pins used); very small [[instruction cache|I-cache]] -->
|190,000<ref name="DeMone">{{cite web|first=Paul |last=Demone |url=http://www.realworldtech.com/arms-race/ |title=ARM's Race to World Domination | publisher=real world technologies|date = 2000-11-09 | access-date=2015-07-20}}</ref>
|1984
|Motorola
|2,000&nbsp;nm
|85&nbsp;mm<sup>2</sup>
|2,200
|-
|[[Intel 80386]] (32-bit, 132-pin; no cache) <!--88-pin PGA for SX-variant, 100-pin also (only?) available for it, not non-SX-->
|275,000
|1985
|Intel
|1,500&nbsp;nm
|104&nbsp;mm<sup>2</sup>
|2,640
|-
|[[ARM architecture family|ARM 1]] (32-bit; no cache)
|25,000<ref name="DeMone"/>
|1985
|[[Acorn Computers|Acorn]]
|3,000&nbsp;nm
|50&nbsp;mm<sup>2</sup>
|500
|-
|Novix NC4016 (16-bit) <!-- all instructions 2 bytes: only 8 (10?) classes of instructions; 40+ instructions? -->
|16,000<ref>{{cite web|url=http://soton.mpeforth.com/flag/jfar/vol6/no1/article1.pdf |title=The Harris RTX 2000 Microcontroller |first=Tom |last=Hand |work= mpeforth.com |access-date=2014-08-09}}</ref>
|1985<ref>{{cite web|url=http://www.ultratechnology.com/chips.htm |title=Forth chips list |publisher=UltraTechnology |date=2001-03-15 |access-date=2014-08-09}}</ref> <!-- users.ece.cmu.edu/~koopman/stack_computers/sec4_4.html "The Novix NC4016, formerly called the NC4000, is a 16-bit stack based microprocessor designed to execute primitives of the Forth programming language. [..] The NC4016 is implemented using fewer than 4000 gates on a 3.0 micron HCMOS gate array technology, packaged in a 121-pin Pin Grid Array (PGA). The NC4016 runs at up to 8&nbsp;MHz." -->
|[[Harris Corporation]]
|3,000&nbsp;nm<ref>{{cite book |first=Philip J. |last=Koopman |chapter-url=https://www.ece.cmu.edu/~koopman/stack_computers/sec4_4.html |title=Stack Computers: the new wave |chapter=4.4 Architecture of the Novix NC4016 |publisher=Carnegie Mellon University |date=1989 |access-date=2014-08-09 |isbn=978-0745804187 |series=Ellis Horwood Series in Computers and Their Applications}}</ref>
|{{?}}
|{{?}}
|-
|[[MB86900|SPARC MB86900]] (32-bit; no cache)
|110,000<ref>{{cite web |title=Fujitsu SPARC |url=http://www.cpu-collection.de/?tn=0&l0=cl&l1=SPARC&l2=Fujitsu |website=cpu-collection.de |access-date=30 June 2019}}</ref>
|1986
|[[Fujitsu]]
|1,200&nbsp;nm
|{{?}}
|{{?}}
|-
|[[NEC V60]]<ref name=NEC>{{cite journal |vauthors=Kimura S, Komoto Y, Yano Y |title=Implementation of the V60/V70 and its FRM function |journal=IEEE Micro |volume=8 |issue=2 |pages=22–36 |year=1988 |doi=10.1109/40.527 |s2cid=9507994 }}</ref> (32-bit; no cache)
|375,000
|1986
|NEC
|1,500&nbsp;nm
|{{?}}
|{{?}}
|-
|[[ARM architecture family|ARM 2]] (32-bit, 84-pin; no cache) <!-- 24-bit addressing, later full 32-bit or 64-bit version; and later chips, 8-Pin SOIC for US$0.1375 in volume (up to 28-Pin SSOP) -->
|27,000<ref>{{Cite web|url=https://en.wikichip.org/wiki/vti/vl86cx/vl2333|title=VL2333 - VTI - WikiChip|website=en.wikichip.org|access-date=2019-08-31}}</ref><ref name="DeMone"/>
|1986
|Acorn
|2,000&nbsp;nm
|30.25&nbsp;mm<sup>2</sup> <!-- for this, i.e. ARM2, not ARM1, prototype, but in production slightly bigger 34.13 -->
|890
|-
|[[Z80000]] (32-bit; very small cache)
|91,000
|1986
|Zilog
|{{?}}
|{{?}}
|{{?}}
|-
|[[NEC V70]]<ref name=NEC/> (32-bit; no cache)
|385,000
|1987
|NEC
|1,500&nbsp;nm
|{{?}}
|{{?}}
|-
|[[TRON Project|Hitachi Gmicro/200]]<ref>{{cite journal |vauthors=Inayoshi H, Kawasaki I, Nishimukai T, Sakamura K |title=Realization of Gmicro/200 |journal=IEEE Micro |volume=8 |issue=2 |pages=12–21 |year=1988 |doi=10.1109/40.526 |s2cid=36938046 }}</ref>
|730,000
|1987
|[[Hitachi]]
|[[1 μm process|1,000&nbsp;nm]]
|{{?}}
|{{?}}
|-
|[[Motorola 68030]] (32-bit, very small caches)
|273,000
|1987
|Motorola
|[[800 nm process|800&nbsp;nm]]
|102&nbsp;mm<sup>2</sup>
|2,680
|-
|[[TI Explorer]]'s 32-bit <small>[[Lisp (programming language)|Lisp]] [[Lisp machine|machine]] chip</small>
|553,000<ref name="MegaChip">{{cite journal |author1=Bosshart, P. |author2=Hewes, C. |author3=Mi-Chang Chang |author4=Kwok-Kit Chau |author5=Hoac, C. |author6=Houston, T. |author7=Kalyan, V. |author8=Lusky, S. |author9=Mahant-Shetti, S. |author10=Matzke, D. |author11=Ruparel, K. |author12=Ching-Hao Shaw |author13=Sridhar, T. |author14=Stark, D. |title=A 553K-Transistor LISP Processor Chip |journal=IEEE Journal of Solid-State Circuits |volume=22 |issue=5 |pages=202–3 |date=October 1987 |doi=10.1109/ISSCC.1987.1157084 |s2cid=195841103 }}</ref>
|1987
|Texas Instruments
|2,000&nbsp;nm<ref>{{cite book |first=Lennart E. |last=Fahlén |author2=Stockholm International Peace Research Institute |title=Arms and Artificial Intelligence: Weapon and Arms Control Applications of Advanced Computing |chapter=3. Hardware requirements for artificial intelligence § Lisp Machines: TI Explorer |chapter-url=https://books.google.com/books?id=88Mcg5MMPdYC&pg=PA57 |year=1987 |publisher=Oxford University Press |isbn=978-0-19-829122-0 |page=57 |series=SIPRI Monograph Series}}</ref>
|{{?}}
|{{?}}
|-
|DEC WRL MultiTitan
|180,000<ref>
{{cite journal|author-link1=Norman Jouppi |first1=Norman P. |last1=Jouppi |first2=Jeffrey Y. F. |last2=Tang |title=A 20-MIPS Sustained 32-bit CMOS Microprocessor with High Ratio of Sustained to Peak Performance |journal=IEEE Journal of Solid-State Circuits |volume=24 |issue=5 |date=July 1989 |id=WRL Research Report 89/11 |page=i |citeseerx=10.1.1.85.988 |bibcode=1989IJSSC..24.1348J |doi=10.1109/JSSC.1989.572612 }}</ref>
|1988
|[[Digital Equipment Corporation|DEC WRL]]
|1,500&nbsp;nm
|61&nbsp;mm<sup>2</sup>
|2,950
|-
|[[Intel i960]] (32-bit, <small>33-bit memory subsystem</small>, no cache)<!-- 33-bit technically: "The memory subsystem was 33-bits wide—to accommodate a 32-bit word and a "tag" bit to implement memory protection in hardware".-->
|250,000<ref>{{cite web|url=http://www.cpushack.com/chippics/Intel/80960/IntelA80960CA-25-2.html |title=The CPU shack museum |publisher=CPUshack.com |date=2005-05-15 |access-date=2014-08-09}}</ref>
|1988
|Intel
|1,500&nbsp;nm<ref name="i960">{{cite web |title=Intel i960 Embedded Microprocessor |url=http://micro.magnet.fsu.edu/optics/olympusmicd/galleries/chips/intel960b.html |archive-url=https://web.archive.org/web/20030303223737/http://micro.magnet.fsu.edu/optics/olympusmicd/galleries/chips/intel960b.html |url-status=dead |archive-date=3 March 2003 |website=[[National High Magnetic Field Laboratory]] |publisher=[[Florida State University]] |access-date=29 June 2019 |date=3 March 2003}}</ref>
|{{?}}
|{{?}}
|-
|[[Intel i960|Intel i960CA]] (32-bit, cache)
|600,000<ref name="i960"/>
|1989
|Intel
|800&nbsp;nm
|143&nbsp;mm<sup>2</sup>
|4,200
|-
|[[Intel i860]] (32/64-bit, 128-bit [[Single instruction, multiple data|SIMD]], cache, [[very long instruction word|VLIW]])
|1,000,000<ref>{{cite book |last1=Venkatasawmy |first1=Rama |title=The Digitization of Cinematic Visual Effects: Hollywood's Coming of Age |date=2013 |publisher=[[Rowman & Littlefield]] |isbn=9780739176214 |page=198 |url=https://books.google.com/books?id=tg2ix9VD_-sC&pg=PA198}}</ref>
|1989
|Intel
|{{?}}
|{{?}}
||{{?}}
|-
|[[Intel 80486]] (32-bit, 8&nbsp;KB cache)
|1,180,235
|1989
|Intel
|1,000&nbsp;nm
|173&nbsp;mm<sup>2</sup>
|6,822
|-
|[[ARM architecture family|ARM 3]] (32-bit, 4&nbsp;KB cache)
|310,000
|1989
|Acorn
|1,500&nbsp;nm
|87&nbsp;mm<sup>2</sup>
|3,600
|-
|[[POWER1]] (9-chip module, 72 kB of cache)
|6,900,000<ref>Bakoglu, Grohoski, and Montoye. ''"The IBM RISC System/6000 processor: Hardware overview."'' IBM J. Research and Development. Vol. 34 No. 1, January 1990, pp. 12-22.</ref>
|1990
|IBM
|1,000&nbsp;nm
|1,283.61&nbsp;mm<sup>2</sup>
|5,375
|-
|[[Motorola 68040]] (32-bit, 8&nbsp;KB caches)
|1,200,000
|1990
|Motorola
|650&nbsp;nm
|152&nbsp;mm<sup>2</sup>
|7,900
|-
|[[R4000]] (64-bit, 16&nbsp;KB of caches)
|1,350,000
|1991
|[[MIPS Technologies|MIPS]]
|1,000&nbsp;nm
|213&nbsp;mm<sup>2</sup>
|6,340
|-
|[[ARM architecture family|ARM 6]] (32-bit, no cache for this 60 variant)
|35,000
|1991
|[[ARM Holdings|ARM]]
|800&nbsp;nm
|{{?}}
|{{?}}
|-
|[[SuperH|Hitachi SH-1]] (32-bit, no cache)
|600,000<ref>{{cite web |title=SH Microprocessor Leading the Nomadic Era |url=http://www.shmj.or.jp/makimoto/en/pdf/makimoto_E_02_10.pdf |archive-url=https://web.archive.org/web/20190627070645/http://www.shmj.or.jp/makimoto/en/pdf/makimoto_E_02_10.pdf |url-status=dead |archive-date=June 27, 2019 |website=Semiconductor History Museum of Japan |access-date=27 June 2019 }}</ref>
|1992<ref>{{cite web |title=SH2: A Low Power RISC Micro for Consumer Applications |url=http://www.hotchips.org/wp-content/uploads/hc_archives/hc06/2_Mon/HC6.S4/HC6.4.2.pdf |publisher=[[Hitachi]] |access-date=27 June 2019 |archive-date=May 10, 2019 |archive-url=https://web.archive.org/web/20190510040218/http://www.hotchips.org/wp-content/uploads/hc_archives/hc06/2_Mon/HC6.S4/HC6.4.2.pdf |url-status=dead }}</ref>
|Hitachi
|800&nbsp;nm
|100&nbsp;mm<sup>2</sup>
|6,000
|-
|[[Intel i960|Intel i960CF]] (32-bit, cache)
|900,000<ref name="i960"/>
|1992
|Intel
|{{?}}
|125&nbsp;mm<sup>2</sup>
|7,200
|-
|[[Alpha 21064]] (64-bit, 290-pin; 16&nbsp;KB of caches) <!-- 6-bit instructions, 6 groups. "An optional external secondary cache, known as the B-cache, with capacities of 128 KB to 16 MB was supported"-->
|1,680,000
|1992
|[[Digital Equipment Corporation|DEC]]
|750&nbsp;nm
|233.52&nbsp;mm<sup>2</sup>
|7,190
|-
|[[Hitachi]] HARP-1 (32-bit, cache) <!-- based on [[PA-RISC]] -->
|2,800,000<ref>{{cite web |title=HARP-1: A 120&nbsp;MHz Superscalar PA-RISC Processor |url=https://www.hotchips.org/wp-content/uploads/hc_archives/hc05/3_Tue/HC05.S8/HC05.8.1-Matsubara-Hitachi-HARP-1.pdf |publisher=[[Hitachi]] |access-date=19 June 2019 |archive-date=April 23, 2016 |archive-url=https://web.archive.org/web/20160423084425/http://www.hotchips.org/wp-content/uploads/hc_archives/hc05/3_Tue/HC05.S8/HC05.8.1-Matsubara-Hitachi-HARP-1.pdf |url-status=dead }}</ref>
|1993
|Hitachi
|500&nbsp;nm
|267&nbsp;mm<sup>2</sup>
|10,500
|-
|[[Intel P5|Pentium]] (32-bit, 16&nbsp;KB of caches)
|3,100,000
|1993
|Intel
|800&nbsp;nm
|294&nbsp;mm<sup>2</sup>
|10,500
|-
|[[POWER2]] (8-chip module, 288 kB of cache)
|23,037,000<ref>White and Dhawan. ''"POWER2: next generation of the RISC System/6000 family"'' IBM J. Research and Development. Vol. 38 No. 5, September 1994, pp. 493-502.</ref>
|1993
|IBM
|720&nbsp;nm
|1,217.39&nbsp;mm<sup>2</sup>
|18,923
|-
|[[ARM architecture family|ARM700]] (32-bit; 8&nbsp;KB cache)
|578,977<ref>{{cite web|url=http://www.poppyfields.net/acorn/docs/armdocs/arm7stat.shtml |title=ARM7 Statistics |publisher=Poppyfields.net |date=1994-05-27 |access-date=2014-08-09}}</ref>
|1994
|ARM
|700&nbsp;nm
|68.51&nbsp;mm<sup>2</sup>
|8,451
|-
|MuP21 (21-bit,<ref>{{Cite web|url=http://www.ultratechnology.com/p21.html|title=Forth Multiprocessor Chip MuP21|quote=MuP21 has a 21-bit CPU core, a memory coprocessor, and a video coprocessor|website=www.ultratechnology.com|access-date=2019-09-06}}</ref> 40-pin; includes [[video card|video]]) <!-- "only 24 instructions". unclear if 20- or 21-bit, or : "21-bit CPU core [..] 20-bit words are fetched from the DRAM memory at a rate of 20 MHz. Each word contains four 5-bit instructions"  --> 
|7,000<ref name="F21"/>
|1994
|Offete Enterprises
|1,200&nbsp;nm <!-- 1.2 micron -->
|{{?}}
|{{?}}
|-
|[[Motorola 68060]] (32-bit, 16&nbsp;KB of caches)
|2,500,000
|1994
|Motorola
|[[600 nm process|600&nbsp;nm]]
|218&nbsp;mm<sup>2</sup>
|11,500
|-
|[[PowerPC 600|PowerPC 601]] (32-bit, 32&nbsp;KB of caches)
|2,800,000<ref>{{Cite web|title=Ars Technica: PowerPC on Apple: An Architectural History, Part I - Page 2 - (8/2004)|url=https://archive.arstechnica.com/cpu/004/ppc-1/m-ppc-1-2.html|access-date=2020-08-11|website=archive.arstechnica.com}}</ref>
|1994
|[[AIM alliance|Apple, IBM, Motorola]]
|600&nbsp;nm
|121&nbsp;mm<sup>2</sup>
|23,000
|-
|[[PowerPC 600|PowerPC 603]] (32-bit, 16&nbsp;KB of caches)
|1,600,000<ref>Gary et al. (1994). "The PowerPC 603 microprocessor: a low-power design for portable applications." ''Proceedings of COMPCON 94.'' DOI: 10.1109/CMPCON.1994.282894</ref>
|1994
|[[AIM alliance|Apple, IBM, Motorola]]
|500&nbsp;nm
|84.76&nbsp;mm<sup>2</sup>
|18,900
|-
|[[PowerPC 600|PowerPC 603e]] (32-bit, 32&nbsp;KB of caches)
|2,600,000<ref>Slaton et al. (1995). "The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor." ''Proceedings of ICCD '95 International Conference on Computer Design.'' DOI: 10.1109/ICCD.1995.528810</ref>
|1995
|[[AIM alliance|Apple, IBM, Motorola]]
|500&nbsp;nm
|98&nbsp;mm<sup>2</sup>
|26,500
|-
|[[Alpha 21164]] EV5 (64-bit, 112 kB cache)
|9,300,000<ref>Bowhill, William J. et al. (1995). "Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU". ''Digital Technical Journal'', Volume 7, Number 1, pp. 100&ndash;118.</ref>
|1995
|DEC
|500&nbsp;nm
|298.65&nbsp;mm<sup>2</sup>
|31,140
|-
|[[StrongARM|SA-110]] (32-bit, 32&nbsp;KB of caches)
|2,500,000<ref name="DeMone"/>
|1995
|Acorn, DEC, [[Apple Inc.|Apple]]
|[[350 nm process|350&nbsp;nm]]
|50&nbsp;mm<sup>2</sup>
|50,000
|-
|[[Pentium Pro]] (32-bit, 16&nbsp;KB of caches;<ref>{{Cite web |url=http://hw-museum.cz/cpu/7/intel-pentium-pro-180 |title=Intel Pentium Pro 180 |website=hw-museum.cz |date=February 20, 2015 |access-date=2019-09-08}}</ref> L2 cache on-package, but on separate die) <!--"Likely Pentium Pro's most noticeable addition was its on-package L2 cache, which ranged from 256 KB at introduction to 1 MB in 1997. At the time, manufacturing technology did not feasibly allow a large L2 cache to be integrated into the processor core." -->
|5,500,000<ref>{{cite web|url=http://www.pcguide.com/ref/cpu/fam/g6PPro-c.html |archive-url=https://web.archive.org/web/20010414032941/http://www.pcguide.com/ref/cpu/fam/g6PPro-c.html |url-status=dead |archive-date=2001-04-14 |title=PC Guide Intel Pentium Pro ("P6") |publisher=PCGuide.com |date=2001-04-17 |access-date=2014-08-09}}</ref>
|1995
|Intel
|500&nbsp;nm
|307&nbsp;mm<sup>2</sup>
|18,000
|-
|[[PA-8000]] 64-bit, no cache
|3,800,000<ref>Gaddis, N.; Lotz, J. (November 1996). "A 64-b quad-issue CMOS RISC microprocessor". ''IEEE Journal of Solid-State Circuits'' '''31''' (11): pp. 1697&ndash;1702.</ref>
|1995
|HP
|500&nbsp;nm
|337.69&nbsp;mm<sup>2</sup>
|11,300
|-
|[[Alpha 21164|Alpha 21164A]] EV56 (64-bit, 112 kB cache)
|9,660,000<ref>Bouchard, Gregg. [https://web.archive.org/web/20110723210647/http://www.hotchips.org/archives/hc8/2_Mon/HC8.S1/HC8.1.2.pdf "Design objectives of the 0.35 μm Alpha 21164 Microprocessor"]. IEEE Hot Chips Symposium, August 1996, IEEE Computer Society.</ref>
|1996
|DEC
|350&nbsp;nm
|208.8&nbsp;mm<sup>2</sup>
|46,260
|-
|[[AMD K5]] (32-bit, caches)
|4,300,000
|1996
|[[AMD]]
|500&nbsp;nm
|251&nbsp;mm<sup>2</sup>
|17,000
|-
|[[Pentium II]] Klamath (32-bit, 64-bit [[Single instruction, multiple data|SIMD]], caches)
|7,500,000
|1997
|Intel
|350&nbsp;nm
|195&nbsp;mm<sup>2</sup>
|39,000
|-
|[[AMD K6]] (32-bit, caches)
|8,800,000
|1997
|AMD
|350&nbsp;nm
|162&nbsp;mm<sup>2</sup>
|54,000
|-
|F21 (21-bit<!--assumed: 40-pin-->; includes e.g. [[video card|video]]) <!-- 27 instructions. "based on the MuP21 however F21 has many improvements over MuP21 [..] and more coprocessors on chip so that in addition to MuP21's video output F21 offers video I/O, analog I/O, serial network I/O, and a parallel I/O port on chip. F21 has a transistor count of about 15,000 vs about 7,000 for MuP21. [..]
CPU Instructions are based on Forth: [..] This is a 21-bit Forth engine with 2 push-down stacks: [..] It has a 20-bit memory bus, the 21st bit serving as address or carry." -->
|15,000
|1997<ref name="F21">{{Cite web|url=http://www.ultratechnology.com/f21cpu.html|title=F21 CPU|quote=F21 offers video I/O, analog I/O, serial network I/O, and a parallel I/O port on chip. F21 has a transistor count of about 15,000 vs about 7,000 for MuP21.|website=www.ultratechnology.com|access-date=2019-09-06}}</ref> <!-- see "Updated 6/4/97", assuming made it to production, that year, not just its predecessor -->
|Offete Enterprises
|{{?}}<!-- equal or denser than 1200&nbsp;nm of its predecessor MuP21 -->
|{{?}}<!-- likely smallest chip in table, I calculated likely 4&nbsp;mm<sup>2</sup> -->
|{{?}}
|-
|[[AVR microcontrollers|AVR]] (8-bit, 40-pin; w/memory)
|140,000 (48,000 <!--"12,000 gates"--><br><small>excl. memory</small><ref>{{Cite web|url=https://www.embeddedrelated.com/showthread/comp.arch.embedded/14362-1.php|title=Transistor count of common uCs?|author=<!--for his comment there: -->Ulf Samuelsson|website=www.embeddedrelated.com|quote=IIRC, The AVR core is 12,000 gates, and the megaAVR core is 20,000 gates. Each gate is 4 transistors. The chip is considerably larger since the memory uses quite a lot.<!--
The ATmega128 is probably somewhere between 600k-1M transistors.
For comparison: The AT91R40008 ARM7 micro is probably 2 M transistors. The ultimate CISC microprocessor, the NS32016 was but 60,000 transistors.-->|access-date=2019-09-08}}</ref>)
<!--"The AT90S8515 provides the following features: 8K bytes of In-System ProgrammableFlash, 512 bytes EEPROM, 512 bytes SRAM", e.g. the 512 bytes of SRAM alone would be 24,576 transistors plus 65,536 for the EEPROM = 90,112 additional or at least 138,112 (given 48,000 exact for non-memory).-->
|1997
|[[Nordic Semiconductor|Nordic VLSI]]/[[Atmel]]
|{{?}}
|{{?}}
|{{?}}
|-
|[[Pentium II]] Deschutes (32-bit, large cache)
|7,500,000
|1998
|Intel
|[[250 nm process|250&nbsp;nm]]
|113&nbsp;mm<sup>2</sup>
|66,000
|-
|[[Alpha 21264]] EV6 (64-bit)
|15,200,000<ref>Gronowski, Paul E. et al. (May 1998). "High-performance microprocessor design". ''IEEE Journal of Solid-State Circuits'' '''33''' (5): pp.&nbsp;676&ndash;686.</ref> 
|1998
|DEC
|350&nbsp;nm
|313.96&nbsp;mm<sup>2</sup>
|48,400
|-
|[[Alpha 21164PC]] PCA57 (64-bit, 48 kB cache)
|5,700,000
|1998
|Samsung
|280&nbsp;nm
|100.5&nbsp;mm<sup>2</sup>
|56,700
|-
|[[Hitachi SH-4]] (32-bit, caches)<ref>
{{cite journal
|last1=Nakagawa
|first1=Norio
|last2=Arakawa
|first2=Fumio
|date=April 1999
|title=Entertainment Systems and High-Performance Processor SH-4
|url=https://www.hitachi.com/rev/1999/revapr99/r2_103.pdf
|journal=Hitachi Review
|volume=48
|issue=2
|pages=58–63
|access-date=2023-03-18
}}</ref>
|3,200,000<ref>{{cite book |date=1998 |pages=18.1-1 - 18.1-11 |publisher=[[IEEE]] |doi=10.1109/ISSCC.1998.672469 |chapter-url=https://ieeexplore.ieee.org/document/672469 |access-date=17 March 2023|last1=Nishii |first1=O. |last2=Arakawa |first2=F. |last3=Ishibashi |first3=K. |last4=Nakano |first4=S. |last5=Shimura |first5=T. |last6=Suzuki |first6=K. |last7=Tachibana |first7=M. |last8=Totsuka |first8=Y. |last9=Tsunoda |first9=T. |last10=Uchiyama |first10=K. |last11=Yamada |first11=T. |last12=Hattori |first12=T. |last13=Maejima |first13=H. |last14=Nakagawa |first14=N. |last15=Narita |first15=S. |last16=Seki |first16=M. |last17=Shimazaki |first17=Y. |last18=Satomura |first18=R. |last19=Takasuga |first19=T. |last20=Hasegawa |first20=A. |title=1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No. 98CH36156) |chapter=A 200 MHZ 1.2 W 1.4 GFLOPS microprocessor with graphic operation unit |isbn=0-7803-4344-1 |s2cid=45392734 }}</ref>
|1998
|Hitachi
|250&nbsp;nm 
|57.76&nbsp;mm<sup>2</sup>
|55,400
|-
|[[ARM architecture family|ARM 9TDMI]] (32-bit, no cache)
|111,000<ref name="DeMone"/>
|1999
|Acorn
|350&nbsp;nm
|4.8&nbsp;mm<sup>2</sup>
|23,100
|-
|[[Pentium III]] Katmai (32-bit, 128-bit SIMD, caches)
|9,500,000
|1999
|Intel
|250&nbsp;nm
|128&nbsp;mm<sup>2</sup>
|74,000
|-
|[[Emotion Engine]] (64-bit, 128-bit [[Single instruction, multiple data|SIMD]], cache)
|10,500,000<ref name=Diefendorff /><br>– 13,500,000<ref name="hennessy">{{cite book|last1=Hennessy|first1=John L. |author-link1=John L. Hennessy |last2=Patterson|first2=David A. |author-link2=David Patterson (scientist)|title=Computer Architecture: A Quantitative Approach|page=491|url=https://books.google.com/books?id=XX69oNsazH4C&pg=PA491|access-date=9 April 2013|edition=3|date=29 May 2002|publisher=Morgan Kaufmann|isbn=978-0-08-050252-6}}</ref>
|1999
|[[Sony]], [[Toshiba]]
|250&nbsp;nm
|239.7&nbsp;mm<sup>2</sup><ref name="Diefendorff">{{cite journal |last1=Diefendorff |first1=Keith |title=Sony's Emotionally Charged Chip: Killer Floating-Point "Emotion Engine" To Power PlayStation 2000 |journal=[[Microprocessor Report]] |date=April 19, 1999 |volume=13 |issue=5 |s2cid=29649747 |url=http://pdfs.semanticscholar.org/9248/eea6c98e5a7fc45606d9d562a0e74707ce43.pdf |archive-url=https://web.archive.org/web/20190228125309/http://pdfs.semanticscholar.org/9248/eea6c98e5a7fc45606d9d562a0e74707ce43.pdf |url-status=dead |archive-date=February 28, 2019 |access-date=19 June 2019}}</ref>
|43,800 – 56,300
|-
|[[Pentium II]] Mobile Dixon (32-bit, caches)
|27,400,000
|1999
|Intel
|180&nbsp;nm
|180&nbsp;mm<sup>2</sup>
|152,000
|-
|[[AMD K6-III]] (32-bit, caches)
|21,300,000
|1999
|AMD
|250&nbsp;nm
|118&nbsp;mm<sup>2</sup>
|181,000
|-
|[[AMD K7]] (32-bit, caches)
|22,000,000
|1999
|AMD
|250&nbsp;nm
|184&nbsp;mm<sup>2</sup>
|120,000
|-
|[[Gekko (microprocessor)|Gekko]] (32-bit, large cache)
|21,000,000<ref name="pcper2005">{{cite web |title=NVIDIA GeForce 7800 GTX GPU Review |url=https://pcper.com/2005/06/nvidia-geforce-7800-gtx-gpu-review/ |website=[[PC Perspective]] |access-date=18 June 2019 |date=22 June 2005}}</ref>
|2000
|IBM, [[Nintendo]]
|180&nbsp;nm
|43&nbsp;mm<sup>2</sup>
|490,000 (check)
|-
|[[Pentium III]] Coppermine (32-bit, large cache)
|21,000,000
|2000
|Intel
|180&nbsp;nm
|80&nbsp;mm<sup>2</sup>
|263,000
|-
|[[Pentium 4]] Willamette (32-bit, large cache)
|42,000,000
|2000
|Intel
|180&nbsp;nm
|217&nbsp;mm<sup>2</sup>
|194,000
|-
|[[SPARC64 V]] (64-bit, large cache)
|191,000,000<ref>{{cite conference| last1 = Ando| first1 = H.| last2  = Yoshida| first2 = Y.| last3 = Inoue| first3 = A.| last4 = Sugiyama| first4 = I.| last5  = Asakawa| first5 = T.| last6  = Morita| first6 = K.| last7  = Muta| first7 = T.| last8  = Otokurumada| first8 = T.| last9  = Okada| first9 = S.| last10 = Yamashita| first10 = H.| last11 = Satsukawa| first11 = Y.| last12 = Konmoto| first12 = A.| last13 = Yamashita| first13 = R.| last14 = Sugiyama| first14 = H.| date = 2003| title = Proceedings of the 40th Annual Design Automation Conference| chapter = A 1.3GHz fifth generation SPARC64 microprocessor| conference = Design Automation Conference| pages = 702–705| doi = 10.1145/775832.776010| isbn = 1-58113-688-9}}</ref>
|2001
|Fujitsu
|[[130 nm process|130&nbsp;nm]]<ref>Krewell, Kevin (21 October 2002). [http://www.eecg.toronto.edu/~moshovos/ACA07/lecturenotes/ultrasparc5%2520(mpr).pdf "Fujitsu's SPARC64 V Is Real Deal".] ''[[Microprocessor Report]]''.</ref>
|290&nbsp;mm<sup>2</sup>
|659,000
|-
|[[Pentium III]] Tualatin (32-bit, large cache)
|45,000,000
|2001
|Intel
|130&nbsp;nm
|81&nbsp;mm<sup>2</sup>
|556,000
|-
|[[Pentium 4]] Northwood (32-bit, large cache)
|55,000,000
|2002
|Intel
|130&nbsp;nm
|145&nbsp;mm<sup>2</sup>
|379,000
|-
|[[Itanium 2]] McKinley (64-bit, large cache)
|220,000,000
|2002
|Intel
|180&nbsp;nm
|421&nbsp;mm<sup>2</sup>
|523,000
|-
|[[Alpha 21364]] (64-bit, 946-pin, SIMD, very large caches) <!-- "PGA-1443 package 946 signal pins" "1,443-land flip-chip land grid array (LGA)"-->
|152,000,000<ref name="DEC Alpha">{{Cite web|url=https://en.wikichip.org/wiki/compaq/microarchitectures/alpha_21364|title=Alpha 21364 - Microarchitectures - Compaq - WikiChip|website=en.wikichip.org|access-date=2019-09-08}}</ref>
|2003
|DEC
|180&nbsp;nm
|397&nbsp;mm<sup>2</sup>
|383,000
|-
|[[AMD K7]] [[Athlon#Barton / Thorton|Barton]] (32-bit, large cache)
|54,300,000
|2003
|AMD
|130&nbsp;nm
|101&nbsp;mm<sup>2</sup>
|538,000
|-
|[[AMD K8]] (64-bit, large cache)
|105,900,000
|2003
|AMD
|130&nbsp;nm
|193&nbsp;mm<sup>2</sup>
|548,700
|-
|[[Pentium M]] Banias (32-bit)
|77,000,000<ref>{{cite web | url=https://ark.intel.com/content/www/us/en/ark/products/27577/intel-pentium-m-processor-1-60-ghz-1m-cache-400-mhz-fsb.html | title=Intel Pentium M Processor 1.60 GHZ, 1M Cache, 400 MHZ FSB Product Specifications }}</ref>
|2003
|Intel
|130&nbsp;nm
|83&nbsp;mm<sup>2</sup>
|928,000
|-
|[[Itanium 2]] Madison 6M (64-bit)
|410,000,000
|2003
|Intel
|130&nbsp;nm
|374&nbsp;mm<sup>2</sup>
|1,096,000
|-
|[[PlayStation 2]] single chip (CPU + GPU)
|53,500,000<ref>
{{cite web
|url=https://playstationdev.wiki/ps2devwiki/EE%2BGS
|title=EE+GS
|website=PS2 Dev Wiki
}}</ref>
|2003<ref>
{{cite press release
|date=2003-11-27
|title=Sony MARKETING (JAPAN) ANNOUNCES LAUNCH OF "PSX" DESR-5000 and DESR-7000 TOWARDS THE END OF 2003
|url=https://www.sony.com/en/SonyInfo/News/Press_Archive/200310/03-1007E/
|publisher=Sony
}}</ref>
|Sony, Toshiba
|90&nbsp;nm<ref>
{{cite news
|title=EMOTION ENGINE AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION BECOME ONE CHIP
|url=https://www.sie.com/content/dam/corporate/en/corporate/release/pdf/030421be.pdf
|access-date=19 March 2023
|publisher=[[Sony]]
|date=April 21, 2003
}}</ref><br>130&nbsp;nm<ref>
{{cite web
|url=https://www.theregister.com/2004/01/30/sony_psxs_90nm_cpu/
|title=Sony PSX's 90nm CPU is 'not 90nm'
|website=The Register
|date=2004-01-30
}}</ref><ref>
{{cite web
|url=https://www.eetimes.com/semi-insights-stands-by-not-90-nm-description-of-psx-chip/
|title=Semi Insights stands by 'not 90-nm' description of PSX chip
|website=EE Times
|date=2004-02-05
}}</ref>
|86&nbsp;mm<sup>2</sup>
|622,100
|-
|[[Pentium 4]] Prescott (32-bit, large cache)
|112,000,000
|2004
|Intel
|[[90 nm process|90&nbsp;nm]]
|110&nbsp;mm<sup>2</sup>
|1,018,000
|-
|[[Pentium M]] Dothan (32-bit)
|144,000,000<ref>{{cite web | url=https://ark.intel.com/content/www/us/en/ark/products/27595/intel-pentium-m-processor-760-2m-cache-2-00a-ghz-533-mhz-fsb.html | title=Intel Pentium M Processor 760 (2M Cache, 2.00A GHZ, 533 MHZ FSB) Product Specifications }}</ref>
|2004
|Intel
|90&nbsp;nm
|87&nbsp;mm<sup>2</sup>
|1,655,000
|-
|[[SPARC64 V+]] (64-bit, large cache)
|400,000,000<ref>[[Fujitsu Limited]] (August 2004). ''SPARC64 V Processor For UNIX Server''.</ref>
|2004
|Fujitsu
|90&nbsp;nm
|294&nbsp;mm<sup>2</sup>
|1,360,000
|-
|[[Itanium 2]] (64-bit;9&nbsp;[[mebibyte|MB]] cache)
|592,000,000
|2004
|Intel
|130&nbsp;nm
|432&nbsp;mm<sup>2</sup>
|1,370,000
|-
|[[Pentium 4]] Prescott-2M (32-bit, large cache)
|169,000,000
|2005
|Intel
|90&nbsp;nm
|143&nbsp;mm<sup>2</sup>
|1,182,000
|-
|[[Pentium D]] Smithfield (64-bit, large cache)
|228,000,000
|2005
|Intel
|90&nbsp;nm
|206&nbsp;mm<sup>2</sup>
|1,107,000
|-
|[[Xenon (processor)|Xenon]] (64-bit, 128-bit SIMD, large cache)
|165,000,000
|2005
|IBM
|90&nbsp;nm
|{{?}}
|{{?}}
|-
|[[Cell (microprocessor)|Cell]] (32-bit, cache)
|250,000,000<ref>{{cite web |title=A Glimpse Inside The Cell Processor |url=https://www.gamedeveloper.com/programming/a-glimpse-inside-the-cell-processor |website=[[Gamasutra]] |access-date=19 June 2019 |date=July 13, 2006}}</ref>
|2005
|Sony, IBM, Toshiba
|90&nbsp;nm
|221&nbsp;mm<sup>2</sup>
|1,131,000
|-
|[[Pentium 4]] Cedar Mill (32-bit, large cache)
|184,000,000
|2006
|Intel
|[[65 nm process|65&nbsp;nm]]
|90&nbsp;mm<sup>2</sup>
|2,044,000
|-
<!--C2Q is double die product — two C2D dies in a single package |-
|[[Core 2 Quad]] Kenfield (64-bit)
|582,000,000
|2006
|Intel
|65 nm -->
|-
|[[Pentium D]] Presler (64-bit, large cache)
|362,000,000 <ref>{{cite web|url=https://ark.intel.com/content/www/us/en/ark/products/42114/intel-pentium-d-processor-920-4m-cache-2-8-ghz-800-mhz-fsb.html |title=Intel Pentium D Processor 920 |publisher=Intel |access-date=2023-01-05}}</ref>
|2006
|Intel
|65&nbsp;nm
|162&nbsp;mm<sup>2</sup>
|2,235,000
|-
|[[Core 2 Duo]] Conroe (dual-core 64-bit, large caches)
|291,000,000
|2006
|Intel
|65&nbsp;nm
|143&nbsp;mm<sup>2</sup>
|2,035,000
|-
|Dual-core [[Itanium 2]] (64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|1,700,000,000<ref>{{cite web|url=http://www.intel.com/pressroom/kits/itanium2/ |title=PRESS KIT — Dual-core Intel Itanium Processor |publisher=Intel |access-date=2014-08-09}}</ref>
|2006
|Intel
|90&nbsp;nm
|596&nbsp;mm<sup>2</sup>
|2,852,000
|-
|[[AMD K10]] quad-core 2M L3 (64-bit, large caches)
|463,000,000<ref name="tomshardware.com">{{cite web|first=Bert |last=Toepelt |url=http://www.tomshardware.com/reviews/phenom-ii-940,2114.html |title=AMD Phenom II X4: 45nm Benchmarked — The Phenom II And AMD's Dragon Platform |publisher=TomsHardware.com |date=2009-01-08 |access-date=2014-08-09}}</ref>
|2007
|AMD
|65&nbsp;nm
|283&nbsp;mm<sup>2</sup>
|1,636,000
|-
|[[ARM architecture family|ARM Cortex-A9]] (32-bit, (optional) [[Single instruction, multiple data|SIMD]], caches)
|26,000,000<ref>{{cite web|url=http://www.engineersgarage.com/articles/arm-advanced-risc-machines-processors |title=ARM (Advanced RISC Machines) Processors |publisher=EngineersGarage.com |access-date=2014-08-09}}</ref>
|2007
|ARM
|45&nbsp;nm
|31&nbsp;mm<sup>2</sup>
|839,000
|-
|[[Core 2 Duo]] Wolfdale (dual-core 64-bit, [[Single instruction, multiple data|SIMD]], caches)
|411,000,000
|2007
|Intel
|45&nbsp;nm
|107&nbsp;mm<sup>2</sup>
|3,841,000
|-
|[[POWER6]] (64-bit, large caches)
|789,000,000
|2007
|IBM
|65&nbsp;nm
|341&nbsp;mm<sup>2</sup>
|2,314,000
|-
|[[Core 2 Duo]] Allendale (dual-core 64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|169,000,000
|2007
|Intel
|65&nbsp;nm
|111&nbsp;mm<sup>2</sup>
|1,523,000
|-
|[[Venus Engine|Uniphier]]
|250,000,000<ref name="panasonic2007">{{cite news |title=Panasonic starts to sell a New-generation UniPhier System LSI |url=http://panasonic.co.jp/corp/news/official.data/data.dir/en071010-3/en071010-3.html |access-date=2 July 2019 |publisher=[[Panasonic]] |date=October 10, 2007}}</ref>
|2007
|[[Panasonic|Matsushita]]
|45&nbsp;nm
|{{?}}
|{{?}}
|-
|[[SPARC64 VI]] (64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|540,000,000
|2007<ref>[http://www.fujitsu.com/downloads/SPARCE/others/sparc64vi-extensions.pdf "SPARC64 VI Extensions"] page 56, Fujitsu Limited, Release 1.3, 27 March 2007</ref>
|Fujitsu
|90&nbsp;nm
|421&nbsp;mm<sup>2</sup>
|1,283,000
|-
|[[Core 2 Duo]] Wolfdale 3M (dual-core 64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|230,000,000
|2008
|Intel
|45&nbsp;nm
|83&nbsp;mm<sup>2</sup>
|2,771,000
|-
|[[Core i7]] (quad-core 64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|731,000,000
|2008
|Intel
|45&nbsp;nm
|263&nbsp;mm<sup>2</sup>
|2,779,000
|-
|[[AMD K10]] quad-core 6M L3 (64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|758,000,000<ref name="tomshardware.com"/>
|2008
|AMD
|45&nbsp;nm
|258&nbsp;mm<sup>2</sup>
|2,938,000
|-
|[[Intel Atom|Atom]] (32-bit, large cache)
|47,000,000
|2008
|Intel
|[[45 nm process|45&nbsp;nm]]
|24&nbsp;mm<sup>2</sup>
|1,958,000
|-
|[[SPARC64 VII]] (64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|600,000,000
|2008<ref>Morgan, Timothy Prickett (17 July 2008). [https://web.archive.org/web/20081120140153/http://www.itjungle.com/tug/tug071708-story01.html "Fujitsu and Sun Flex Their Quads with New Sparc Server Lineup"]. ''The Unix Guardian'', Vol. 8, No. 27.</ref>
|Fujitsu
|65&nbsp;nm
|445&nbsp;mm<sup>2</sup>
|1,348,000
|-
|Six-core [[Xeon]] 7400 (64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|1,900,000,000
|2008
|Intel
|45&nbsp;nm
|503&nbsp;mm<sup>2</sup> 
|3,777,000
|-
|Six-core [[Opteron]] 2400 (64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|904,000,000
|2009
|AMD
|45&nbsp;nm
|346&nbsp;mm<sup>2</sup>
|2,613,000
|-
|[[SPARC64 VIIIfx]] (64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|760,000,000<ref>{{Cite conference|author=Takumi Maruyama|year=2009|title=SPARC64 VIIIfx: Fujitsu's New Generation Octo Core Processor for PETA Scale computing|conference=Proceedings of Hot Chips 21|url=http://www.hotchips.org/archives/hc21/3_tues/HC21.25.500.ComputingAccelerators-Epub/HC21.25.51A.Maruyama-Fujitsu-Octo-Core-VIIIfx.pdf|publisher=IEEE Computer Society|archive-url=https://web.archive.org/web/20101008183810/http://www.hotchips.org/archives/hc21/3_tues/HC21.25.500.ComputingAccelerators-Epub/HC21.25.51A.Maruyama-Fujitsu-Octo-Core-VIIIfx.pdf|archive-date=2010-10-08|access-date=30 June 2019}}</ref>
|2009
|Fujitsu
|45&nbsp;nm
|513&nbsp;mm<sup>2</sup>
|1,481,000
|-
|[[Intel Atom|Atom]] ([[Pineview (microprocessor)|Pineview]]) 64-bit, 1-core, 512 kB L2 cache
|123,000,000<ref>{{cite web
 |url=https://ark.intel.com/content/www/us/en/ark/products/42503/intel-atom-processor-n450-512k-cache-1-66-ghz.html
 |title=Intel Atom N450 specifications
 |website=Intel
 |access-date=2023-06-08
}}</ref>
|2010
|Intel
|45&nbsp;nm
|66&nbsp;mm<sup>2</sup>
|1,864,000
|-
|[[Intel Atom|Atom]] ([[Pineview (microprocessor)|Pineview]]) 64-bit, 2-core, 1 MB L2 cache
|176,000,000<ref>{{cite web
 |url=https://ark.intel.com/content/www/us/en/ark/products/43098/intel-atom-processor-d510-1m-cache-1-66-ghz.html
 |title=Intel Atom D510 specifications
 |website=Intel
 |access-date=2023-06-08
}}</ref>
|2010
|Intel
|45&nbsp;nm
|87&nbsp;mm<sup>2</sup>
|2,023,000
|-
|[[SPARC T3]] (16-core 64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|1,000,000,000<ref>{{cite web|last=Stokes |first=Jon |url=https://arstechnica.com/business/news/2010/02/two-billion-transistor-beasts-power7-and-niagara-3.ars |title=Sun's 1 billion-transistor, 16-core Niagara 3 processor |publisher=ArsTechnica.com |date=2010-02-10 |access-date=2014-08-09}}</ref>
|2010
|[[Sun Microsystems|Sun]]/[[Oracle Corporation|Oracle]]
|40&nbsp;nm
|377&nbsp;mm<sup>2</sup>
|2,653,000
|-
|Six-core [[Gulftown (microprocessor)|Core i7]] (Gulftown)
|1,170,000,000
|2010
|Intel
|32&nbsp;nm
|240&nbsp;mm<sup>2</sup>
|4,875,000
|-
|[[POWER7]] 32M L3 (8-core 64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|1,200,000,000
|2010
|IBM
|45&nbsp;nm
|567&nbsp;mm<sup>2</sup>
|2,116,000
|-
|Quad-core [[IBM z196|z196]]<ref>{{cite web|url=http://www-03.ibm.com/press/us/en/pressrelease/32414.wss#release |archive-url=https://web.archive.org/web/20100905053649/http://www-03.ibm.com/press/us/en/pressrelease/32414.wss#release |url-status=dead |archive-date=September 5, 2010 |title=IBM to Ship World's Fastest Microprocessor |publisher=IBM|date=2010-09-01 |access-date=2014-08-09}}</ref> (64-bit, very large caches)
|1,400,000,000
|2010
|IBM
|45&nbsp;nm
|512&nbsp;mm<sup>2</sup>
|2,734,000
|-
|Quad-core Itanium [[Tukwila (processor)|Tukwila]] (64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|2,000,000,000<ref>{{cite web|url=http://afp.google.com/article/ALeqM5ipelkeZwHqz3cqmha_jD7gNhB98A|title=Intel to deliver first computer chip with two billion transistors|url-status=dead|archive-url=https://web.archive.org/web/20110520120639/http://afp.google.com/article/ALeqM5ipelkeZwHqz3cqmha_jD7gNhB98A |archive-date=May 20, 2011 |agency=AFP |date=February 5, 2008 |access-date=February 5, 2008}}</ref>
|2010
|Intel
|65&nbsp;nm
|699&nbsp;mm<sup>2</sup>
|2,861,000
<!-- Magny-Cours Opteron 6100 is double die product — two dies in a single package|-
|12-core [[Opteron]] 6100
|1,810,000,000
|2010
|AMD
|45 nm
|692 mm<sup>2</sup>  -->
|-
|[[Xeon]] [[Beckton (microprocessor)|Nehalem-EX]] (8-core 64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|2,300,000,000<ref>"[http://www.intel.com/pressroom/archive/releases/20090526comp.htm Intel Previews Intel Xeon 'Nehalem-EX' Processor]." May 26, 2009. Retrieved on May 28, 2009.</ref>
|2010
|Intel
|45&nbsp;nm
|684&nbsp;mm<sup>2</sup>
|3,363,000
|-
|[[SPARC64 IXfx]] (64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|1,870,000,000<ref name="fujitsu-s64ixfx">{{citation| url = https://www.theregister.co.uk/2011/11/21/fujitsu_sparc64_ixfx_fx10_details| title = Fujitsu parades 16-core Sparc64 super stunner| first = Timothy Prickett| last = Morgan| date = November 21, 2011| work = [[The Register]]| access-date = December 8, 2011}}</ref>
|2011
|Fujitsu
|40&nbsp;nm
|484&nbsp;mm<sup>2</sup>
|3,864,000
|-
|Quad-core + [[Graphics processing unit|GPU]] [[Sandy Bridge (microarchitecture)|Core i7]] (64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|1,160,000,000
|2011
|Intel
|32&nbsp;nm
|216&nbsp;mm<sup>2</sup>
|5,370,000
|-
|Six-core [[Sandy Bridge-E (microprocessor)|Core i7]]/8-core Xeon E5<br /> (Sandy Bridge-E/EP) (64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|2,270,000,000<ref>{{cite web|first=Chris |last=Angelini |url=http://www.tomshardware.com/reviews/core-i7-3960x-x79-sandy-bridge-e,3071.html |title=Intel Core i7-3960X Review: Sandy Bridge-E And X79 Express |publisher=TomsHardware.com |date=2011-11-14 |access-date=2014-08-09}}</ref>
|2011
|Intel
|32&nbsp;nm
|434&nbsp;mm<sup>2</sup>
|5,230,000
|-
|[[Xeon]] [[Westmere-EX]] (10-core 64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|2,600,000,000
|2011
|Intel
|32&nbsp;nm
|512&nbsp;mm<sup>2</sup>
|5,078,000
|-
|[[Intel Atom|Atom]] "Medfield" (64-bit)
|432,000,000<ref>{{Cite web|url=https://www.intel.com/content/dam/www/public/us/en/documents/presentation/silicon-technology-leadership-presentation.pdf|title=IDF2012 Mark Bohr, Intel Senior Fellow}}</ref>
|2012
|Intel
|[[32 nm process|32&nbsp;nm]]
|64&nbsp;mm<sup>2</sup>
|6,750,000
|-
|[[SPARC64 X]] (64-bit, [[Single instruction, multiple data|SIMD]], caches)
|2,990,000,000<ref>{{cite web|url=https://www.fujitsu.com/global/Images/HC25.27.910-SPARC64.pdf|title=Images of SPARC64|publisher=fujitsu.com|access-date=August 29, 2017}}</ref>
|2012
|Fujitsu
|28&nbsp;nm
|600&nbsp;mm<sup>2</sup>
|4,983,000
|-
|[[AMD Bulldozer]] (8-core 64-bit, [[Single instruction, multiple data|SIMD]], caches)
|1,200,000,000<ref name="anandtech.com">{{cite web
 | url=http://www.anandtech.com/showdoc.aspx?i=3276&p=9
 | title=Intel's Atom Architecture: The Journey Begins
 | publisher=AnandTech
 | access-date=April 4, 2010
}}</ref>
|2012
|AMD
|32&nbsp;nm
|315&nbsp;mm<sup>2</sup> 
|3,810,000
|-
|Quad-core + GPU [[AMD Trinity]] (64-bit, [[Single instruction, multiple data|SIMD]], caches)
|1,303,000,000
|2012
|AMD
|32&nbsp;nm
|246&nbsp;mm<sup>2</sup>
|5,297,000
|-
|Quad-core + GPU [[Ivy Bridge (microarchitecture)|Core i7 Ivy Bridge]] (64-bit, [[Single instruction, multiple data|SIMD]], caches)
|1,400,000,000
|2012
|Intel
|[[22 nm process|22&nbsp;nm]]
|160&nbsp;mm<sup>2</sup>
|8,750,000
|-
|[[POWER7#POWER7+|POWER7+]] (8-core 64-bit, [[Single instruction, multiple data|SIMD]], 80&nbsp;MB L3 cache)
|2,100,000,000
|2012
|IBM
|32&nbsp;nm
|567&nbsp;mm<sup>2</sup>
|3,704,000
|-
|Six-core [[IBM zEC12 (microprocessor)|zEC12]] (64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|2,750,000,000
|2012
|IBM
|32&nbsp;nm
|597&nbsp;mm<sup>2</sup>
|4,606,000
|-
|Itanium [[Poulson (processor)|Poulson]] (8-core 64-bit, [[Single instruction, multiple data|SIMD]], caches)
|3,100,000,000
|2012
|Intel
|32&nbsp;nm
|544&nbsp;mm<sup>2</sup>
|5,699,000
|-
|[[Xeon Phi]] (61-core 32-bit, 512-bit [[Single instruction, multiple data|SIMD]], caches) <!-- prior to 64-bit upgrade? 512-bit SIMD, but not AVX-512 -->
|5,000,000,000<ref>{{cite web|url=http://www.techpowerup.com/gpudb/1891/xeon-phi-se10x.html |title=Intel Xeon Phi SE10X |publisher=TechPowerUp |access-date = 2015-07-20}}</ref>
|2012
|Intel
|22&nbsp;nm
|720&nbsp;mm<sup>2</sup>
|6,944,000
|-
|[[Apple A7]] (dual-core 64/32-bit [[ARM64]], "mobile [[System on a chip|SoC]]", [[Single instruction, multiple data|SIMD]], caches)
|1,000,000,000
|2013
|[[Apple Inc.|Apple]]
|28&nbsp;nm
|102&nbsp;mm<sup>2</sup>
|9,804,000
|-
|Six-core [[Ivy Bridge (microarchitecture)|Core i7 Ivy Bridge E]] (64-bit, [[Single instruction, multiple data|SIMD]], caches)
|1,860,000,000
|2013
|Intel
|22&nbsp;nm
|256&nbsp;mm<sup>2</sup>
|7,266,000
|-
|[[POWER8]] (12-core 64-bit, [[Single instruction, multiple data|SIMD]], caches)
|4,200,000,000
|2013
|IBM
|22&nbsp;nm
|650&nbsp;mm<sup>2</sup>
|6,462,000
|-
|[[Xbox One]] main SoC (64-bit, [[Single instruction, multiple data|SIMD]], caches)
|5,000,000,000
|2013
|[[Microsoft]], AMD
|28&nbsp;nm
|363&nbsp;mm<sup>2</sup>
|13,770,000
|-
|Quad-core + GPU [[Haswell (microarchitecture)|Core i7 Haswell]] (64-bit, [[Single instruction, multiple data|SIMD]], caches)
|1,400,000,000<ref name="anandtech">{{cite web|last1=Shimpi|first1=Lal|title=The Haswell Review: Intel Core i7-4770K & i5-4670K Tested|url=http://www.anandtech.com/show/7003/the-haswell-review-intel-core-i74770k-i54560k-tested/5|website=anandtech|access-date=20 November 2014}}</ref>
|2014
|Intel
|22&nbsp;nm
|177&nbsp;mm<sup>2</sup>
|7,910,000
|-
|[[Apple A8]] (dual-core 64/32-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|2,000,000,000
|2014
|Apple
|20&nbsp;nm
|89&nbsp;mm<sup>2</sup>
|22,470,000
|-
|[[Haswell (microarchitecture)|Core i7 Haswell-E]] (8-core 64-bit, [[Single instruction, multiple data|SIMD]], caches)
|2,600,000,000<ref>"{{cite web|url=http://www.overclockersclub.com/reviews/iintel_core_i7_5960x_extreme_edition/|title=Intel Core i7 5960X Extreme Edition Review|website=Overclockers Club|first=Frank|last=Dimmick|date=August 29, 2014|access-date=August 29, 2014}}</ref>
|2014
|Intel
|22&nbsp;nm
|355&nbsp;mm<sup>2</sup>
|7,324,000
|-
|[[Apple A8X]] (tri-core 64/32-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|3,000,000,000<ref>{{cite web |url=http://www.notebookcheck.net/Apple-A8X-iPad-SoC.128403.0.html|title=Apple A8X |access-date=2015-07-20 |website=NotebookCheck}}</ref>
|2014
|Apple
|20&nbsp;nm
|128&nbsp;mm<sup>2</sup>
|23,440,000
|-
|Xeon Ivy Bridge-EX (15-core 64-bit, [[Single instruction, multiple data|SIMD]], caches)
|4,310,000,000<ref>{{cite web|url=http://www.anandtech.com/show/7753/intel-readying-15core-xeon-e7-v2 |title=Intel Readying 15-core Xeon E7 v2 |publisher=AnandTech |access-date=2014-08-09}}</ref>
|2014
|Intel
|22&nbsp;nm
|541&nbsp;mm<sup>2</sup>
|7,967,000
|-
|[[Haswell (microarchitecture)|Xeon Haswell-E5]] (18-core 64-bit, [[Single instruction, multiple data|SIMD]], caches)
|5,560,000,000<ref name="pcper">{{cite web|title=Intel Xeon E5-2600 v3 Processor Overview: Haswell-EP Up to 18 Cores|url=http://www.pcper.com/reviews/Processors/Intel-Xeon-E5-2600-v3-Processor-Overview-Haswell-EP-18-Cores/5|website=pcper|date=September 8, 2014|access-date=29 January 2015}}</ref>
|2014
|Intel
|22&nbsp;nm
|661&nbsp;mm<sup>2</sup>
|8,411,000
|-
|Quad-core + GPU GT2 [[Skylake (microarchitecture)|Core i7 Skylake K]] (64-bit, [[Single instruction, multiple data|SIMD]], caches)
|1,750,000,000
|2015
|Intel
|[[14 nm process|14&nbsp;nm]]
|122&nbsp;mm<sup>2</sup>
|14,340,000
|-
|Dual-core + GPU Iris [[Broadwell (microarchitecture)|Core i7 Broadwell-U]] (64-bit, [[Single instruction, multiple data|SIMD]], caches)
|1,900,000,000<ref name="techreport">{{cite web |title=Intel's Broadwell-U arrives aboard 15W, 28W mobile processors |date=January 5, 2015|url=http://techreport.com/news/27557/intel-broadwell-u-arrives-aboard-15w-28w-mobile-processors|access-date=5 January 2015 |publisher=TechReport}}</ref>
|2015
|Intel
|14&nbsp;nm
|133&nbsp;mm<sup>2</sup>
|14,290,000
|-
|rowspan="2" | [[Apple A9]] (dual-core 64/32-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|rowspan="2" | 2,000,000,000+
|rowspan="2" | 2015
|rowspan="2" | Apple
|14&nbsp;nm<br />([[Samsung Electronics|Samsung]])
|96&nbsp;mm<sup>2</sup><br />([[Samsung Electronics|Samsung]])
|20,800,000+
|-
|16&nbsp;nm<br />([[TSMC]])
|104.5&nbsp;mm<sup>2</sup><br />([[TSMC]])
|19,100,000+
|-
|[[Apple A9X]] (dual core 64/32-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|3,000,000,000+
|2015
|Apple
|16&nbsp;nm
|143.9&nbsp;mm<sup>2</sup>
|20,800,000+
|-
|[[IBM z13 (microprocessor)|IBM z13]] (64-bit, caches)
|3,990,000,000
|2015
|IBM
|22&nbsp;nm
|678&nbsp;mm<sup>2</sup>
|5,885,000
|-
|[[IBM z13 (microprocessor)#Storage Controller|IBM z13 Storage Controller]]
|7,100,000,000
|2015
|IBM
|22&nbsp;nm
|678&nbsp;mm<sup>2</sup>
|10,472,000
|-
|[[SPARC]] M7 (32-core 64-bit, [[Single instruction, multiple data|SIMD]], caches)
|10,000,000,000<ref>{{Cite web|url=http://www.enterprisetech.com/2014/08/13/oracle-cranks-cores-32-sparc-m7-chip/|title=Oracle Cranks up the Cores to 32 with Sparc M7 Chip|work=EnterpriseTech |date=August 13, 2014}}</ref>
|2015
|Oracle
|20&nbsp;nm
|{{?}}
|{{?}}
|-
|[[Broadwell (microarchitecture)#"Broadwell-E" HEDT (14 nm)|Core i7 Broadwell-E]] (10-core 64-bit, [[Single instruction, multiple data|SIMD]], caches)
|3,200,000,000<ref>{{Cite web|url=http://www.tomshardware.com/reviews/intel-core-i7-broadwell-e-6950x-6900k-6850k-6800k,4587.html|title=Broadwell-E: Intel Core i7-6950X, 6900K, 6850K & 6800K Review|date=2016-05-30|website=Tom's Hardware|access-date=2017-04-12}}</ref>
|2016
|Intel
|14&nbsp;nm
|246&nbsp;mm<sup>2</sup><ref>{{Cite magazine|url=http://www.pcgamer.com/the-broadwell-e-review/|title=The Broadwell-E Review|date=2016-07-08|magazine=PC Gamer|access-date=2017-04-12}}</ref>
|13,010,000
|-
|[[Apple A10|Apple A10 Fusion]] (quad-core 64/32-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|3,300,000,000
|2016
|Apple
|16&nbsp;nm
|125&nbsp;mm<sup>2</sup>
|26,400,000
|-
||HiSilicon Kirin 960 (octa-core 64/32-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|4,000,000,000<ref>{{cite web|url=https://www.firstpost.com/tech/news-analysis/huawei-to-unveil-kirin-970-soc-with-ai-unit-5-5-billion-transistors-and-1-2-gbps-lte-speed-at-ifa-2017-3996027.html|title=HUAWEI TO UNVEIL KIRIN 970 SOC WITH AI UNIT, 5.5 BILLION TRANSISTORS AND 1.2 GBPS LTE SPEED AT IFA 2017|date=2017-09-01|website=firstpost.com|access-date=2018-11-18}}</ref>
|2016
|[[Huawei]]
|16&nbsp;nm
|110.00&nbsp;mm<sup>2</sup>
|36,360,000
|-
|[[Broadwell (microarchitecture)|Xeon Broadwell-E5]] (22-core 64-bit, [[Single instruction, multiple data|SIMD]], caches)
|7,200,000,000<ref>{{Cite web|url=http://www.tomshardware.com/reviews/intel-xeon-e5-2600-v4-broadwell-ep,4514-2.html|title=Broadwell-EP Architecture - Intel Xeon E5-2600 v4 Broadwell-EP Review|date=2016-03-31|website=Tom's Hardware|access-date=2016-04-04}}</ref>
|2016
|Intel
|14&nbsp;nm
|456&nbsp;mm<sup>2</sup>
|15,790,000
|-
|[[Xeon Phi]] (72-core 64-bit, 512-bit [[Single instruction, multiple data|SIMD]], caches) <!-- seems after upgrade from 32-bit; AVX-512 -->
|8,000,000,000
|2016
|Intel
|14&nbsp;nm
|683&nbsp;mm<sup>2</sup>
|11,710,000
|-
|Zip CPU (32-bit, for [[field-programmable gate array|FPGA]]s)
|1,286 6-LUTs<!-- "between 1286 and 4926 6-LUTs" --><ref>{{Cite web|url=http://zipcpu.com/about/zipcpu.html|title=About the ZipCPU|website=zipcpu.com|quote=As of ORCONF, 2016, the ZipCPU used between 1286 and 4926 6-LUTs, depending upon how it is configured.  <!--This number is out of date, though, for the same reason that the Dhrystone benchmark measure is out of date: the ZipCPU has since been modified to support 8-bit bytes. I can say, though, that I was able to pack more logic into the CMod-S6 as a result than I could pack into it before, suggesting that the new and improved CPU uses even fewer resources.-->|access-date=2019-09-10}}</ref><!-- to calculate/translate to nr. of transistors, "Transistor-sizing" may be helpful: http://www.eecg.utoronto.ca/~vaughn/papers/fpt2013_coffe.pdf -->
|2016
|Gisselquist Technology
|{{?}}
|{{?}}
|{{?}}
|-
|[[Qualcomm Snapdragon|Qualcomm Snapdragon 835]] (octa-core 64/32-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|3,000,000,000<ref>{{cite web |url=https://www.notebookcheck.net/Qualcomm-Snapdragon-835-SoC-Benchmarks-and-Specs.207842.0.html |access-date=2017-09-23 |title=Qualcomm Snapdragon 835 (8998) |website=NotebookCheck}}</ref><ref>{{cite web |url=https://venturebeat.com/2017/01/03/qualcomms-snapdragon-835-will-debut-with-3-billion-transistors-and-a-10nm-manufacturing-process/ |title=Qualcomm's Snapdragon 835 will debut with 3 billion transistors and a 10nm manufacturing process |last=Takahashi |first=Dean |date=January 3, 2017 |website=VentureBeat}}</ref>
|2016
|[[Qualcomm]]
|[[10 nm process|10&nbsp;nm]]
|72.3&nbsp;mm<sup>2</sup>
|41,490,000
|-
|[[Apple A11|Apple A11 Bionic]] (hexa-core 64/32-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|4,300,000,000
|2017
|Apple
|10&nbsp;nm
|89.23&nbsp;mm<sup>2</sup>
|48,190,000
|-
|AMD [[Zen (first generation)|Zen]] CCX (core complex unit: 4 cores, 8 MB L3 cache)
|1,400,000,000<ref>{{Cite conference
 |first=Teja
 |last=Singh
 |book-title=Proc. IEEE International Solid-State Circuits Conference
 |title=3.2 Zen: A Next-Generation High-Performance x86 Core
 |pages=52–54
 |date=2017}}</ref>
|2017
|AMD
|14&nbsp;nm<br>(GF&nbsp;14LPP)
|44&nbsp;mm<sup>2</sup>
|31,800,000
|-
|AMD Zeppelin SoC [[Zen (microarchitecture)|Ryzen]] (64-bit, [[Single instruction, multiple data|SIMD]], caches)
|4,800,000,000<ref name="Anand_zen_announcement">{{cite news|last1=Cutress|first1=Ian|title=AMD Launches Zen|url=http://www.anandtech.com/show/11143/amd-launch-ryzen-52-more-ipc-eight-cores-for-under-330-preorder-today-on-sale-march-2nd|access-date=22 February 2017|publisher=Anandtech.com|date=22 February 2017}}</ref>
|2017
|AMD
|14&nbsp;nm
|192&nbsp;mm<sup>2</sup> 
|25,000,000
|-
|AMD Ryzen 5 1600 [[Zen (microarchitecture)|Ryzen]] (64-bit, [[Single instruction, multiple data|SIMD]], caches)
|4,800,000,000<ref>{{cite web|url=https://en.wikichip.org/wiki/amd/ryzen_5/1600|title=Ryzen 5 1600 - AMD|date=2018-04-20|website=Wikichip.org|access-date=2018-12-09}}</ref>
|2017
|AMD
|14&nbsp;nm
|213&nbsp;mm<sup>2</sup> 
|22,530,000
|-
|[[IBM z14 (microprocessor)|IBM z14]] (64-bit, [[Single instruction, multiple data|SIMD]], caches)
|6,100,000,000
|2017
|IBM
|14&nbsp;nm
|696&nbsp;mm<sup>2</sup>
|8,764,000
|-
|[[IBM z14 (microprocessor)#Storage Controller|IBM z14 Storage Controller]] (64-bit)
|9,700,000,000
|2017
|IBM
|14&nbsp;nm
|696&nbsp;mm<sup>2</sup>
|13,940,000
|-
||HiSilicon Kirin 970 (octa-core 64/32-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|5,500,000,000<ref>{{cite web|url=https://en.wikichip.org/wiki/hisilicon/kirin/970|title=Kirin 970{{Snd}} HiSilicon|date=2018-03-01|website=Wikichip|access-date=2018-11-08}}</ref>
|2017
|Huawei
|10&nbsp;nm
|96.72&nbsp;mm<sup>2</sup>
|56,900,000
|-
|[[Xbox One X|Xbox One X (Project Scorpio)]] main SoC (64-bit, [[Single instruction, multiple data|SIMD]], caches)
|7,000,000,000<ref name=":0" />
|2017
|Microsoft, AMD
|16&nbsp;nm
|360&nbsp;mm<sup>2</sup><ref name=":0">{{Cite web|url=http://www.eurogamer.net/articles/digitalfoundry-2017-project-scorpio-tech-revealed|title=Inside the next Xbox: Project Scorpio tech revealed|last=Leadbetter|first=Richard|date=2017-04-06|website=Eurogamer|access-date=2017-05-03}}</ref>
|19,440,000
|-
|[[Skylake (microarchitecture)|Xeon Platinum 8180]] (28-core 64-bit, [[Single instruction, multiple data|SIMD]], caches)
|8,000,000,000<ref>{{Cite web|url=https://www.techpowerup.com/cpudb/2055/xeon-platinum-8180|title=Intel Xeon Platinum 8180|date=2018-12-01|website=TechPowerUp|access-date=2018-12-02}}</ref>
|2017
|Intel
|14&nbsp;nm
|{{?}}
|{{?}}
|-
|Xeon (unspecified)
|7,100,000,000<ref>{{Cite web
 |first=Stefano
 |last=Pellerano
 |url=https://youtube.com/watch?v=pFQj6L4eKc0
 |title=Circuit Design to Harness the Power of Scaling and Integration (ISSCC 2022)
 |website=YouTube
 |date=2022-03-02}}</ref>
|2017
|Intel
|14&nbsp;nm
|672&nbsp;mm<sup>2</sup>
|10,570,000
|-
|[[POWER9]] (64-bit, [[Single instruction, multiple data|SIMD]], caches)
|8,000,000,000
|2017
|IBM
|14&nbsp;nm
|695&nbsp;mm<sup>2</sup>
|11,500,000
|-
|Freedom U500 Base Platform Chip (E51, 4×U54) [[RISC-V]] (64-bit, caches)
|250,000,000<ref>{{cite web |first=Y. |last=Lee |title=SiFive Freedom SoCs : Industry's First Open Source RISC V Chips |work=HotChips 29 IOT/Embedded |url=https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.20-IOT-Embedded-Pub/HC29.21.210-Freedom-SoCs-Lee-SiFive-v2.pdf |access-date=June 19, 2019 |archive-date=August 9, 2020 |archive-url=https://web.archive.org/web/20200809140551/https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.20-IOT-Embedded-Pub/HC29.21.210-Freedom-SoCs-Lee-SiFive-v2.pdf |url-status=dead }}</ref>
|2017
|[[SiFive]]
|28&nbsp;nm
|data-sort-value="30"|~30&nbsp;mm<sup>2</sup>
|8,330,000
|-
|[[SPARC64 V|SPARC64 XII]] (12-core 64-bit, [[Single instruction, multiple data|SIMD]], caches)
|5,450,000,000<ref>{{cite web|url=http://www.fujitsu.com/jp/documents/products/computing/servers/unix/sparc/events/2017/coolchips20/CoolChips20-rev8.pdf|title=Documents at Fujitsu|publisher=fujitsu.com|access-date=August 29, 2017}}</ref>
|2017
|Fujitsu
|20&nbsp;nm
|795&nbsp;mm<sup>2</sup>
|6,850,000
|-
||[[Apple A10X Fusion]] (hexa-core 64/32-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|4,300,000,000<ref>{{cite web|url=https://www.zdnet.de/88346243/ipad-pro-2018-a12x-prozessor-bietet-deutlich-mehr-leistung/|title=iPad Pro 2018: A12X-Prozessor bietet deutlich mehr Leistung|language=de|first=Kai|last=Schmerer|date=5 November 2018|website=ZDNet.de}}</ref>
|2017
|Apple
|10&nbsp;nm
|96.40&nbsp;mm<sup>2</sup>
|44,600,000
|-
|[[Centriq]] 2400 (64/32-bit, [[Single instruction, multiple data|SIMD]], caches)
|18,000,000,000<ref>{{Cite news|url=https://www.qualcomm.com/news/releases/2017/11/08/qualcomm-datacenter-technologies-announces-commercial-shipment-qualcomm|title=Qualcomm Datacenter Technologies Announces Commercial Shipment of Qualcomm Centriq 2400 – The World's First 10nm Server Processor and Highest Performance Arm-based Server Processor Family Ever Designed|work=Qualcomm|access-date=2017-11-09}}</ref>
|2017
|Qualcomm
|10&nbsp;nm
|398&nbsp;mm<sup>2</sup>
|45,200,000
|-
|AMD [[Epyc]] (32-core 64-bit, [[Single instruction, multiple data|SIMD]], caches)
|19,200,000,000<!-- misleading? still "micro"processor if not on same die? or MCM an exception? explicist 19.2 miilion count hard to find, independent of [4×] 4.8 million. -->
|2017
|AMD
|14&nbsp;nm
|768&nbsp;mm<sup>2</sup>
|25,000,000
|-
|[[Qualcomm Snapdragon|Qualcomm Snapdragon 845]] (octa-core 64/32-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|5,300,000,000<ref>{{cite web|url=https://www.techradar.com/news/qualcomm-snapdragon-1000-for-laptops-could-pack-85-billion-transistors|access-date=2017-09-23|title=Qualcomm Snapdragon 1000 for laptops could pack 8.5 billion transistors|publisher=techradar}}</ref>
|2017
|Qualcomm
|10&nbsp;nm
|94&nbsp;mm<sup>2</sup>
|56,400,000
|-
|[[Qualcomm Snapdragon|Qualcomm Snapdragon 850]] (octa-core 64/32-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|5,300,000,000<ref>{{cite web|url=https://www.anandtech.com/show/13687/qualcomm-snapdragon-8cx-wafer-on-7nm|access-date=2018-12-06|title=Spotted: Qualcomm Snapdragon 8cx Wafer on 7nm|publisher=AnandTech}}</ref>
|2017
|Qualcomm
|10&nbsp;nm
|94&nbsp;mm<sup>2</sup>
|56,400,000
|-
||HiSilicon Kirin 710 (octa-core ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|5,500,000,000<ref>{{cite web|url=https://www.notebookcheck.net/HiSilicon-Kirin-710-SoC-Benchmarks-and-Specs.333292.0.html |title=HiSilicon Kirin 710 |date=2018-09-19 |website=Notebookcheck |access-date=2018-11-24}}</ref>
|2018
|Huawei
|12&nbsp;nm
|{{?}}
|{{?}}
|-
||[[Apple A12 Bionic]] (hexa-core ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|6,900,000,000<br><ref name="TechInsights-iPhoneXSmax">{{cite web|last1=Yang|first1=Daniel|last2=Wegner|first2=Stacy|url=http://www.techinsights.com/about-techinsights/overview/blog/apple-iphone-xs-teardown/|title=Apple iPhone Xs Max Teardown|publisher=TechInsights|date=September 21, 2018|access-date=September 21, 2018}}</ref><ref>{{Cite news|url=https://www.engadget.com/2018/09/12/apple-a12-bionic-7-nanometer-chip/|title=Apple's A12 Bionic is the first 7-nanometer smartphone chip|work=Engadget|access-date=2018-09-26}}</ref>
|2018
|Apple
|7&nbsp;nm
|83.27&nbsp;mm<sup>2</sup>
|82,900,000
|-
||HiSilicon Kirin 980 (octa-core ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|6,900,000,000<ref>{{cite web|url=https://en.wikichip.org/wiki/hisilicon/kirin/980|title=Kirin 980{{Snd}} HiSilicon|date=2018-11-08|website=Wikichip|access-date=2018-11-08}}</ref>
|2018
|Huawei
|7&nbsp;nm
|74.13&nbsp;mm<sup>2</sup>
|93,100,000
|-
|[[Qualcomm Snapdragon|Qualcomm Snapdragon 8cx / SCX8180]] (octa-core ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|8,500,000,000<ref>{{cite web|url=https://m.dailyhunt.in/news/bangladesh/english/gear-epaper-gear/qualcomm+snapdragon+8180+7nm+soc+sdm1000+with+8+5+billion+transistors+to+challenge+apple+a12+bionic+chipset-newsid-97431923|access-date=2018-09-21|title=Qualcomm Snapdragon 8180: 7nm SoC SDM1000 With 8.5 Billion Transistors To Challenge Apple A12 Bionic Chipset |publisher=dailyhunt}}</ref>
|2018
|Qualcomm
|7&nbsp;nm
|112&nbsp;mm<sup>2</sup>
|75,900,000
|-
||[[Apple A12X Bionic]] (octa-core 64/32-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|10,000,000,000<ref>{{cite web|url=https://wccftech.com/apple-a12x-10-billion-transistors-performance/|title=Apple's A12X Has 10 Billion Transistors, 90% Performance Boost & 7-Core GPU|first=Ramish|last=Zafar|date=October 30, 2018|website=Wccftech}}</ref>
|2018
|Apple
|7&nbsp;nm
|122&nbsp;mm<sup>2</sup>
|82,000,000
|-
|[[Fujitsu]] A64FX (64/32-bit, [[Single instruction, multiple data|SIMD]], caches)
|8,786,000,000<ref>{{cite news |title=Fujitsu began to produce Japan's billions of super-calculations with the strongest ARM processor A64FX |url=http://images.firstxw.com/view/230119.html |access-date=19 June 2019 |work=firstxw.com |date=2019-04-16 |archive-date=June 20, 2019 |archive-url=https://web.archive.org/web/20190620065621/http://images.firstxw.com/view/230119.html |url-status=dead }}</ref>
|2018<ref>{{cite news |title=Fujitsu Successfully Triples the Power Output of Gallium-Nitride Transistors |url=https://www.fujitsu.com/global/about/resources/news/press-releases/2018/0822-02.html |access-date=19 June 2019 |work=[[Fujitsu]] |date=August 22, 2018}}</ref>
|Fujitsu
|7&nbsp;nm
|{{?}}
|{{?}}
|-
|[[Tegra]] Xavier SoC (64/32-bit<!-- for ARM-based part of it-->)
|9,000,000,000<ref>{{cite web|url=https://fuse.wikichip.org/news/1618/hot-chips-30-nvidia-xavier-soc |title=Hot Chips 30: Nvidia Xavier SoC |website=fuse.wikichip.org |date=2018-09-18 |access-date=2018-12-06}}</ref>
|2018
|[[Nvidia]]
|12&nbsp;nm
|350&nbsp;mm<sup>2</sup>
|25,700,000
|-
|[[Qualcomm Snapdragon|Qualcomm Snapdragon 855]] (octa-core 64/32-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|6,700,000,000<ref>{{Cite web|last=Frumusanu|first=Andrei|title=The Samsung Galaxy S10+ Snapdragon & Exynos Review: Almost Perfect, Yet So Flawed|url=https://www.anandtech.com/show/14072/the-samsung-galaxy-s10plus-review|access-date=2021-02-19|website=www.anandtech.com}}</ref>
|2018
|Qualcomm
|7&nbsp;nm
|73&nbsp;mm<sup>2</sup>
|91,800,000
|-
|AMD [[Zen 2]] core (0.5 MB L2 + 4 MB L3 cache)
|475,000,000<ref name=zen2 />
|2019
|AMD
|7&nbsp;nm
|7.83&nbsp;mm<sup>2</sup>
|60,664,000
|-
|AMD [[Zen 2]] CCX (core complex: 4 cores, 16 MB L3 cache)
|1,900,000,000<ref name=zen2>{{cite web
 |url=https://en.wikichip.org/wiki/amd/microarchitectures/zen_2
 |title=Zen 2 Microarchitecture
 |website=WikiChip
 |access-date=2023-02-21}}</ref>
|2019
|AMD
|7&nbsp;nm
|31.32&nbsp;mm<sup>2</sup>
|60,664,000
|-
|AMD [[Zen 2]] CCD (core complex die: 8 cores, 32 MB L3 cache)
|3,800,000,000<ref name=zen2 />
|2019
|AMD
|7&nbsp;nm
|74&nbsp;mm<sup>2</sup>
|51,350,000
|-
|AMD [[Zen 2]] client I/O die
|2,090,000,000<ref name=zen2 />
|2019
|AMD
|12&nbsp;nm 
|125&nbsp;mm<sup>2</sup>
|16,720,000
|-
|AMD [[Zen 2]] server I/O die
|8,340,000,000<ref name=zen2 />
|2019
|AMD
|12&nbsp;nm 
|416&nbsp;mm<sup>2</sup>
|20,050,000
|-
|AMD [[Zen 2]] Renoir die
|9,800,000,000<ref name=zen2 />
|2019
|AMD
|7&nbsp;nm 
|156&nbsp;mm<sup>2</sup>
|62,820,000
|-
|[[AMD]] [[Zen 2#Desktop processors|Ryzen]] 7 3700X (64-bit, [[Single instruction, multiple data|SIMD]], caches, I/O die)
|5,990,000,000<ref>{{cite news |title=AMD Ryzen 9 3900X and Ryzen 7 3700X Review: Zen 2 and 7nm Unleashed |url=https://www.tomshardware.com/reviews/ryzen-9-3900x-7-3700x-review,6214.html |access-date=19 October 2019 |work=[[Tom's Hardware]] |date=7 July 2019}}</ref>{{efn|3,900,000,000 core chiplet die, 2,090,000,000 I/O die}}
|2019
|AMD
|7 & 12&nbsp;nm<br>([[TSMC]])
|199&nbsp;<br><small>(74+125)&nbsp;mm<sup>2</sup></small>
|30,100,000
|-
|HiSilicon Kirin 990 4G
|8,000,000,000<ref>{{Cite web|url= https://www.anandtech.com/show/15099/the-huawei-mate-30-pro-review-top-hardware-without-google/2|title=The Huawei Mate 30 Pro Review: Top Hardware without Google?|last=Frumusanu|first=Andrei|website=AnandTech|language=en-US|access-date=2020-01-02}}</ref>
|2019
|Huawei
|7&nbsp;nm
|90.00&nbsp;mm<sup>2</sup>
|89,000,000
|-
|[[Apple A13]] (hexa-core 64-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|8,500,000,000<br><ref>{{Cite web|url=https://wccftech.com/apple-a13-iphone-11-transistors-gpu/|title=Apple A13 For iPhone 11 Has 8.5 Billion Transistors, Quad-Core GPU|last=Zafar|first=Ramish|date=2019-09-10|website=Wccftech|access-date=2019-09-11}}</ref><ref>{{Citation|title=Introducing iPhone 11 Pro — Apple Youtube Video|url=https://www.youtube.com/watch?v=cVEemOmHw9Y&t=70|access-date=2019-09-11}}{{cbignore}}{{Dead YouTube link|date=February 2022}}</ref>
|2019
|Apple
|7&nbsp;nm
|98.48&nbsp;mm<sup>2</sup>
|86,300,000
|-
|[[IBM z15 (microprocessor)|IBM z15 CP chip]] (12 cores, 256 MB L3 cache)
|9,200,000,000<ref>{{cite web|url=https://www.anandtech.com/show/15987/hot-chips-2020-live-blog-ibm-z15-a-52-ghz-mainframe-cpu-1100am-pt|title=Hot Chips 2020 Live Blog: IBM z15|website=AnandTech|date=2020-08-17}}</ref>
|2019
|IBM
|14&nbsp;nm
|696&nbsp;mm<sup>2</sup>
|13,220,000
|-
|[[IBM z15 (microprocessor)|IBM z15 SC chip]] (960 MB L4 cache)
|12,200,000,000
|2019
|IBM
|14&nbsp;nm
|696&nbsp;mm<sup>2</sup>
|17,530,000
|-
|[[AMD]] [[Zen 2#Desktop processors|Ryzen]] 9 3900X (64-bit, [[Single instruction, multiple data|SIMD]], caches, I/O die)
|9,890,000,000<br><ref name="Zen2 THW">{{cite news|title=AMD's 64-Core EPYC and Ryzen CPUs Stripped: A Detailed Inside Look|url=https://www.tomshardware.com/news/amd-64-core-epyc-cpu-die-design-architecture-ryzen-3000|last=Broekhuijsen|first=Niels|date=23 October 2019|access-date=24 October 2019}}</ref><ref name="Zen2 wcftech">{{cite news|title=AMD 2nd Gen EPYC Rome Processors Feature A Gargantuan 39.54 Billion Transistors, IO Die Pictured in Detail|url=https://wccftech.com/amd-2nd-gen-epyc-rome-iod-ccd-chipshots-39-billion-transistors/|last=Mujtaba|first=Hassan|date=22 October 2019|access-date=24 October 2019}}</ref>
|2019
|AMD
|7 & 12&nbsp;nm<br>([[TSMC]])
|273&nbsp;mm<sup>2</sup>
|36,230,000
|-
|HiSilicon Kirin 990 5G
|10,300,000,000<ref>{{Cite web|url=https://www.phonearena.com/news/Huawei-tipped-to-develop-new-flagship-chip-for-Mate-40_id121102|title=5nm Kirin 1020 SoC tipped for next year's Huawei Mate 40 line|last=Friedman|first=Alan|website=Phone Arena|date=December 14, 2019 |language=en-US|access-date=2019-12-23}}</ref>
|2019
|Huawei
|7&nbsp;nm
|113.31&nbsp;mm<sup>2</sup>
|90,900,000
|-
|AWS Graviton2 (64-bit, 64-core ARM-based, [[Single instruction, multiple data|SIMD]], caches)<ref>{{Cite web|url=https://www.tomshardware.com/news/amazon-web-services-takes-on-intel-with-64-core-arm-graviton2|title=Amazon Compares 64-core ARM Graviton2 to Intel's Xeon|first=Arne |last=Verheyde |website=Tom's Hardware|date=December 5, 2019|language=en|access-date=2019-12-06}}</ref><ref>{{Cite web|url=https://www.nextplatform.com/2019/12/03/finally-aws-gives-servers-a-real-shot-in-the-arm/|title=Finally: AWS Gives Servers A Real Shot In The Arm|last=Morgan|first=Timothy Prickett|date=2019-12-03|website=The Next Platform|language=en-US|access-date=2019-12-06}}</ref>
|30,000,000,000
|2019
|[[Amazon (company)|Amazon]]
|7&nbsp;nm
|{{?}}
|{{?}}
|-
|AMD [[Epyc]] Rome (64-bit, [[Single instruction, multiple data|SIMD]], caches)
|39,540,000,000<br><ref name="Zen2 THW"/><ref name="Zen2 wcftech"/>
|2019
|AMD
|7 & 12&nbsp;nm<br>([[TSMC]])
|1,008&nbsp;mm<sup>2</sup>
|39,226,000
|-
|[[Qualcomm Snapdragon|Qualcomm Snapdragon 865]] (octa-core 64/32-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|10,300,000,000<ref>{{Cite web|last=Friedman|first=Alan|title=Qualcomm will reportedly introduce the Snapdragon 865 SoC as soon as next month|url=https://www.phonearena.com/news/Qualcomm-to-unveil-the-Snapdragon-865-chipset-as-soon-as-next-month_id119548|access-date=2021-02-19|website=Phone Arena|date=October 10, 2019 |language=en-US}}</ref>
|2019
|Qualcomm
|7&nbsp;nm
|83.54&nbsp;mm<sup>2</sup><ref>{{Cite web|title=Xiaomi Mi 10 Teardown Analysis {{!}} TechInsights|url=https://www.techinsights.com/blog/xiaomi-mi-10-teardown-analysis#:~:text=We%20have%20die%20photos%20ready,die%20HG11-PC761-2.|access-date=2021-02-19|website=www.techinsights.com}}</ref>
|123,300,000
|-
|TI Jacinto TDA4VM (ARM A72, DSP, SRAM)
|3,500,000,000<ref>{{Cite web|title=The Linley Group - TI Jacinto Accelerates Level 3 ADAS|url=https://www.linleygroup.com/newsletters/newsletter_detail.php?num=6130&year=2020&tag=3|access-date=2021-02-12|website=www.linleygroup.com}}</ref>
|2020
|Texas Instruments
|16&nbsp;nm
|{{?}}
|{{?}}
|-
|[[Apple A14 Bionic]] (hexa-core 64-bit ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|11,800,000,000<ref>{{Cite web|date=2020-11-10|title=Apple unveils A14 Bionic processor with 40% faster CPU and 11.8 billion transistors|url=https://venturebeat.com/2020/09/15/apple-unveils-a14-bionic-processor-with-40-faster-cpu-and-11-8-billion-transistors/|access-date=2020-11-24|website=Venturebeat|language=en-US}}</ref>
|2020
|Apple
|[[5 nm process|5&nbsp;nm]]
|88&nbsp;mm<sup>2</sup>
|134,100,000
|-
|[[Apple M1]] (octa-core 64-bit ARM64 SoC, [[Single instruction, multiple data|SIMD]], caches)
|16,000,000,000<ref>{{Cite web|date=2020-11-10|title=Apple says new Arm-based M1 chip offers the 'longest battery life ever in a Mac'|url=https://www.theverge.com/2020/11/10/21558095/apple-silicon-m1-chip-arm-macs-soc-charge-power-efficiency-mobile-processor/|access-date=2020-11-11|website=The Verge|language=en-US}}</ref>
|2020
|Apple
|[[5 nm process|5&nbsp;nm]]
|119&nbsp;mm<sup>2</sup>
|134,500,000
|-
|[[HiSilicon#Kirin 9000 5G/4G and Kirin 9000E|HiSilicon Kirin 9000]]
|15,300,000,000<br><ref>{{Cite web |last=Ikoba |first=Jed John |date=2020-10-23 |title=Multiple benchmark tests rank the Kirin 9000 as one of the most-powerful chipset yet |url=https://www.gizmochina.com/2020/10/23/multiple-benchmark-tests-rank-the-kirin-9000-as-one-of-the-most-powerful-chipset-yet/ |access-date=2020-11-14 |website=Gizmochina |language=en-US}}</ref><ref>{{Cite web |last=Frumusanu |first=Andrei |title=Huawei Announces Mate 40 Series: Powered by 15.3bn Transistors 5nm Kirin 9000 |url=https://www.anandtech.com/show/16156/huawei-announces-mate-40-series |access-date=2020-11-14 |website=www.anandtech.com}}</ref>
|2020
|Huawei
|[[5 nm process|5&nbsp;nm]]
|114&nbsp;mm<sup>2</sup>
|134,200,000
|-
|AMD [[Zen 3]] CCX (core complex unit: 8 cores, 32 MB L3 cache)
|4,080,000,000<ref name=zen3>{{Cite conference
 |first=Thomas
 |last=Burd
 |book-title=Proc. IEEE International Solid-State Circuits Conference
 |title=2.7 Zen3: The AMD 2nd-Generation 7nm x86-64 Microprocessor Core
 |pages=54–56
 |date=2022}}</ref>
|2020
|AMD
|7&nbsp;nm
|68&nbsp;mm<sup>2</sup>
|60,000,000
|-
|AMD [[Zen 3]] CCD (core complex die)
|4,150,000,000<ref name=zen3 />
|2020
|AMD
|7&nbsp;nm
|81&nbsp;mm<sup>2</sup>
|51,230,000
|-
|Core 11th gen [[Rocket Lake]] (8-core 64-bit, [[Single instruction, multiple data|SIMD]], large caches)
|6,000,000,000+ <ref>{{Cite web|title=For a long time, Intel once again named the number of transistors in the chip. There are supposed to be about 6 billion for Rocket Lake-S. Coffee Lake-S is supposed to have about 4 billion. The chip with eight cores is about 30 % bigger than the predecessor with ten core|url=https://twitter.com/aschilling/status/1371845970581975050|access-date=2021-03-16|website=twitter|language=en}}</ref>
|2021
|Intel
|14&nbsp;nm +++ [[14 nm process|14&nbsp;nm]]
|276&nbsp;mm<sup>2</sup><ref>{{Cite web|title=Intel's Core i7-11700K 'Rocket Lake' Delidded: A Big Die, Revealed|url=https://www.tomshardware.com/news/intel-rocket-lake-delidded|access-date=2021-03-16|website=tomshardware|date=March 12, 2021 |language=en}}</ref>
|37,500,000 or 21,800,000+ <ref>{{Cite web|title=Intel's 14nm density|url=https://www.techcenturion.com/7nm-10nm-14nm-fabrication|access-date=2019-11-26|website=www.techcenturion.com|date=November 26, 2019 |language=en}}</ref>
|-
|[[AMD Ryzen Mobile|AMD Ryzen 7 5800H]] (64-bit, [[Single instruction, multiple data|SIMD]], caches, I/O and GPU)
|10,700,000,000<ref>{{Cite web|title=AMD Ryzen 7 5800H Specs|url=https://www.techpowerup.com/cpu-specs/ryzen-7-5800h.c2368|access-date=2021-09-20|website=TechPowerUp|language=en}}</ref>
|2021
|AMD
|[[7 nm process|7&nbsp;nm]]
|180&nbsp;mm<sup>2</sup>
|59,440,000
|-
|[[Epyc|AMD Epyc 7763 (Milan)]] (64-core, 64-bit)
|?
|2021
|AMD
|7 & 12&nbsp;nm<br>([[TSMC]])
|1,064&nbsp;mm<sup>2</sup><br>(8×81+416)<ref>{{cite web|url=https://www.techpowerup.com/cpu-specs/epyc-7763.c2373|title=AMD Epyc 7763 specifications|date=August 2023 }}</ref>
|{{?}}
|-
|[[Apple A15]]
|15,000,000,000<br><ref>{{Cite web|last=Shankland|first=Stephen|title=Apple's A15 Bionic chip powers iPhone 13 with 15 billion transistors, new graphics and AI|url=https://www.cnet.com/tech/mobile/apples-a15-bionic-chip-powers-iphone-13-with-15-billion-transistors-new-graphics-and-ai/|access-date=2021-09-20|website=CNET|language=en}}</ref><ref>{{Cite web|title=Apple iPhone 13 Pro Teardown {{!}} TechInsights|url=https://www.techinsights.com/blog/teardown/apple-iphone-13-pro-teardown|access-date=2021-09-29|website=www.techinsights.com}}</ref>
|2021
|Apple
|[[5 nm process|5&nbsp;nm]]
|107.68&nbsp;mm<sup>2</sup>
|139,300,000
|-
|[[Apple M1 Pro and M1 Max|Apple M1 Pro]] (10-core, 64-bit)
|33,700,000,000<ref name="VentureBeat M1 Pro and Max" />
|2021
|Apple
|5&nbsp;nm
|245&nbsp;mm<sup>2</sup><ref name="AnandTech M1 Pro and Max">{{Cite web|title=Apple Announces M1 Pro & M1 Max: Giant New Arm SoCs with All-Out Performance|url=https://www.anandtech.com/show/17019/apple-announced-m1-pro-m1-max-giant-new-socs-with-allout-performance|access-date=2021-12-02|website=AnanadTech|language=en}}</ref>
|137,600,000
|-
|[[Apple M1 Pro and M1 Max|Apple M1 Max]] (10-core, 64-bit)
|57,000,000,000<br><ref name="BBC M1 Pro and Max" >{{cite news |title=Apple unveils new computer chips amid shortage |url=https://www.bbc.com/news/technology-58917992 |work=BBC News |date=19 October 2021}}</ref><ref name="VentureBeat M1 Pro and Max" >{{cite news |title=Apple unveils M1 Pro and M1 Max chips for latest MacBook Pro laptops |url=https://venturebeat.com/2021/10/18/apple-unveils-m1-pro-and-m1-max-chips-for-latest-macbook-pro-laptops/ |work=VentureBeat |date=18 October 2021}}</ref>
|2021
|Apple
|5&nbsp;nm
|420.2&nbsp;mm<sup>2</sup><ref name="m1_max_die_TI">{{cite web|title=Apple Joins 3D-Fabric Portfolio with M1 Ultra?|url=https://www.techinsights.com/blog/apple-joins-3d-fabric-portfolio-m1-ultra|website=TechInsights|access-date=2022-07-08}}</ref>
|135,600,000
|-
|[[Power10]] dual-chip module (30 SMT8 cores or 60 SMT4 cores)
|36,000,000,000<ref>{{cite web|url=https://www.anandtech.com/show/15985/hot-chips-2020-live-blog-ibms-power10-processor-on-samsung-7nm-1000am-pt|title=Hot Chips 2020 live blog|date=2020-08-17|website=AnandTech}}</ref>
|2021
|IBM
|7&nbsp;nm
|1,204&nbsp;mm<sup>2</sup>
|29,900,000
|-
|[[List of MediaTek processors#Dimensity 9000 Series|Dimensity 9000]] (ARM64 SoC)
|15,300,000,000<br><ref>{{cite web
|url=https://www.mediatek.com/blog/phantom-x2-series-5g-powered-by-mediatek-dimensity-9000
|title=Phantom X2 Series 5G powered by MediaTek Dimensity 9000
|website=Mediatek
|date=2022-12-12
}}</ref><ref>{{cite web
|url=https://www.mediatek.com/products/smartphones-2/mediatek-dimensity-9000
|title=MediaTek Dimensity 9000
|website=Mediatek
|date=2023-01-21
}}</ref>
|2021
|Mediatek
|[[5 nm process|4&nbsp;nm<br>(TSMC N4)]]
|{{?}}
|{{?}}
|-
|[[Apple A16]] (ARM64 SoC)
|16,000,000,000<br><ref>{{cite web
|url=https://www.notebookcheck.net/Apple-A16-Bionic-announced-for-the-iPhone-14-Pro-and-iPhone-14-Pro-Max.647967.0.html
|title=Apple A16 Bionic announced for the iPhone 14 Pro and iPhone 14 Pro Max
|website=NotebookCheck
|date=2022-09-07
}}</ref><ref>{{cite web
|url=https://www.cnet.com/tech/mobile/iphone-14-pro-and-pro-max-only-models-to-get-new-a16-chip/
|title=iPhone 14 Pro and Pro Max Only Models to Get New A16 Chip
|website=CNET
|date=2022-09-07
}}</ref><ref>{{cite web
|url=https://www.anandtech.com/print/17563/the-apple-2022-fall-iphone-event-live-blog-10am-pt-1700-utc
|title=The Apple 2022 Fall iPhone Event Live Blog
|website=AnandTech
|date=2022-09-07
}}</ref>
|2022
|Apple
|[[5 nm process|4&nbsp;nm]]
|{{?}}
|{{?}}
|-
|[[Apple M1 Ultra]] (dual-chip module, 2×10 cores)
|114,000,000,000<br><ref name="Apple M1 Ultra">{{cite web |title=Apple unveils M1 Ultra, the world's most powerful chip for a personal computer |url=https://www.apple.com/newsroom/2022/03/apple-unveils-m1-ultra-the-worlds-most-powerful-chip-for-a-personal-computer/ |website=Apple Newsroom |access-date=9 March 2022}}</ref><ref name="CNET M1 Ultra">{{cite news |last1=Shankland |first1=Stephen |title=Meet Apple's Enormous 20-Core M1 Ultra Processor, the Brains in the New Mac Studio Machine |url=https://www.cnet.com/tech/computing/m1-ultra-apple-just-unveiled-its-most-powerful-chip-yet/ |access-date=9 March 2022 |work=CNET |language=en}}</ref>
|2022
|Apple
|5&nbsp;nm
|840.5&nbsp;mm<sup>2</sup><ref name=m1_max_die_TI />
|135,600,000
|-
|[[Epyc|AMD Epyc 7773X (Milan-X)]] (multi-chip module, 64 cores, 768 MB L3 cache)
|26,000,000,000 + Milan<ref name=milanx_at>{{cite web|url=https://www.anandtech.com/print/17323/amd-releases-milan-x-cpus-with-3d-vcache-epyc-7003|title=AMD releases Milan-X CPUs|website=AnandTech|date=2022-03-21}}</ref>
|2022
|AMD
|7 & 12&nbsp;nm<br>([[TSMC]])
|1,352&nbsp;mm<sup>2</sup><br>(Milan + 8×36)<ref name=milanx_at />
|{{?}}
|-
|[[IBM Telum (microprocessor)|IBM Telum]] dual-chip module (2×8 cores, 2×256 MB cache)
|45,000,000,000<br><ref>{{cite web|url=https://hc33.hotchips.org/assets/program/conference/day1/HC2021.C1.3%20IBM%20Cristian%20Jacobi%20Final.pdf|title=IBM Telum Hot Chips slide deck|date=2021-08-23}}</ref><ref>{{cite web|url=https://newsroom.ibm.com/2022-04-05-Announcing-IBM-z16-Real-time-AI-for-Transaction-Processing-at-Scale-and-Industrys-First-Quantum-Safe-System|title=IBM z16 announcement|date=2022-04-05}}</ref>
|2022
|IBM
|7&nbsp;nm (Samsung)
|1,060&nbsp;mm<sup>2</sup>
|42,450,000
|-
|[[Apple M2]] (deca-core 64-bit ARM64 SoC, [[Single instruction, multiple data|SIMD]], caches)
|20,000,000,000<ref>{{Cite web|date=2022-06-06|title=Apple unveils M2, taking the breakthrough performance and capabilities of M1 even further|url=https://www.apple.com/newsroom/2022/06/apple-unveils-m2-with-breakthrough-performance-and-capabilities/|website=Apple}}</ref>
|2022
|Apple
|[[5 nm process|5&nbsp;nm]]
|{{?}}
|{{?}}
|-
|[[List of MediaTek processors#Dimensity 9000 Series|Dimensity 9200]] (ARM64 SoC)
|17,000,000,000<br><ref>{{cite web
|url=https://www.notebookcheck.net/MediaTek-Dimensity-9200-New-flagship-chipset-debuts-with-ARM-Cortex-X3-CPU-and-Immortalis-G715-GPU-cores-built-around-TSMC-N4P-node.667041.0.html
|title=MediaTek Dimensity 9200: New flagship chipset debuts with ARM Cortex-X3 CPU and Immortalis-G715 GPU cores built around TSMC N4P node
|website=NotebookCheck
|date=2022-11-08
}}</ref><ref>{{cite web
|url=https://www.mediatek.com/products/smartphones-2/mediatek-dimensity-9200
|title=Dimensity 9200 specs
|website=Mediatek
|date=2022-11-08
}}</ref><ref>{{cite web
|url=https://i.mediatek.com/dimensity-9200
|title=Dimensity 9200 presentation
|website=Mediatek
|date=2022-11-08
}}</ref>
|2022
|Mediatek
|[[5 nm process|4&nbsp;nm<br>(TSMC N4P)]]
|{{?}}
|{{?}}
|-
|[[Qualcomm Snapdragon|Qualcomm Snapdragon 8 Gen 2]] (octa-core ARM64 "mobile SoC", [[Single instruction, multiple data|SIMD]], caches)
|16,000,000,000
|2022
|Qualcomm
|4&nbsp;nm
|268&nbsp;mm<sup>2</sup>
|59,701,492
|-
|AMD [[Zen 4#Genoa|EPYC Genoa (4th gen/9004 series)]] 13-chip module (up to 96 cores and 384 MB (L3) + 96 MB (L2) cache)<ref>{{cite web
 |url=https://www.servethehome.com/amd-epyc-genoa-gaps-intel-xeon-in-stunning-fashion/
 |title=AMD EPYC Genoa Gaps Intel Xeon in Stunning Fashion
 |website=ServeTheHome
 |date=2022-11-10
}}</ref>
|90,000,000,000<br><ref>{{cite web
 |url=https://appuals.com/amd-zettaflop-plans/
 |title=AMD Aims to Break the ZettaFLOP Barrier by 2035, Lays Down Next-Gen Plans to Resolve Efficiency Problems
 |website=Appuals
 |date=2023-02-21
}}</ref><ref>{{cite web
 |url=https://wccftech.com/amd-lays-the-path-to-zettascale-computing-talks-cpu-gpu-performance-plus-efficiency-trends-next-gen-chiplet-packaging-more/
 |title=AMD Lays The Path To Zettascale Computing: Talks CPU & GPU Performance Plus Efficiency Trends, Next-Gen Chiplet Packaging & More
 |website=WCCFtech
 |date=2023-02-20
}}</ref>
|2022
|AMD
|5&nbsp;nm (CCD)<br>6&nbsp;nm (IOD)
|1,263.34&nbsp;mm<sup>2</sup><br>12×72.225 (CCD)<br>396.64 (IOD)<br><ref>
{{cite web
 |url=https://wccftech.com/amd-epyc-genoa-zen-4-server-cpus-and-sp5-lga-6096-server-platform-details-leaked/
 |title=AMD EPYC Genoa & SP5 Platform Leaked – 5nm Zen 4 CCD Measures Roughly 72mm, 12 CCD Package at 5428mm2, Up To 700W Peak Socket Power
 |website=WCCFtech
 |date=2021-08-17
}}</ref><ref>
{{cite web
 |url=https://www.hardwaretimes.com/leaked-amd-epyc-genoa-docs-reveal-96-cores-max-tdp-of-700w-and-zen-4-chiplet-dimensions/
 |title=Leaked AMD Epyc Genoa Docs Reveal 96 Cores, Max TDP of 700W, and Zen 4 Chiplet Dimensions
 |website=HardwareTimes
 |date=2021-08-17
|last1=Syed
 |first1=Areej
 }}</ref>
|71,240,000
|-
|[[HiSilicon#Kirin 9000s|HiSilicon Kirin 9000s]]
|9,510,000,000<ref>{{Cite web|url=https://inf.news/en/news/fe8aae471cb54698f4ddac2d2baf1abd.html|title=Kirin 9000S has about 6 billion fewer transistors than Kirin 9000, but its performance is stronger! How did you do it?|website=iNews|date=September 13, 2023 |language=en-US|access-date=2023-09-24}}</ref>
|2023
|Huawei
|[[7 nm process|7&nbsp;nm]]
|107&nbsp;mm<sup>2</sup>
|107,690,000
|-
|[[Apple M4]] (deca-core 64-bit ARM64 SoC, [[Single instruction, multiple data|SIMD]], caches)
|28,000,000,000<ref name="anandtech.com2024">{{Cite web|date=2024-05-07|title=Apple Announces M4 SoC: Latest and Greatest Starts on 2024 iPad Pro|url=https://www.anandtech.com/show/21387/apple-announces-m4-soc-latest-and-greatest-starts-on-ipad-pro/|website=Anandtech}}</ref>
|2024
|Apple
|[[3 nm process|3&nbsp;nm]]
|{{?}}
|{{?}}
|-
|[[Apple M3]] (octa-core 64-bit ARM64 SoC, [[Single instruction, multiple data|SIMD]], caches)
|25,000,000,000<ref name="arstechnica.com">{{Cite web|date=2023-10-31|title=Apple introduces new M3 chip lineup, starting with the M3, M3 Pro, and M3 Max|url=https://arstechnica.com/gadgets/2023/10/everything-to-know-about-apples-new-m3-m3-pro-and-m3-max-processors/|website=Arstechnica}}</ref>
|2023
|Apple
|[[3 nm process|3&nbsp;nm]]
|{{?}}
|{{?}}
|-
|[[Apple M3 Pro]] (dodeca-core 64-bit ARM64 SoC, [[Single instruction, multiple data|SIMD]], caches)
|37,000,000,000<ref name="arstechnica.com"/>
|2023
|Apple
|[[3 nm process|3&nbsp;nm]]
|{{?}}
|{{?}}
|-
|[[Apple M3 Max]] (16-core 64-bit ARM64 SoC, [[Single instruction, multiple data|SIMD]], caches)
|92,000,000,000<ref name="arstechnica.com"/>
|2023
|Apple
|[[3 nm process|3&nbsp;nm]]
|{{?}}
|{{?}}
|-
|[[Apple A17]]
|19,000,000,000<br><ref>{{Cite web|last=Goldman|first=Joshua|title=Apple A17 Pro Chip: The New Brain Inside iPhone 15 Pro, Pro Max|url=https://www.cnet.com/tech/mobile/apple-a17-pro-chip-the-new-brain-inside-iphone-15-pro/|access-date=2023-09-12|website=CNET|language=en}}</ref>
|2023
|Apple
|[[3 nm process|3&nbsp;nm]]
|103.8&nbsp;mm<sup>2</sup>
|183,044,315
|-

|[[Sapphire Rapids]] quad-chip module (up to 60 cores and 112.5 MB of cache)<ref>{{cite web
 |url=https://www.servethehome.com/4th-gen-intel-xeon-scalable-sapphire-rapids-leaps-forward/
 |title=4th Gen Intel Xeon Scalable Sapphire Rapids Leaps Forward
 |website=ServeTheHome
 |date=2023-01-10
}}</ref>
|44,000,000,000–<br>48,000,000,000<ref>{{cite web
 |url=https://www.hardwareluxx.de/index.php/news/hardware/prozessoren/58175-isscc-2022-wie-vier-dies-zu-einem-monolithischen-sapphire-rapids-werden.html
 |title=Wie vier Dies zu einem "monolithischen" Sapphire Rapids werden
 |website=hardwareLUXX
 |date=2022-02-21
}}</ref>
|2023
|Intel
|[[10 nm process|10&nbsp;nm ESF]] (Intel 7)
|1,600&nbsp;mm<sup>2</sup>
|27,500,000–<br>30,000,000
|-
|[[Apple M2 Pro]] (12-core 64-bit ARM64 SoC, [[Single instruction, multiple data|SIMD]], caches)
|40,000,000,000<ref name=m2promax>{{cite press release
 |url=https://www.apple.com/newsroom/2023/01/apple-unveils-m2-pro-and-m2-max-next-generation-chips-for-next-level-workflows/
 |title=Apple unveils M2 Pro and M2 Max: next-generation chips for next-level workflows
 |website=Apple
 |date=2023-01-17
}}</ref>
|2023
|Apple
|[[5 nm process|5&nbsp;nm]]
|{{?}}
|{{?}}
|-
|[[Apple M2 Max]] (12-core 64-bit ARM64 SoC, [[Single instruction, multiple data|SIMD]], caches)
|67,000,000,000<ref name=m2promax />
|2023
|Apple
|[[5 nm process|5&nbsp;nm]]
|{{?}}
|{{?}}
|-
|[[Apple M2 Ultra]] (two M2 Max dies)
|134,000,000,000<ref name=m2ultra>{{cite press release
 |date=2023-06-05
 |title=Apple introduces M2 Ultra
 |url=https://www.apple.com/newsroom/2023/06/apple-introduces-m2-ultra/
 |publisher=Apple
}}</ref>
|2023
|Apple
|[[5 nm process|5&nbsp;nm]]
|{{?}}
|{{?}}
|-
|AMD [[Zen 4#Server|Epyc Bergamo (4th gen/97X4 series)]] 9-chip module (up to 128 cores and 256 MB (L3) + 128 MB (L2) cache)
|82,000,000,000<ref>{{cite web
 |url=https://www.servethehome.com/amd-epyc-bergamo-launched-128-cores-per-socket-and-1024-threads-per-1u/
 |title=AMD EPYC Bergamo Launched 128 Cores Per Socket and 1024 Threads Per 1U
 |website=ServeTheHome
 |date=2023-06-13
}}</ref>
|2023
|AMD
|5&nbsp;nm (CCD)<br>6&nbsp;nm (IOD)
|{{?}}
|{{?}}
|-
|[[AMD Instinct]] MI300A (multi-chip module, 24 cores, 128&nbsp;GB GPU memory + 256&nbsp;MB (LLC/L3) cache)
|146,000,000,000<ref>{{cite web
|url=https://www.amd.com/en/products/accelerators/instinct/mi300/mi300a.html
 |title=AMD Instinct MI300A Accelerators
 |website=AMD
 |access-date=January 14, 2024
}}</ref><ref>{{cite web
 |last=Alcorn
 |first=Paul
 |url=https://www.tomshardware.com/pc-components/cpus/amd-unveils-instinct-mi300x-gpu-and-mi300a-apu-claims-up-to-16x-lead-over-nvidias-competing-gpus
 |title=AMD unveils Instinct MI300X GPU and MI300A APU, claims up to 1.6X lead over Nvidia's competing GPUs
 |website=Tom's Hardware
 |date=December 6, 2023
 |access-date=January 14, 2024
}}</ref>
|2023
|AMD
|5&nbsp;nm (CCD, GCD)<br>6&nbsp;nm (IOD)
|1,017&nbsp;mm<sup>2</sup>
|144,000,000
|-
| RV32-WUJI: 3-atom-thick molybdenum disulfide on sapphire; [[RISC-V]] architecture
| 5931<ref>
[https://www.intellinews.com/china-creates-world-s-thinnest-chip-with-5931-transistors-378131/ "China creates world's thinnest chip with 5931 transistors"].
2025.
</ref>
| 2025
| {{?}}
| 3000&nbsp;nm
| {{?}}
| {{?}}
|-
![[Microprocessor|Processor]]
!Transistor count
!Year
!Designer
![[Semiconductor device fabrication|Process]]<br />([[Nanometre|nm]])
!Area ([[Millimetre|mm]]<sup>2</sup>)
!Transistor<br>density<br>(tr./mm<sup>2</sup>)
|}

=== GPUs ===
A [[graphics processing unit]] (GPU) is a specialized electronic circuit designed to rapidly manipulate and alter memory to accelerate the building of images in a frame buffer intended for output to a display.

The designer refers to the [[technology company]] that designs the logic of the [[integrated circuit]] chip (such as [[Nvidia]] and [[AMD]]). The manufacturer ("Fab.") refers to the [[semiconductor company]] that fabricates the chip using its [[semiconductor manufacturing process]] at a [[Semiconductor fabrication plant|foundry]] (such as [[TSMC]] and [[Samsung Semiconductor]]). The transistor count in a chip is dependent on a manufacturer's fabrication process, with smaller [[semiconductor node]]s typically enabling higher transistor density and thus higher transistor counts.

The [[random-access memory]] (RAM) that comes with GPUs (such as [[VRAM]], [[SGRAM]] or [[High Bandwidth Memory|HBM]]) greatly increases the total transistor count, with the [[computer memory|memory]] typically accounting for the majority of transistors in a [[graphics card]]. For example, [[Nvidia]]'s [[Nvidia Tesla|Tesla P100]] has 15{{nbsp}}billion [[FinFET]]s ([[16&nbsp;nm]]) in the GPU in addition to 16{{nbsp}}[[Gibibyte|GB]] of [[HBM2]] memory, totaling about 150{{nbsp}}billion [[MOSFET]]s on the graphics card.<ref>{{Cite web|url=https://www.theregister.co.uk/2016/04/05/nvidia_gtc_telsa_p100_pascal/|title=Nvidia's Tesla P100 has 15 billion transistors, 21TFLOPS|last=Williams|first=Chris|website=www.theregister.co.uk|access-date=2019-08-12}}</ref> The following table does not include the memory. For memory transistor counts, see the ''[[#Memory|Memory]]'' section below.
{{Row hover highlight}}
{| class="wikitable sortable mw-datatable" style="font-size:96%;"
|-
! Processor
! data-sort-type="number" | Transistor count
! Year
! Designer(s)
! [[Semiconductor manufacturer|Fab(s)]]
! data-sort-type="number" | [[Semiconductor device fabrication|Process]]
! data-sort-type="number" | Area
! data-sort-type="number" | Transistor<br>density<br>(tr./mm<sup>2</sup>)
! class="unsortable"| {{Abbr|Ref|Reference(s)}}
|-
|[[NEC μPD7220|μPD7220 GDC]]
|40,000
|1982
|[[NEC]]
|[[NEC]]
|[[6 μm process|5,000&nbsp;nm]]
|{{?}}
|{{?}}
|<ref>{{cite web |title=Famous Graphics Chips: NEC μPD7220 Graphics Display Controller |url=https://www.computer.org/publications/tech-news/chasing-pixels/famous-graphics-chips |website=[[IEEE Computer Society]] |publisher=[[Institute of Electrical and Electronics Engineers]] |date=August 22, 2018 |access-date=21 June 2019}}</ref>
|-
|ARTC HD63484
|60,000
|1984
|[[Hitachi]]
|[[Hitachi]]
|{{?}}
|{{?}}
|{{?}}
|<ref>{{cite web |title=GPU History: Hitachi ARTC HD63484. The second graphics processor. |url=https://www.computer.org/publications/tech-news/chasing-pixels/gpu-history-hitachi-artc-hd63484 |website=[[IEEE Computer Society]] |date=October 7, 2018 |publisher=[[Institute of Electrical and Electronics Engineers]] |access-date=21 June 2019}}</ref>
|-
|[[Original Chip Set#Agnus|CBM Agnus]]
|21,000
|1985
|[[Commodore International|Commodore]]
|[[MOS Technology|CSG]]
|5,000&nbsp;nm
|{{?}}
|{{?}}
|<ref>{{cite web |title=Big Book of Amiga Hardware |url=https://bboah.com/index.php?action=artikel&cat=51&id=2174}}</ref><ref>{{cite book |title=MOS Technology Agnus |isbn=978-5511916842 |last1=Russell |first1=Jesse |last2=Cohn |first2=Ronald |date=May 2012 |publisher=Book on Demand }}</ref>
|-
|[[Sega Genesis/Mega Drive|YM7101 VDP]]
|100,000
|1988
|[[Yamaha Corporation|Yamaha]], [[Sega]]
|[[Yamaha Corporation|Yamaha]]
|{{?}}
|{{?}}
|{{?}}
|<ref name="klingerphotography">{{cite web |title=30 Years of Console Gaming |url=https://klingerphotography.com/wp/2017/08/20/30-years-console-gaming/ |website=Klinger Photography |access-date=19 June 2019 |date=20 August 2017}}</ref>
|-
|[[Atari Jaguar|Tom & Jerry]]
|750,000
|1993
|[[Flare Technology|Flare]]
|[[IBM]]
|{{?}}
|{{?}}
|{{?}}
|<ref name="klingerphotography"/>
|-
|[[Sega Saturn|VDP1]]
|1,000,000
|1994
|Sega
|Hitachi
|[[600 nanometer|500&nbsp;nm]]
|{{?}}
|{{?}}
|<ref>{{cite web |title=Sega Saturn |url=https://github.com/mamedev/mame/blob/master/src/mame/drivers/saturn.cpp |website=[[MAME]] |access-date=18 July 2019}}</ref>
|-
|[[PlayStation technical specifications|Sony GPU]]
|1,000,000
|1994
|[[Toshiba]]
|[[LSI Corporation|LSI]]
|500&nbsp;nm
|{{?}}
|{{?}}
|<ref>{{cite news |title=ASIC CHIPS ARE INDUSTRY'S GAME WINNERS |url=https://www.washingtonpost.com/archive/business/1995/09/18/asic-chips-are-industrys-game-winners/50bcb622-e890-4d46-803f-39e007c489ca/ |access-date=19 June 2019 |newspaper=[[The Washington Post]] |date=18 September 1995}}</ref><ref>{{cite web |title=Is it Time to Rename the GPU? |url=https://www.computer.org/publications/tech-news/chasing-pixels/is-it-time-to-rename-the-gpu |work=Jon Peddie Research |publisher=[[IEEE Computer Society]] |date=2018-07-09 |access-date=19 June 2019}}</ref><ref name="patpend">{{cite web | url=http://patpend.net/technical/psx/LSI.htm | title=FastForward Sony Taps LSI Logic for PlayStation Video Game CPU Chip | publisher=FastForward | access-date=29 January 2014}}</ref>
|-
|[[NV1]]
|1,000,000
|1995
|[[Nvidia]], Sega
|[[STMicroelectronics|SGS]]
|500&nbsp;nm
|90&nbsp;mm<sup>2</sup>
|11,000
|
|-
|[[Reality Coprocessor]]
|2,600,000
|1996
|[[Silicon Graphics|SGI]]
|NEC
|[[350&nbsp;nm]]
|81&nbsp;mm<sup>2</sup>
|32,100
|<ref name="rcp">{{cite web |title=Reality Co-Processor − The Power In Nintendo64 |url=http://www.hotchips.org/wp-content/uploads/hc_archives/hc09/3_Tue/HC9.S10/HC9.10.2.pdf |publisher=[[Silicon Graphics]] |date=August 26, 1997 |access-date=18 June 2019 |archive-date=May 19, 2020 |archive-url=https://web.archive.org/web/20200519051320/http://www.hotchips.org/wp-content/uploads/hc_archives/hc09/3_Tue/HC9.S10/HC9.10.2.pdf |url-status=dead }}</ref>
|-
|[[PowerVR]]
|1,200,000
|1996
|[[VideoLogic]]
|NEC
|350&nbsp;nm
|{{?}}
|{{?}}
|<ref>{{cite web |title=Imagination PowerVR PCX2 GPU |url=https://videocardz.net/gpu/imagination-powervr-pcx2/ |website=VideoCardz.net |access-date=19 June 2019}}</ref>
|-
|[[Voodoo Graphics]]
|1,000,000
|1996
|[[3dfx Interactive|3dfx]]
|[[TSMC]]
|500&nbsp;nm
|{{?}}
|{{?}}
|<ref name="pcgamer">{{cite magazine |last1=Lilly |first1=Paul |title=From Voodoo to GeForce: The Awesome History of 3D Graphics |url=https://www.pcgamer.com/from-voodoo-to-geforce-the-awesome-history-of-3d-graphics/ |magazine=[[PC Gamer]] |access-date=19 June 2019 |date=19 May 2009}}</ref><ref name="vintage3d">{{cite web |title=3D accelerator database |url=http://vintage3d.org/dbn.php |website=Vintage 3D |access-date=21 July 2019}}</ref>
|-
|[[Voodoo Rush]]
|1,000,000
|1997
|3dfx
|TSMC
|500&nbsp;nm
|{{?}}
|{{?}}
|<ref name="pcgamer"/><ref name="vintage3d"/>
|-
|[[NV3]]
|3,500,000
|1997
|[[Nvidia]]
|SGS, TSMC
|350&nbsp;nm
|90&nbsp;mm<sup>2</sup>
|38,900
|<ref>{{cite web |title=RIVA128 Datasheet |url=http://www.datasheetcatalog.com/datasheets_pdf/R/I/V/A/RIVA128.shtml |publisher=[[STMicroelectronics|SGS Thomson Microelectronics]] |access-date=21 July 2019}}</ref><ref name="techspot">{{cite web |last1=Singer |first1=Graham |title=History of the Modern Graphics Processor, Part 2 |url=https://www.techspot.com/article/653-history-of-the-gpu-part-2/ |website=TechSpot |date=April 3, 2013 |access-date=21 July 2019}}</ref>
|-
|[[i740]]
|3,500,000
|1998
|[[Intel]], [[Real3D]]
|[[Real3D]]
|350&nbsp;nm
|{{?}}
|{{?}}
| rowspan="3" |<ref name="pcgamer"/><ref name="vintage3d"/>
|-
|[[Voodoo 2]]
|4,000,000
|1998
|3dfx
|TSMC
|350&nbsp;nm
|{{?}}
|{{?}}
|-
|[[Voodoo Rush]]
|4,000,000
|1998
|3dfx
|TSMC
|350&nbsp;nm
|{{?}}
|{{?}}
|-
|[[Riva TNT|NV4]]
|7,000,000
|1998
|Nvidia
|TSMC
|350&nbsp;nm
|90&nbsp;mm<sup>2</sup>
|78,000
|<ref name="pcgamer"/><ref name="techspot"/>
|-
|[[PowerVR#Series2 (NEC)|PowerVR2 CLX2]]
|10,000,000
|1998
|VideoLogic
|NEC
|[[250 nanometer|250&nbsp;nm]]
|116&nbsp;mm<sup>2</sup>
|86,200
|<ref name="bit-tech">{{cite web |title=Remembering the Sega Dreamcast |url=https://bit-tech.net/reviews/gaming/retro/remembering-the-sega-dreamcast/3/ |website=[[Bit-Tech]] |access-date=18 June 2019 |date=September 29, 2009}}</ref><ref>{{cite news |last1=Weinberg |first1=Neil |title=Comeback kid |url=https://www.forbes.com/global/1998/0907/0111082a.html |access-date=19 June 2019 |work=[[Forbes]] |date=September 7, 1998}}</ref><ref>{{cite journal |last1=Charles |first1=Bertie |title=Sega's New Dimension |journal=[[Forbes]] |date=1998 |volume=162 |issue=5–9 |page=206 |url=https://books.google.com/books?id=rCO8AAAAIAAJ |publisher=Forbes Incorporated |quote=The chip, etched in 0.25-micron detail — state-of-the-art for graphics processors — fits 10 million transistors}}</ref><ref name="Unified">{{cite journal|last1=Hagiwara|first1=Shiro|last2=Oliver|first2=Ian|title=Sega Dreamcast: Creating a Unified Entertainment World|journal=[[IEEE Micro]]|volume=19|number=6|date=November–December 1999|pages=29–35|publisher=[[IEEE Computer Society]]|url=http://computer.org/micro/articles/dreamcast_2.htm|archive-url=https://archive.today/20000823204755/http://computer.org/micro/articles/dreamcast_2.htm|url-status=dead|archive-date=2000-08-23|access-date=27 June 2019|doi=10.1109/40.809375|url-access=subscription}}</ref>
|-
|[[PowerVR#Series2 (NEC)|PowerVR2 PMX1]]
|6,000,000
|1999
|VideoLogic
|NEC
|250&nbsp;nm
|{{?}}
|{{?}}
|<ref>{{cite web |title=VideoLogic Neon 250 4MB |url=https://videocardz.net/videologic-neon-250-4mb/ |website=VideoCardz.net |access-date=19 June 2019}}</ref>
|-
|[[Rage 128]]
|8,000,000
|1999
|[[ATI Technologies|ATI]]
|TSMC, [[United Microelectronics Corporation|UMC]]
|250&nbsp;nm
|70&nbsp;mm<sup>2</sup>
|114,000
|<ref name="vintage3d"/>
|-
|[[Voodoo 3]]
|8,100,000
|1999
|3dfx
|TSMC
|250&nbsp;nm
|{{?}}
|{{?}}
|<ref>{{cite news |last1=Shimpi |first1=Anand Lal |title=Fall Comdex '98 Coverage |url=https://www.anandtech.com/show/103/6 |access-date=19 June 2019 |work=[[AnandTech]] |date=November 21, 1998}}</ref>
|-
|[[Graphics Synthesizer]]
|43,000,000
|1999
|[[Sony]], Toshiba
|[[Sony]], [[Toshiba]]
|[[180&nbsp;nm]]
|279&nbsp;mm<sup>2</sup>
|154,000
|<ref name="pcper2005"/><ref name="sony2003">{{cite news |title=EMOTION ENGINE AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION BECOME ONE CHIP |url=https://www.sie.com/content/dam/corporate/en/corporate/release/pdf/030421be.pdf |access-date=26 June 2019 |publisher=[[Sony]] |date=April 21, 2003}}</ref><ref name="hennessy"/><ref name="Diefendorff"/>
|-
|[[NV5]]
|15,000,000
|1999
|Nvidia
|TSMC
|250&nbsp;nm
|90&nbsp;mm<sup>2</sup>
|167,000
|<ref name="vintage3d"/>
|-
|[[NV10]]
|17,000,000
|1999
|Nvidia
|TSMC
|220&nbsp;nm
|111&nbsp;mm<sup>2</sup>
|153,000
|<ref>{{cite web |title=NVIDIA NV10 A3 GPU Specs |url=https://www.techpowerup.com/gpu-specs/nvidia-nv10-a3.g165 |website=TechPowerUp |access-date=19 June 2019}}</ref><ref name="techspot"/>
|-
|[[NV11]]
|20,000,000
|2000
|Nvidia
|TSMC
|180&nbsp;nm
|65&nbsp;mm<sup>2</sup>
|308,000
|<ref name="vintage3d"/>
|-
|[[NV15]]
|25,000,000
|2000
|Nvidia
|TSMC
|180&nbsp;nm
|81&nbsp;mm<sup>2</sup>
|309,000
|<ref name="vintage3d"/>
|-
|[[Voodoo 4]]
|14,000,000
|2000
|3dfx
|TSMC
|220&nbsp;nm
|{{?}}
|{{?}}
|<ref name="pcgamer"/><ref name="vintage3d"/>
|-
|[[Voodoo 5]]
|28,000,000
|2000
|3dfx
|TSMC
|220&nbsp;nm
|{{?}}
|{{?}}
|<ref name="pcgamer"/><ref name="vintage3d"/>
|-
|[[Radeon R100|R100]]
|30,000,000
|2000
|ATI
|TSMC
|180&nbsp;nm
|97&nbsp;mm<sup>2</sup>
|309,000
|<ref name="vintage3d"/>
|-
|[[GameCube technical specifications|Flipper]]
|51,000,000
|2000
|[[ArtX]]
|NEC
|180&nbsp;nm
|106&nbsp;mm<sup>2</sup>
|481,000
|<ref name="pcper2005"/><ref>{{cite web|url=https://ign.com/articles/2000/11/04/gamecube-versus-playstation-2|title=Gamecube Versus PlayStation 2|author=IGN Staff|date=November 4, 2000|work=IGN|access-date=November 22, 2015}}</ref>
|-
|[[PowerVR#Series3 (STMicro)|PowerVR3 KYRO]]
|14,000,000
|2001
|[[Imagination Technologies|Imagination]]
|[[STMicroelectronics|ST]]
|250&nbsp;nm
|rowspan="2" | {{?}}
|rowspan="2" | {{?}}
|rowspan="2" | <ref name="pcgamer"/><ref name="vintage3d"/>
|-
|[[PowerVR#Series3 (STMicro)|PowerVR3 KYRO II]]
|15,000,000
|2001
|Imagination
|ST
|180&nbsp;nm
|-
|[[Xbox technical specifications|NV2A]]
|60,000,000
|2001
|Nvidia
|TSMC
|[[130 nanometer|150&nbsp;nm]]
|{{?}}
|{{?}}
|<ref name="pcgamer"/><ref>{{cite web |title=NVIDIA NV2A GPU Specs |url=https://www.techpowerup.com/gpu-specs/nvidia-nv2a.g401 |website=TechPowerUp |access-date=21 July 2019}}</ref>
|-
|[[NV20]]
|57,000,000
|2001
|Nvidia
|TSMC
|150&nbsp;nm
|128&nbsp;mm<sup>2</sup>
|445,000
| rowspan="16" |<ref name="vintage3d"/>
|-
|[[NV25]]
|63,000,000
|2002
|Nvidia
|TSMC
|150&nbsp;nm
|142&nbsp;mm<sup>2</sup>
|444,000
|-
|[[NV25|NV28]]
|36,000,000
|2002
|Nvidia
|TSMC
|150&nbsp;nm
|101&nbsp;mm<sup>2</sup>
|356,000
|-
|[[NV25|NV17/18]]
|29,000,000
|2002
|Nvidia
|TSMC
|150&nbsp;nm
|65&nbsp;mm<sup>2</sup>
|446,000
|-
|[[R200]]
|60,000,000
|2001
|ATI
|TSMC
|150&nbsp;nm
|68&nbsp;mm<sup>2</sup>
|882,000
|-
|[[R300]]
|107,000,000
|2002
|ATI
|TSMC
|150&nbsp;nm
|218&nbsp;mm<sup>2</sup>
|490,800
|-
|R360
|117,000,000
|2003
|ATI
|TSMC
|150&nbsp;nm
|218&nbsp;mm<sup>2</sup>
|536,700
|-
|[[GeForce FX series|NV34]]
|45,000,000
|2003
|Nvidia
|TSMC
|150&nbsp;nm
|124&nbsp;mm<sup>2</sup>
|363,000
|-
|[[GeForce FX series|NV34b]]
|45,000,000
|2004
|Nvidia
|TSMC
|140&nbsp;nm
|91&nbsp;mm<sup>2</sup>
|495,000
|-
|[[GeForce FX series|NV30]]
|125,000,000
|2003
|Nvidia
|TSMC
|[[130&nbsp;nm]]
|199&nbsp;mm<sup>2</sup>
|628,000
|-
|[[GeForce FX series|NV31]]
|80,000,000
|2003
|Nvidia
|TSMC
|[[130&nbsp;nm]]
|121&nbsp;mm<sup>2</sup>
|661,000
|-
|[[GeForce FX series|NV35/38]]
|135,000,000
|2003
|Nvidia
|TSMC
|[[130&nbsp;nm]]
|207&nbsp;mm<sup>2</sup>
|652,000
|-
|[[GeForce FX series|NV36]]
|82,000,000
|2003
|Nvidia
|IBM
|[[130&nbsp;nm]]
|133&nbsp;mm<sup>2</sup>
|617,000
|-
|R480
|160,000,000
|2004
|ATI
|TSMC
|130&nbsp;nm
|297&nbsp;mm<sup>2</sup>
|538,700
|-
|[[NV40]]
|222,000,000
|2004
|Nvidia
|IBM
|130&nbsp;nm
|305&nbsp;mm<sup>2</sup>
|727,900
|-
|[[NV40|NV44]]
|75,000,000
|2004
|Nvidia
|IBM
|130&nbsp;nm
|110&nbsp;mm<sup>2</sup>
|681,800
|-
|[[Curie (microarchitecture)|NV41]]
|222,000,000
|2005
|Nvidia
|TSMC
|110&nbsp;nm
|225&nbsp;mm<sup>2</sup>
|986,700
| rowspan="4" |<ref name="vintage3d"/>
|-
|[[Curie (microarchitecture)|NV42]]
|198,000,000
|2005
|Nvidia
|TSMC
|110&nbsp;nm
|222&nbsp;mm<sup>2</sup>
|891,900
|-
|[[Curie (microarchitecture)|NV43]]
|146,000,000
|2005
|Nvidia
|TSMC
|110&nbsp;nm
|154&nbsp;mm<sup>2</sup>
|948,100
|-
|[[GeForce 7 series|G70]]
|303,000,000
|2005
|Nvidia
|TSMC, [[Chartered Semiconductor Manufacturing|Chartered]]
|110&nbsp;nm
|333&nbsp;mm<sup>2</sup>
|909,900
|-
|[[Xenos (graphics chip)|Xenos]]
|232,000,000
|2005
|ATI
|TSMC
|[[90&nbsp;nm]]
|182&nbsp;mm<sup>2</sup>
|1,275,000
|<ref>{{cite web |title=ATI Xenos GPU Specs |url=https://www.techpowerup.com/gpu-specs/ati-xenos.g424 |website=TechPowerUp |access-date=21 June 2019}}</ref><ref>{{cite news |last1=International |first1=GamesIndustry |title=TSMC to manufacture X360 GPU |url=https://www.eurogamer.net/articles/news140705tsmc |access-date=22 August 2006 |work=[[Eurogamer]] |date=14 July 2005}}</ref>
|-
|[[RSX Reality Synthesizer]]
|300,000,000
|2005
|Nvidia, Sony
|[[Sony]]
|90&nbsp;nm
|186&nbsp;mm<sup>2</sup>
|1,613,000
|<ref>{{cite web |title=NVIDIA Playstation 3 RSX 65nm Specs |url=https://www.techpowerup.com/gpu-specs/playstation-3-rsx-65nm.c1682 |website=TechPowerUp |access-date=21 June 2019}}</ref><ref name="shrink_plan">{{cite web|publisher=Edge Online|date=2008-06-26|title=PS3 Graphics Chip Goes 65nm in Fall|url=http://www.edge-online.com/news/ps3-graphics-chip-goes-65nm-fall/|archive-url=https://web.archive.org/web/20080725024026/http://www.edge-online.com/news/ps3-graphics-chip-goes-65nm-fall/|url-status=dead|archive-date=2008-07-25}}</ref>
|-
|[[R520]]
|321,000,000
|2005
|ATI
|TSMC
|90&nbsp;nm
|288&nbsp;mm<sup>2</sup>
|1,115,000
| rowspan="12" |<ref name="vintage3d"/>
|-
|[[R520|RV530]]
|157,000,000
|2005
|ATI
|TSMC
|90&nbsp;nm
|150&nbsp;mm<sup>2</sup>
|1,047,000
|-
|[[R520|RV515]]
|107,000,000
|2005
|ATI
|TSMC
|90&nbsp;nm
|100&nbsp;mm<sup>2</sup>
|1,070,000
|-
|[[R580]]
|384,000,000
|2006
|ATI
|TSMC
|90&nbsp;nm
|352&nbsp;mm<sup>2</sup>
|1,091,000
|-
|[[Curie (microarchitecture)|G71]]
|278,000,000
|2006
|Nvidia
|TSMC
|90&nbsp;nm
|196&nbsp;mm<sup>2</sup>
|1,418,000
|-
|[[Curie (microarchitecture)|G72]]
|112,000,000
|2006
|Nvidia
|TSMC
|90&nbsp;nm
|81&nbsp;mm<sup>2</sup>
|1,383,000
|-
|[[Curie (microarchitecture)|G73]]
|177,000,000
|2006
|Nvidia
|TSMC
|90&nbsp;nm
|125&nbsp;mm<sup>2</sup>
|1,416,000
|-
|[[G80]]
|681,000,000
|2006
|Nvidia
|TSMC
|90&nbsp;nm
|480&nbsp;mm<sup>2</sup>
|1,419,000
|-
|G86 Tesla
|210,000,000
|2007
|Nvidia
|TSMC
|80&nbsp;nm
|127&nbsp;mm<sup>2</sup>
|1,654,000
|-
|G84 Tesla
|289,000,000
|2007
|Nvidia
|TSMC
|80&nbsp;nm
|169&nbsp;mm<sup>2</sup>
|1,710,000
|-
|[[Radeon R520|RV560]]
|330,000,000
|2006
|ATI
|TSMC
|80&nbsp;nm
|230&nbsp;mm<sup>2</sup>
|1,435,000
|-
|[[Radeon R600|R600]]
|700,000,000
|2007
|ATI
|TSMC
|80&nbsp;nm
|420&nbsp;mm<sup>2</sup>
|1,667,000
|-
|[[Radeon R600|RV610]]
|180,000,000
|2007
|ATI
|TSMC
|65&nbsp;nm
|85&nbsp;mm<sup>2</sup>
|2,118,000
| rowspan="7" |<ref name="vintage3d"/>
|-
|[[Radeon R600|RV630]]
|390,000,000
|2007
|ATI
|TSMC
|65&nbsp;nm
|153&nbsp;mm<sup>2</sup>
|2,549,000
|-
|[[G92]]
|754,000,000
|2007
|Nvidia
|TSMC, UMC
|[[65&nbsp;nm]]
|324&nbsp;mm<sup>2</sup>
|2,327,000
|-
|G94 Tesla
|505,000,000
|2008
|Nvidia
|TSMC
|65&nbsp;nm
|240&nbsp;mm<sup>2</sup>
|2,104,000
|-
|G96 Tesla
|314,000,000
|2008
|Nvidia
|TSMC
|65&nbsp;nm
|144&nbsp;mm<sup>2</sup>
|2,181,000
|-
|G98 Tesla
|210,000,000
|2008
|Nvidia
|TSMC
|65&nbsp;nm
|86&nbsp;mm<sup>2</sup>
|2,442,000
|-
|[[GeForce 200 series|GT200]]<ref>{{cite web|url=http://www.anandtech.com/video/showdoc.aspx?i=3334 |title=NVIDIA's 1.4 Billion Transistor GPU: GT200 Arrives as the GeForce GTX 280 & 260 |publisher=AnandTech.com |access-date=2014-08-09}}</ref>
|1,400,000,000
|2008
|Nvidia
|TSMC
|65&nbsp;nm
|576&nbsp;mm<sup>2</sup>
|2,431,000
|-
|RV620
|181,000,000
|2008
|ATI
|TSMC
|55&nbsp;nm
|67&nbsp;mm<sup>2</sup>
|2,701,000
| rowspan="6" |<ref name="vintage3d"/>
|-
|RV635
|378,000,000
|2008
|ATI
|TSMC
|55&nbsp;nm
|135&nbsp;mm<sup>2</sup>
|2,800,000
|-
|RV710
|242,000,000
|2008
|ATI
|TSMC
|55&nbsp;nm
|73&nbsp;mm<sup>2</sup>
|3,315,000
|-
|RV730
|514,000,000
|2008
|ATI
|TSMC
|55&nbsp;nm
|146&nbsp;mm<sup>2</sup>
|3,521,000
|-
|RV670
|666,000,000
|2008
|ATI
|TSMC
|55&nbsp;nm
|192&nbsp;mm<sup>2</sup>
|3,469,000
|-
|RV770
|956,000,000
|2008
|ATI
|TSMC
|55&nbsp;nm
|256&nbsp;mm<sup>2</sup>
|3,734,000
|-
|[[Radeon R700|RV790]]
|959,000,000
|2008
|ATI
|TSMC
|55&nbsp;nm
|282&nbsp;mm<sup>2</sup>
|3,401,000
|<ref>{{cite web|url=http://www.anandtech.com/video/showdoc.aspx?i=3341 |title=The Radeon HD 4850 & 4870: AMD Wins at $199 and $299 |publisher=AnandTech.com |access-date=2014-08-09}}</ref><ref name="vintage3d" />
|-
|G92b Tesla
|754,000,000
|2008
|Nvidia
|TSMC, UMC
|55&nbsp;nm
|260&nbsp;mm<sup>2</sup>
|2,900,000
| rowspan="4" |<ref name="vintage3d" />
|-
|G94b Tesla
|505,000,000
|2008
|Nvidia
|TSMC, UMC
|55&nbsp;nm
|196&nbsp;mm<sup>2</sup>
|2,577,000
|-
|G96b Tesla
|314,000,000
|2008
|Nvidia
|TSMC, UMC
|55&nbsp;nm
|121&nbsp;mm<sup>2</sup>
|2,595,000
|-
|GT200b Tesla
|1,400,000,000
|2008
|Nvidia
|TSMC, UMC
|55&nbsp;nm
|470&nbsp;mm<sup>2</sup>
|2,979,000
|-
|GT218 Tesla
|260,000,000
|2009
|Nvidia
|TSMC
|[[40&nbsp;nm]]
|57&nbsp;mm<sup>2</sup>
|4,561,000
| rowspan="5" |<ref name="vintage3d" />
|-
|GT216 Tesla
|486,000,000
|2009
|Nvidia
|TSMC
|40&nbsp;nm
|100&nbsp;mm<sup>2</sup>
|4,860,000
|-
|GT215 Tesla
|727,000,000
|2009
|Nvidia
|TSMC
|40&nbsp;nm
|144&nbsp;mm<sup>2</sup>
|5,049,000
|-
|RV740
|826,000,000
|2009
|ATI
|TSMC
|40&nbsp;nm
|137&nbsp;mm<sup>2</sup>
|6,029,000
|-
|[[Evergreen (GPU family)|Cypress RV870]]
|2,154,000,000
|2009
|ATI
|TSMC
|40&nbsp;nm
|334&nbsp;mm<sup>2</sup>
|6,449,000
|-
|Juniper RV840
|1,040,000,000
|2009
|ATI
|TSMC
|40&nbsp;nm
|166&nbsp;mm<sup>2</sup>
|6,265,000
|
|-
|Redwood RV830
|627,000,000
|2010
|AMD (ATI)
|TSMC
|40&nbsp;nm
|104&nbsp;mm<sup>2</sup>
|6,029,000
| rowspan="6" |<ref name="vintage3d" />
|-
|Cedar RV810
|292,000,000
|2010
|AMD
|TSMC
|40&nbsp;nm
|59&nbsp;mm<sup>2</sup>
|4,949,000
|-
|[[Northern Islands (GPU family)|Cayman RV970]]
|2,640,000,000
|2010
|AMD
|TSMC
|40&nbsp;nm
|389&nbsp;mm<sup>2</sup>
|6,789,000
|-
|Barts RV940
|1,700,000,000
|2010
|AMD
|TSMC
|40&nbsp;nm
|255&nbsp;mm<sup>2</sup>
|6,667,000
|-
|Turks RV930
|716,000,000
|2011
|AMD
|TSMC
|40&nbsp;nm
|118&nbsp;mm<sup>2</sup>
|6,068,000
|-
|Caicos RV910
|370,000,000
|2011
|AMD
|TSMC
|40&nbsp;nm
|67&nbsp;mm<sup>2</sup>
|5,522,000
|-
|GF100 Fermi
|3,200,000,000
|2010
|Nvidia
|TSMC
|40&nbsp;nm
|526&nbsp;mm<sup>2</sup>
|6,084,000
|<ref name="autogenerated1">{{cite web|last=Glaskowsky |first=Peter |url=http://news.cnet.com/8301-13512_3-10369441-23.html |archive-url=https://web.archive.org/web/20120127213001/http://news.cnet.com/8301-13512_3-10369441-23.html |url-status=dead |archive-date=2012-01-27 |title=ATI and Nvidia face off-obliquely |publisher= CNET |access-date=2014-08-09}}</ref>
|-
|GF110 Fermi
|3,000,000,000
|2010
|Nvidia
|TSMC
|40&nbsp;nm
|520&nbsp;mm<sup>2</sup>
|5,769,000
|<ref name="autogenerated1" />
|-
|GF104 Fermi
|1,950,000,000
|2011
|Nvidia
|TSMC
|40&nbsp;nm
|332&nbsp;mm<sup>2</sup>
|5,873,000
|<ref name="vintage3d" />
|-
|[[GeForce 400 series|GF106]] Fermi
|1,170,000,000
|2010
|Nvidia
|TSMC
|40&nbsp;nm
|238&nbsp;mm<sup>2</sup>
|4,916,000
|<ref name="vintage3d" />
|-
|GF108 Fermi
|585,000,000
|2011
|Nvidia
|TSMC
|40&nbsp;nm
|116&nbsp;mm<sup>2</sup>
|5,043,000
|<ref name="vintage3d" />
|-
|GF119 Fermi
|292,000,000
|2011
|Nvidia
|TSMC
|40&nbsp;nm
|79&nbsp;mm<sup>2</sup>
|3,696,000
|<ref name="vintage3d" />
|-
|[[Southern Islands (GPU family)|Tahiti GCN1]]
|4,312,711,873
|2011
|AMD
|TSMC
|[[32 nanometer|28&nbsp;nm]]
|365&nbsp;mm<sup>2</sup>
|11,820,000
|<ref>{{cite web|first=Don |last=Woligroski |url=http://www.tomshardware.com/reviews/radeon-hd-7970-benchmark-tahiti-gcn,3104.html |title=AMD Radeon HD 7970 |publisher=TomsHardware.com |date=2011-12-22 |access-date=2014-08-09}}</ref>
|-
|[[Radeon HD 7000 series|Cape Verde GCN1]]
|1,500,000,000
|2012
|AMD
|TSMC
|28&nbsp;nm
|123&nbsp;mm<sup>2</sup>
|12,200,000
|<ref name="vintage3d" />
|-
|[[Radeon HD 7000 series|Pitcairn GCN1]]
|2,800,000,000
|2012
|AMD
|TSMC
|28&nbsp;nm
|212&nbsp;mm<sup>2</sup>
|13,210,000
|<ref name="vintage3d" />
|-
|[[Nvidia Tesla|GK110 Kepler]]
|7,080,000,000
|2012
|Nvidia
|TSMC
|28&nbsp;nm
|561&nbsp;mm<sup>2</sup>
|12,620,000
|<ref name=NK_1>{{cite web| title=NVIDIA Kepler GK110 Architecture| url=https://staff.cs.manchester.ac.uk/~fumie/internal/KeplerArchitecture.pdf| publisher=[[NVIDIA]]| date=2012| access-date=9 January 2024}}</ref><ref>{{cite news|url=http://www.anandtech.com/show/6446/nvidia-launches-tesla-k20-k20x-gk110-arrives-at-last|title=NVIDIA Launches Tesla K20 & K20X: GK110 Arrives At Last|first=Ryan|last=Smith|date=November 12, 2012|work=[[AnandTech]]}}</ref>
|-
|[[GeForce 600 series|GK104 Kepler]]
|3,540,000,000
|2012
|Nvidia
|TSMC
|28&nbsp;nm
|294&nbsp;mm<sup>2</sup>
|12,040,000
|<ref>{{cite web |title=Whitepaper: NVIDIA GeForce GTX 680 |date=2012 |publisher=NVIDIA |url=http://www.geforce.com/Active/en_US/en_US/pdf/GeForce-GTX-680-Whitepaper-FINAL.pdf |url-status=dead |archive-url=https://web.archive.org/web/20120417045615/http://www.geforce.com/Active/en_US/en_US/pdf/GeForce-GTX-680-Whitepaper-FINAL.pdf |archive-date=April 17, 2012 |df=mdy-all }}</ref>
|-
|GK106 Kepler
|2,540,000,000
|2012
|Nvidia
|TSMC
|28&nbsp;nm
|221&nbsp;mm<sup>2</sup>
|11,490,000
|<ref name="vintage3d" />
|-
|GK107 Kepler
|1,270,000,000
|2012
|Nvidia
|TSMC
|28&nbsp;nm
|118&nbsp;mm<sup>2</sup>
|10,760,000
|<ref name="vintage3d" />
|-
|GK208 Kepler
|1,020,000,000
|2013
|Nvidia
|TSMC
|28&nbsp;nm
|79&nbsp;mm<sup>2</sup>
|12,910,000
|<ref name="vintage3d" />
|-
|[[Graphics Core Next|Oland GCN1]]
|1,040,000,000
|2013
|AMD
|TSMC
|28&nbsp;nm
|90&nbsp;mm<sup>2</sup>
|11,560,000
| rowspan="2" |<ref name="vintage3d" />
|-
|[[Graphics Core Next|Bonaire GCN2]]
|2,080,000,000
|2013
|AMD
|TSMC
|28&nbsp;nm
|160&nbsp;mm<sup>2</sup>
|13,000,000
|-
|[[List of AMD graphics processing units#Console GPUs|Durango]] ([[Xbox One]])
|4,800,000,000
|2013
|AMD
|TSMC
|28&nbsp;nm
|375&nbsp;mm<sup>2</sup>
|12,800,000
|<ref name="Xbox-Transistors">{{cite news |last1=Kan |first1=Michael |title=Xbox Series X May Give Your Wallet a Workout Due to High Chip Manufacturing Costs |url=https://uk.pcmag.com/video-game-consoles/128235/xbox-series-x-may-give-your-wallet-a-workout-due-to-high-chip-manufacturing-costs |access-date=5 September 2020 |work=[[PCMag]] |date=18 August 2020}}</ref><ref>{{Cite web|url=https://www.techpowerup.com/gpu-specs/xbox-one-gpu.c2086|title=AMD Xbox One GPU|website=www.techpowerup.com|access-date=2020-02-05}}</ref>
|-
|[[List of AMD graphics processing units#Console GPUs|Liverpool]] ([[PlayStation 4]])
|{{?}}
|2013
|AMD
|TSMC
|28&nbsp;nm
|348&nbsp;mm<sup>2</sup>
|{{?}}
|<ref>{{Cite web|url=https://www.techpowerup.com/gpu-specs/playstation-4-gpu.c2085|title=AMD PlayStation 4 GPU|website=www.techpowerup.com|access-date=2020-02-05}}</ref>
|-
|[[AMD Radeon Rx 200 series|Hawaii GCN2]]
|6,300,000,000
|2013
|AMD
|TSMC
|28&nbsp;nm
|438&nbsp;mm<sup>2</sup>
|14,380,000
| rowspan="7" |<ref name="vintage3d" />
|-
|[[GeForce GTX Titan X|GM200 Maxwell]]
|8,000,000,000
|2015
|Nvidia
|TSMC
|28&nbsp;nm
|601&nbsp;mm<sup>2</sup>
|13,310,000
|-
|[[GeForce 900 series|GM204 Maxwell]]
|5,200,000,000
|2014
|Nvidia
|TSMC
|28&nbsp;nm
|398&nbsp;mm<sup>2</sup>
|13,070,000
|-
|[[Maxwell (microarchitecture)|GM206 Maxwell]]
|2,940,000,000
|2014
|Nvidia
|TSMC
|28&nbsp;nm
|228&nbsp;mm<sup>2</sup>
|12,890,000
|-
|GM107 [[Maxwell (microarchitecture)|Maxwell]]
|1,870,000,000
|2014
|Nvidia
|TSMC
|28&nbsp;nm
|148&nbsp;mm<sup>2</sup>
|12,640,000
|-
|[[Graphics Core Next|Tonga GCN3]]
|5,000,000,000
|2014
|AMD
|TSMC, [[GlobalFoundries]]
|28&nbsp;nm
|366&nbsp;mm<sup>2</sup>
|13,660,000
|-
|[[Graphics Core Next|Fiji GCN3]]
|8,900,000,000
|2015
|AMD
|TSMC
|28&nbsp;nm
|596&nbsp;mm<sup>2</sup>
|14,930,000
|-
|Durango 2 ([[Xbox One#Xbox One S|Xbox One S]])
|5,000,000,000
|2016
|AMD
|TSMC
|16&nbsp;nm
|240&nbsp;mm<sup>2</sup>
|20,830,000
|<ref>{{Cite web|url=https://www.techpowerup.com/gpu-specs/xbox-one-s-gpu.c2866|title=AMD Xbox One S GPU|website=www.techpowerup.com|access-date=2020-02-05}}</ref>
|-
|[[List of AMD graphics processing units#Console GPUs|Neo]] ([[PlayStation 4#PlayStation 4 Pro|PlayStation 4 Pro]])
|5,700,000,000
|2016
|AMD
|TSMC
|16&nbsp;nm
|325&nbsp;mm<sup>2</sup>
|17,540,000
|<ref>{{Cite web|url=https://www.techpowerup.com/gpu-specs/playstation-4-pro-gpu.c2876|title=AMD PlayStation 4 Pro GPU|website=www.techpowerup.com|access-date=2020-02-05}}</ref>
|-
|Ellesmere/[[AMD Radeon 400 series#Polaris|Polaris&nbsp;10&nbsp;GCN4]]
|5,700,000,000
|2016
|AMD
|Samsung, GlobalFoundries
|14&nbsp;nm
|232&nbsp;mm<sup>2</sup>
|24,570,000
|<ref>{{cite news|last1=Smith|first1=Ryan|title=The AMD RX 480 Preview|url=http://www.anandtech.com/show/10446/the-amd-radeon-rx-480-preview|access-date=22 February 2017|publisher=Anandtech.com|date=29 June 2016}}</ref>
|-
|Baffin/[[AMD Radeon 400 series#Polaris|Polaris 11 GCN4]]
|3,000,000,000
|2016
|AMD
|[[Samsung Electronics|Samsung]], GlobalFoundries
|[[14&nbsp;nm]]
|123&nbsp;mm<sup>2</sup>
|24,390,000
|<ref name="vintage3d"/><ref name="gf-samsung"/>
|-
|Lexa/[[Radeon RX 500 series|Polaris 12 GCN4]]
|2,200,000,000
|2017
|AMD
|Samsung, GlobalFoundries
|14&nbsp;nm
|101&nbsp;mm<sup>2</sup>
|21,780,000
|<ref name="vintage3d"/><ref name="gf-samsung"/>
|-
|[[Nvidia Tesla|GP100 Pascal]]
|15,300,000,000
|2016
|Nvidia
|TSMC, Samsung
|16&nbsp;nm
|610&nbsp;mm<sup>2</sup>
|25,080,000
|<ref>{{cite web|url=https://devblogs.nvidia.com/parallelforall/inside-pascal/|title=Inside Pascal: NVIDIA's Newest Computing Platform|first=Mark|last=Harris|date=April 5, 2016|website=Nvidia developer blog}}</ref><ref name=pascal_tpu />
|-
|[[GeForce 10 series#GeForce 10 (10xx) series|GP102 Pascal]]
|11,800,000,000
|2016
|Nvidia
|TSMC, Samsung
|16&nbsp;nm
|471&nbsp;mm<sup>2</sup>
|25,050,000
|<ref name="vintage3d"/><ref name=pascal_tpu>{{cite web|url=https://www.techpowerup.com/gpu-specs/?architecture=Pascal&sort=generation|title=GPU Database: Pascal|website=TechPowerUp|date=July 26, 2023 }}</ref>
|-
|[[GeForce 10 series#GeForce 10 (10xx) series|GP104 Pascal]]
|7,200,000,000
|2016
|Nvidia
|TSMC
|16&nbsp;nm
|314&nbsp;mm<sup>2</sup>
|22,930,000
|<ref name="vintage3d" /><ref name=pascal_tpu />
|-
|[[GeForce 10 series#GeForce 10 (10xx) series|GP106 Pascal]]
|4,400,000,000
|2016
|Nvidia
|TSMC
|16&nbsp;nm
|200&nbsp;mm<sup>2</sup>
|22,000,000
|<ref name="vintage3d"/><ref name=pascal_tpu />
|-
|[[GeForce 10 series#GeForce 10 (10xx) series|GP107 Pascal]]
|3,300,000,000
|2016
|Nvidia
|Samsung
|14&nbsp;nm
|132&nbsp;mm<sup>2</sup>
|25,000,000
|<ref name="vintage3d" /><ref name=pascal_tpu />
|-
|[[GeForce 10 series#GeForce 10 (10xx) series|GP108 Pascal]]
|1,850,000,000
|2017
|Nvidia
|[[Samsung Electronics|Samsung]]
|14&nbsp;nm
|74&nbsp;mm<sup>2</sup>
|25,000,000
|<ref name="vintage3d" /><ref name=pascal_tpu />
|-
|[[List of AMD graphics processing units#Console GPUs|Scorpio]] ([[Xbox One#Xbox One X|Xbox One X]])
|6,600,000,000
|2017
|AMD
|TSMC
|16&nbsp;nm
|367&nbsp;mm<sup>2</sup>
|17,980,000
|<ref name="Xbox-Transistors"/><ref>{{Cite web|url=https://www.techpowerup.com/gpu-specs/xbox-one-x-gpu.c2977|title=AMD Xbox One X GPU|website=www.techpowerup.com|access-date=2020-02-05}}</ref>
|-
|[[AMD RX Vega series|Vega 10 GCN5]]
|12,500,000,000
|2017
|AMD
|Samsung, GlobalFoundries
|14&nbsp;nm
|484&nbsp;mm<sup>2</sup>
|25,830,000
|<ref>{{Cite web|url=http://radeon.com/_downloads/vega-whitepaper-11.6.17.pdf|title=Radeon's next-generation Vega architecture}}</ref>
|-
|[[Nvidia Tesla|GV100]] [[Volta (microarchitecture)|Volta]]
|21,100,000,000
|2017
|Nvidia
|TSMC
|[[12&nbsp;nm]]
|815&nbsp;mm<sup>2</sup>
|25,890,000
|<ref name="volta">{{cite web|url=https://devblogs.nvidia.com/parallelforall/inside-volta/|title=Inside Volta: The World's Most Advanced Data Center GPU|first1=Luke|last1=Durant|first2=Olivier|last2=Giroux|first3=Mark|last3=Harris|first4=Nick|last4=Stam|date=May 10, 2017|website=Nvidia developer blog}}</ref>
|-
|[[GeForce 20 series#Chipset table|TU102 Turing]]
|18,600,000,000
|2018
|Nvidia
|TSMC
|12&nbsp;nm
|754&nbsp;mm<sup>2</sup>
|24,670,000
|<ref>{{cite web |title=NVIDIA TURING GPU ARCHITECTURE: Graphics Reinvented |url=https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf |publisher=[[Nvidia]] |year=2018 |access-date=28 June 2019}}</ref>
|-
|[[GeForce 20 series#Chipset table|TU104 Turing]]
|13,600,000,000
|2018
|Nvidia
|TSMC
|12&nbsp;nm
|545&nbsp;mm<sup>2</sup>
|24,950,000
|
|-
|[[GeForce 20 series#Chipset table|TU106 Turing]]
|10,800,000,000
|2018
|Nvidia
|TSMC
|12&nbsp;nm
|445&nbsp;mm<sup>2</sup>
|24,270,000
|
|-
|[[GeForce 16 series#Products|TU116 Turing]]
|6,600,000,000
|2019
|Nvidia
|TSMC
|12&nbsp;nm
|284&nbsp;mm<sup>2</sup>
|23,240,000
|<ref>{{Cite web|url=https://www.techpowerup.com/gpu-specs/geforce-gtx-1650.c3366|title=NVIDIA GeForce GTX 1650|website=www.techpowerup.com|access-date=2020-02-05}}</ref>
|-
|[[GeForce 16 series#Products|TU117 Turing]]
|4,700,000,000
|2019
|Nvidia
|TSMC
|12&nbsp;nm
|200&nbsp;mm<sup>2</sup>
|23,500,000
|<ref>{{Cite web|url=https://www.techpowerup.com/gpu-specs/geforce-gtx-1660-ti.c3364|title=NVIDIA GeForce GTX 1660 Ti|website=www.techpowerup.com|access-date=2020-02-05}}</ref>
|-
|[[AMD RX Vega series|Vega 20 GCN5]]
|13,230,000,000
|2018
|AMD
|TSMC
|[[7&nbsp;nm]]
|331&nbsp;mm<sup>2</sup>
|39,970,000
|<ref name="vintage3d" />
|-
|[[Radeon RX 5000 series#Desktop|Navi 10 RDNA]]
|10,300,000,000
|2019
|AMD
|TSMC
|7&nbsp;nm
|251&nbsp;mm<sup>2</sup>
|41,040,000
|<ref>{{Cite web|url=https://www.techpowerup.com/gpu-specs/radeon-rx-5700-xt.c3339|title=AMD Radeon RX 5700 XT|website=www.techpowerup.com|access-date=2020-02-05}}</ref> <!-- Please do not add dual-GPU cards like HD5970, HD4870X2, GTX295, etc. — this is a list of transistor count for chips, not multi-chip cards/modules/systems. -->
|-
|[[Radeon Pro#Radeon Pro 5000M series (for Apple MacBook Pro)|Navi 12 RDNA]]
|{{?}}
|2020
|AMD
|TSMC
|7&nbsp;nm
|{{?}}
|{{?}}
|
|-
|[[Radeon RX 5000 series#Desktop|Navi 14 RDNA]]
|6,400,000,000
|2019
|AMD
|TSMC
|7&nbsp;nm
|158&nbsp;mm<sup>2</sup>
|40,510,000
|<ref>{{Cite web|url=https://www.techpowerup.com/gpu-specs/radeon-rx-5500-xt.c3468|title=AMD Radeon RX 5500 XT|website=www.techpowerup.com|access-date=2020-02-05}}</ref>
|-
|[[AMD Instinct|Arcturus CDNA]]
|25,600,000,000
|2020
|AMD
|TSMC
|7&nbsp;nm
|750&nbsp;mm<sup>2</sup>
|34,100,000
|<ref>{{Cite web|url=https://www.techpowerup.com/gpu-specs/amd-arcturus.g927|title=AMD Arcturus GPU Specs|website=TechPowerUp|access-date=November 10, 2022}}</ref>
|-
|[[Ampere (microarchitecture)|GA100 Ampere]]
|54,200,000,000
|2020
|Nvidia
|TSMC
|7&nbsp;nm
|826&nbsp;mm<sup>2</sup>
|65,620,000
|<ref name="ga100">{{cite news|url=https://www.tomshardware.com/news/nvidia-ampere-A100-gpu-7nm|title=Nvidia Unveils Its Next-Generation 7nm Ampere A100 GPU for Data Centers, and It's Absolutely Massive|first=Jared|last=Walton|date=May 14, 2020|work=[[Tom's Hardware]]}}</ref><ref>{{Cite web|url=https://www.nvidia.com/en-gb/data-center/ampere-architecture/|title=Nvidia Ampere Architecture|website=www.nvidia.com|access-date=2020-05-15}}</ref>
|-
|[[GeForce 30 series|GA102 Ampere]]
|28,300,000,000
|2020
|Nvidia
|Samsung
|8&nbsp;nm
|628&nbsp;mm<sup>2</sup>
|45,035,000
|<ref>{{Cite news|url=https://www.techpowerup.com/gpu-specs/nvidia-ga102.g930|title=NVIDIA GA102 GPU Specs|newspaper=Techpowerup|access-date=2020-09-05}}</ref><ref>{{Cite web|url=https://blogs.nvidia.com/blog/2020/09/01/nvidia-ceo-geforce-rtx-30-series-gpus|title='Giant Step into the Future': NVIDIA CEO Unveils GeForce RTX 30 Series GPUs|website=www.nvidia.com|date=September 2020|access-date=2020-09-05}}</ref>
|-
|[[GeForce 30 series|GA103 Ampere]]
|22,000,000,000
|2022
|Nvidia
|Samsung
|8&nbsp;nm
|496&nbsp;mm<sup>2</sup>
|44,400,000
|<ref>{{Cite web |title=NVIDIA GA103 GPU Specs |url=https://www.techpowerup.com/gpu-specs/nvidia-ga103.g989 |website=TechPowerUp |language=en |access-date=March 21, 2023}}</ref>
|-
|[[GeForce 30 series|GA104 Ampere]]
|17,400,000,000
|2020
|Nvidia
|Samsung
|8&nbsp;nm
|392&nbsp;mm<sup>2</sup>
|44,390,000
|<ref>{{Cite web|title=NVIDIA GeForce RTX 3070 Specs|url=https://www.techpowerup.com/gpu-specs/geforce-rtx-3070.c3674|access-date=2021-09-20|website=TechPowerUp|language=en}}</ref>
|-
|[[GeForce 30 series|GA106 Ampere]]
|12,000,000,000
|2021
|Nvidia
|Samsung
|8&nbsp;nm
|276&nbsp;mm<sup>2</sup>
|43,480,000
|<ref>
{{cite web
|url=https://www.techpowerup.com/gpu-specs/nvidia-ga106.g966
|title=NVIDIA GA106 specs
|website=TechPowerUp
|access-date=2023-03-22
}}</ref>
|-
|[[GeForce 30 series|GA107 Ampere]]
|8,700,000,000
|2021
|Nvidia
|Samsung
|8&nbsp;nm
|200&nbsp;mm<sup>2</sup>
|43,500,000
|<ref>{{Cite web |title=NVIDIA GA107 GPU Specs |url=https://www.techpowerup.com/gpu-specs/nvidia-ga107.g988 |website=TechPowerUp |language=en |access-date=March 21, 2023}}</ref>
|-
|[[Radeon RX 6000 series|Navi 21 RDNA2]]
|26,800,000,000
|2020
|AMD
|TSMC
|7&nbsp;nm
|520&nbsp;mm<sup>2</sup>
|51,540,000
|
|-
|[[Radeon RX 6000 series|Navi 22 RDNA2]]
|17,200,000,000
|2021
|AMD
|TSMC
|7&nbsp;nm
|335&nbsp;mm<sup>2</sup>
|51,340,000
|
|-
|[[Radeon RX 6000 series|Navi 23 RDNA2]]
|11,060,000,000
|2021
|AMD
|TSMC
|7&nbsp;nm
|237&nbsp;mm<sup>2</sup>
|46,670,000
|
|-
|[[Radeon RX 6000 series|Navi 24 RDNA2]]
|5,400,000,000
|2022
|AMD
|TSMC
|6&nbsp;nm
|107&nbsp;mm<sup>2</sup>
|50,470,000
|
|-
|[[AMD Instinct|Aldebaran CDNA2]]
|58,200,000,000 ([[Multi-chip module|MCM]])
|2021
|AMD
|TSMC
|6&nbsp;nm
|1448&ndash;1474&nbsp;mm<sup>2</sup><ref>{{cite web |url=https://twitter.com/Locuza_/status/1460987998934384640 |title=MI250X die size estimates |website=Twitter |date=2021-11-17}}</ref><br>1480&nbsp;mm<sup>2</sup><ref>
{{cite web |url=https://videocardz.net/amd-instinct-mi250 |title=AMD Instinct MI250 Professional Graphics Card |website=VideoCardz |date=2022-11-02}}</ref><br>1490&ndash;1580&nbsp;mm<sup>2</sup><ref>
{{cite web |url=https://www.tomshardware.com/news/amd-instinct-mi250x-pictured |title=AMD's Instinct MI250X OAM Card Pictured: Aldebaran's Massive Die Revealed |website=Tom's Hardware |date=2021-11-17}}</ref>
|39,500,000&ndash;40,200,000<br>39,200,000<br>36,800,000&ndash;39,100,000
|<ref>{{cite web |url=https://www.servethehome.com/amd-mi250x-and-toplogies-explained-at-hc34-hpe-gigabyte-supermicro/ |title=AMD MI250X and Toplogies Explained at HC34 |website=ServeTheHome |date=2022-08-22}}</ref>
|-
|[[Hopper (microarchitecture)|GH100 Hopper]]
|80,000,000,000
|2022
|Nvidia
|TSMC
|[[5 nm process|4&nbsp;nm]]
|814&nbsp;mm<sup>2</sup>
|98,280,000
|<ref>{{Cite web |title=Nvidia Launches Hopper H100 GPU, New DGXs and Grace Superchips |url=https://www.hpcwire.com/2022/03/22/nvidia-launches-hopper-h100-gpu-new-dgxs-and-grace-megachips/ |access-date=2022-03-23 |website=HPCWire |date=March 22, 2022 |language=en}}</ref>
|-
|[[GeForce 40 series|AD102 Ada Lovelace]]
|76,300,000,000
|2022
|Nvidia
|TSMC
|4&nbsp;nm
|608.4&nbsp;mm<sup>2</sup>
|125,411,000
|<ref>{{Cite web |title=NVIDIA details AD102 GPU, up to 18432 CUDA cores, 76.3B transistors and 608 mm<sup>2</sup> |url=https://videocardz.com/newz/nvidia-details-ad102-gpu-up-to-18432-cuda-cores-76-3b-transistors-and-608-mm%C2%B2 |website=VideoCardz |date=2022-09-20}}</ref>
|-
|[[GeForce 40 series|AD103 Ada Lovelace]]
|45,900,000,000
|2022
|Nvidia
|TSMC
|4&nbsp;nm
|378.6&nbsp;mm<sup>2</sup>
|121,240,000
|<ref name=ada103>{{cite web |title=NVIDIA confirms Ada 102/103/104 GPU specs, AD104 has more transistors than GA102 |url=https://videocardz.com/newz/nvidia-confirms-ada-102-103-104-gpu-specs-ad104-has-more-transistors-than-ga102 |website=VideoCardz |date=2022-09-23}}</ref>
|-
|[[GeForce 40 series|AD104 Ada Lovelace]]
|35,800,000,000
|2022
|Nvidia
|TSMC
|4&nbsp;nm
|294.5&nbsp;mm<sup>2</sup>
|121,560,000
|<ref name=ada103 />
|-
|[[GeForce 40 series|AD106 Ada Lovelace]]
|{{?}}
|2023
|Nvidia
|TSMC
|4&nbsp;nm
|190&nbsp;mm<sup>2</sup>
|{{?}}
|<ref name=ad106>{{cite web
 |url=https://www.tomshardware.com/news/nvidia-ad106-and-ad107-gpus-pictured
 |title=Alleged Nvidia AD106 and AD107 GPU Pics, Specs, Die Sizes Revealed
 |website=Tom's Hardware
 |date=2023-02-03
}}</ref><ref>{{cite web
 |url=https://wccftech.com/nvidia-geforce-rtx-4060-ti-ad106-350-gpu-pictured-uses-samsung-gddr6-dies/
 |title=NVIDIA GeForce RTX 4060 Ti "AD106-350" GPU Pictured, Uses Samsung GDDR6 Dies
 |website=WCCFtech
 |date=2023-04-28
}}</ref>
|-
|[[GeForce 40 series|AD107 Ada Lovelace]]
|{{?}}
|2023
|Nvidia
|TSMC
|4&nbsp;nm
|146&nbsp;mm<sup>2</sup>
|{{?}}
|<ref name=ad106 /><ref>{{cite web
 |url=https://wccftech.com/nvidias-smallest-ada-gpu-the-ad107-400-for-geforce-rtx-4060-gpus-pictured/
 |title=NVIDIA's Smallest Ada GPU, The AD107-400, For GeForce RTX 4060 GPUs Pictured
 |website=WCCFtech
 |date=2023-05-21
}}</ref>
|-
|[[Radeon RX 7000 series|Navi 31 RDNA3]]
|57,700,000,000&nbsp;(MCM)<br>45,400,000,000&nbsp;(GCD)<br>6×2,050,000,000&nbsp;(MCD)
|2022
|AMD
|TSMC
|5&nbsp;nm&nbsp;(GCD)<br>6&nbsp;nm&nbsp;(MCD)
|531&nbsp;mm<sup>2</sup>&nbsp;(MCM)<br>306&nbsp;mm<sup>2</sup>&nbsp;(GCD)<br>6×37.5&nbsp;mm<sup>2</sup>&nbsp;(MCD)
|109,200,000&nbsp;(MCM)<br>132,400,000&nbsp;(GCD)<br>54,640,000&nbsp;(MCD)
|<ref>{{cite press release |title=AMD Unveils World's Most Advanced Gaming Graphics Cards, Built on Groundbreaking AMD RDNA 3 Architecture with Chiplet Design |url=https://www.amd.com/en/press-releases/2022-11-03-amd-unveils-world-s-most-advanced-gaming-graphics-cards-built |website=AMD |date=2022-11-03}}</ref><ref>{{cite web |title=AMD Announces the $999 Radeon RX 7900 XTX... (endnote RX-819) |url=https://www.techpowerup.com/300632/amd-announces-the-usd-999-radeon-rx-7900-xtx-and-usd-899-rx-7900-xt-5nm-rdna3-displayport-2-1-fsr-3-0-fluidmotion |website=TechPowerUp |date=2022-11-04}}</ref><ref>{{Cite web |title=AMD Navi 31 GPU Specs |url=https://www.techpowerup.com/gpu-specs/amd-navi-31.g998 |website=TechPowerUp |language=en |access-date=November 7, 2023}}</ref>
|-
|[[Radeon RX 7000 series|Navi 32 RDNA3]]
|28,100,000,000&nbsp;(MCM)
|2023
|AMD
|TSMC
|5&nbsp;nm&nbsp;(GCD)<br>6&nbsp;nm&nbsp;(MCD)
|350&nbsp;mm<sup>2</sup>&nbsp;(MCM)<br>200&nbsp;mm<sup>2</sup>&nbsp;(GCD)<br>4×37.5&nbsp;mm<sup>2</sup>&nbsp;(MCD)
|80,200,000&nbsp;(MCM)
|<ref>{{Cite web |title=AMD Navi 32 GPU Specs |url=https://www.techpowerup.com/gpu-specs/amd-navi-32.g1000 |website=TechPowerUp |language=en |access-date=November 7, 2023}}</ref>
|-
|[[Radeon RX 7000 series|Navi 33 RDNA3]]
|13,300,000,000
|2023
|AMD
|TSMC
|6&nbsp;nm
|204&nbsp;mm<sup>2</sup>
|65,200,000
|<ref>{{Cite web |title=AMD Navi 33 GPU Specs |url=https://www.techpowerup.com/gpu-specs/amd-navi-33.g1001 |website=TechPowerUp |language=en |access-date=March 21, 2023}}</ref>
|-
|[[AMD Instinct|Aqua Vanjaram CDNA3]]
|153,000,000,000 (MCM)
|2023
|AMD
|TSMC
|5&nbsp;nm&nbsp;(GCD)<br>6&nbsp;nm&nbsp;(MCD)
|{{?}}
|{{?}}
|<ref>{{Cite web|title=AMD Has a GPU to Rival Nvidia's H100|url=https://www.hpcwire.com/2023/06/13/amd-has-a-gpu-to-rival-nvidias-h100/|access-date=2023-06-14|website=HPCWire|date=June 13, 2023 |language=en}}</ref><ref>{{Cite web |title=AMD Aqua Vanjaram Specs |url=https://www.techpowerup.com/gpu-specs/amd-aqua-vanjaram.g1023 |website=TechPowerUp |access-date=January 14, 2024}}</ref>
|-
|[[Blackwell (microarchitecture)|GB200 Grace Blackwell]]
|208,000,000,000 (MCM)
|2024
|Nvidia
|TSMC
|4&nbsp;nm&nbsp;
|{{?}}
|{{?}}
|<ref>{{cite press release | url=https://www.globenewswire.com/news-release/2024/03/18/2848181/0/en/NVIDIA-Blackwell-Platform-Arrives-to-Power-a-New-Era-of-Computing.html | title=NVIDIA Blackwell Platform Arrives to Power a New Era of Computing | date=March 18, 2024 }}</ref>
|-
|-
|[[Blackwell (microarchitecture)|GB202 Blackwell (RTX 5090)]]
|92,200,000,000
|2025
|Nvidia
|TSMC
|4&nbsp;nm&nbsp;
|750&nbsp;mm<sup>2</sup>
|122,600,000
|<ref>{{Cite web |date=2025-01-17 |title=NVIDIA GeForce RTX 5090 Specs |url=https://www.techpowerup.com/gpu-specs/geforce-rtx-5090.c4216 |access-date=2025-01-17 |website=TechPowerUp |language=en}}</ref>
|-
! Processor
! data-sort-type="number" | Transistor count
! Year
! Designer(s)
! [[Semiconductor manufacturer|Fab(s)]]
! data-sort-type="number" | [[MOSFET|MOS]] [[Semiconductor device fabrication|process]]
! data-sort-type="number" | Area
! data-sort-type="number" | Transistor<br>density<br>(tr./mm<sup>2</sup>)
! class="unsortable"| {{Abbr|Ref|Reference(s)}}
|}

=== FPGA ===
A [[field-programmable gate array]] (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing.

{| class="wikitable sortable"
|-
! [[FPGA]]
! data-sort-type="number" | Transistor count
! Date of introduction
! Designer
! Manufacturer
! data-sort-type="number" | [[Semiconductor device fabrication|Process]]
! data-sort-type="number" | Area
! data-sort-type="number" | Transistor density, tr./mm<sup>2</sup>
! class="unsortable"| {{Abbr|Ref|Reference(s)}}
|-
|[[Virtex (FPGA)|Virtex]]
|70,000,000
|1997
|[[Xilinx]]
|
|
|
|
|rowspan="5" |
|-
|[[Virtex (FPGA)#Virtex-E|Virtex-E]]
|200,000,000
|1998
|Xilinx
|
|
|
|
|-
|[[Virtex (FPGA)#Virtex-II|Virtex-II]]
|350,000,000
|2000
|Xilinx
|
|130&nbsp;nm
|
|
|-
|[[Virtex (FPGA)#Virtex-II|Virtex-II PRO]]
|430,000,000
|2002
|Xilinx
|
|
|
|
|-
|[[Virtex-4]]
|1,000,000,000
|2004
|Xilinx
|
|90&nbsp;nm
|
|
|-
|[[Virtex-5]]
|1,100,000,000
|2006
|Xilinx
|[[TSMC]]
|65&nbsp;nm
|
|
|<ref>"[https://web.archive.org/web/20081023020234/http://www.sda-asia.com/sda/features/psecom,id,734,srn,2,nodeid,21,_language,Singapore.html Taiwan Company UMC Delivers 65nm FPGAs to Xilinx]." ''SDA-ASIA'' Thursday, November 9, 2006.</ref>
|-
|[[Stratix]] IV
|2,500,000,000
|2008
|[[Altera]]
|TSMC
|40&nbsp;nm
|
|
|<ref>"{{cite web| url= http://www.pldesignline.com/207800871| title= Altera's new 40nm FPGAs — 2.5 billion transistors!| work= pldesignline.com| access-date= January 22, 2009| archive-date= June 19, 2010| archive-url= https://web.archive.org/web/20100619104139/http://www.pldesignline.com/207800871| url-status= dead}}</ref>
|-
|[[Stratix]] V
|3,800,000,000
|2011
|Altera
|TSMC
|28&nbsp;nm
|
|
|{{cn|date=May 2024}}
|-
|Arria 10
|5,300,000,000
|2014
|Altera
|TSMC
|20&nbsp;nm
|
|
|<ref>{{cite web | url= https://www.hotchips.org/wp-content/uploads/hc_archives/hc26/HC26-12-day2-epub/HC26.12-5-FPGAs-epub/HC26.12.510-SoC-FPGA-20nm-Vest-Altera.pdf | title= Design of a High-Density SoC FPGA at 20nm | date= 2014 | access-date= July 16, 2017 | archive-date= April 23, 2016 | archive-url= https://web.archive.org/web/20160423215925/http://www.hotchips.org/wp-content/uploads/hc_archives/hc26/HC26-12-day2-epub/HC26.12-5-FPGAs-epub/HC26.12.510-SoC-FPGA-20nm-Vest-Altera.pdf | url-status= dead }}</ref>
|-
|[[Virtex (FPGA)#Virtex-7|Virtex-7]] 2000T
|6,800,000,000
|2011
|Xilinx
|TSMC
|28&nbsp;nm
|
|
|<ref>{{cite magazine|url=https://www.eetimes.com/document.asp?doc_id=1316816|magazine=EETimes|publisher=AspenCore|date=October 2011|access-date=September 4, 2019|title=New Xilinx Virtex-7 2000T FPGA provides equivalent of 20 million ASIC gates|first=Clive|last=Maxfield}}</ref>
|-
|Stratix 10 SX 2800
|17,000,000,000
|TBD
|Intel
|Intel
|14&nbsp;nm
|560&nbsp;mm<sup>2</sup>
|30,400,000
|<ref>{{Cite book|last1=Greenhill|first1=D.|last2=Ho|first2=R.|last3=Lewis|first3=D.|last4=Schmit|first4=H.|last5=Chan|first5=K. H.|last6=Tong|first6=A.|last7=Atsatt|first7=S.|last8=How|first8=D.|last9=McElheny|first9=P.|title=2017 IEEE International Solid-State Circuits Conference (ISSCC) |chapter=3.3 a 14nm 1GHz FPGA with 2.5D transceiver integration |date=February 2017|pages=54–55|doi=10.1109/ISSCC.2017.7870257|isbn=978-1-5090-3758-2|s2cid=2135354}}</ref><ref>{{Cite web|url=https://www.deepdyve.com/lp/institute-of-electrical-and-electronics-engineers/3-3-a-14nm-1ghz-fpga-with-2-5d-transceiver-integration-dOpKM0jD74|title=3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration {{!}} DeepDyve|date=2017-05-17|access-date=2019-09-19|archive-url=https://web.archive.org/web/20170517193955/https://www.deepdyve.com/lp/institute-of-electrical-and-electronics-engineers/3-3-a-14nm-1ghz-fpga-with-2-5d-transceiver-integration-dOpKM0jD74|archive-date=May 17, 2017}}</ref>
|-
|[[Virtex (FPGA)#Virtex UltraScale|Virtex-Ultrascale]] VU440
|20,000,000,000
|Q1 2015
|Xilinx
|TSMC
|20&nbsp;nm
|
|
|<ref>{{cite magazine|url=http://www.xilinx.com/publications/archives/xcell/Xcell86.pdf|magazine=Xcell journal|publisher=[[Xilinx]]|issue=86|date=May 2014|access-date=June 3, 2014|title=Xilinx Ships Industry's First 20-nm All Programmable Devices|first=Mike|last=Santarini|page=14}}</ref><ref>{{Cite web|url=https://www.xilinx.com/news/press/2015/xilinx-delivers-the-industry-s-first-4m-logic-cell-device-offering-50m-equivalent-asic-gates-and-4x-more-capacity-than-competitive-alternatives.html|title=Xilinx Delivers the Industry's First 4M Logic Cell Device, Offering >50M Equivalent ASIC Gates and 4X More Capacity than Competitive Alternatives|website=www.xilinx.com|last=Gianelli|first=Silvia|date=January 2015|access-date=2019-08-22}}</ref>
|-
|[[Virtex (FPGA)#Virtex UltraScale+|Virtex-Ultrascale+]] VU19P
|35,000,000,000
|2020
|Xilinx
|TSMC
|16&nbsp;nm
|900&nbsp;mm<sup>2</sup>{{efn|name=estimate_fn|Estimate}}
|38,900,000
|<ref>{{Cite web|url=https://www.xilinx.com/news/press/2019/xilinx-announces-the-world-s-largest-fpga-featuring-9-million-system-logic-cells.html|title=Xilinx Announces the World's Largest FPGA Featuring 9 Million System Logic Cells|website=www.xilinx.com|last=Sims|first=Tara|date=August 2019|access-date=2019-08-22}}</ref><ref>{{Cite web|url=https://www.tomshardware.com/news/xilinx-world-largest-fpga,40212.html|title=Xilinx Introduces World's Largest FPGA With 35 Billion Transistors|website=www.tomshardware.com|first=Arne|last=Verheyde|date=August 2019|access-date=2019-08-23}}</ref><ref>{{Cite web|url=https://www.anandtech.com/show/14798/xilinx-announces-world-largest-fpga-virtex-ultrascale-vu19p-with-9m-cells|title=Xilinx Announces World Largest FPGA: Virtex Ultrascale+ VU19P with 9m Cells|website=www.anandtech.com|first=Ian|last=Cutress|date=August 2019|access-date=2019-09-25}}</ref>
|-
|[[List of Xilinx FPGAs#Versal|Versal]] VC1902
|37,000,000,000
|2H 2019
|Xilinx
|TSMC
|[[7 nanometer|7&nbsp;nm]]
|
|
|<ref>{{Cite news|url=https://fudzilla.com/news/ai/48791-xilinx-7nm-versal-taped-out-last-year|title=Xilinx 7nm Versal taped out last year|date=May 2019|last=Abazovic|first=Fuad|access-date=2019-09-30}}</ref><ref>{{Cite news|url=https://www.anandtech.com/show/14768/hot-chips-31-live-blogs-xilinx-versal-ai-engine|title=Hot Chips 31 Live Blogs: Xilinx Versal AI Engine|date=August 2019|last=Cutress|first=Ian|access-date=2019-09-30}}</ref><ref>{{Cite news|url=https://www.electronicproducts.com/News/Hot_Chips_2019_highlights_new_AI_strategies.aspx|title=Hot Chips 2019 highlights new AI strategies|date=August 2019|last=Krewell|first=Kevin|access-date=2019-09-30}}</ref>
|-
|[[Stratix]] 10 GX 10M
|43,300,000,000
|Q4 2019
|Intel
|Intel
|[[14 nanometer|14&nbsp;nm]]
|1,400&nbsp;mm<sup>2</sup>{{efn|name=estimate_fn}}
|30,930,000
|<ref>{{Cite news|url=https://blogs.intel.com/psg/intel-announces-intel-stratix-10-gx-10m-fpga-worlds-highest-capacity-with-10-2-million-logic-elements-targets-asic-prototyping-and-emulation-markets/|title=Intel announces Intel Stratix 10 GX 10M FPGA, worlds highest capacity with 10.2 million logic elements|date=2019-11-06|last=Leibson|first=Steven|access-date=2019-11-07}}</ref><ref>{{Cite news|url=https://www.tomshardware.com/news/intel-introduces-worlds-largest-fpga-with-433-billion-transistors|title=Intel Introduces World's Largest FPGA With 43.3 Billion Transistors|date=2019-11-06|last=Verheyde|first=Arne|access-date=2019-11-07}}</ref>
|-
|[[List of Xilinx FPGAs#Versal|Versal]] VP1802
|92,000,000,000
|2021 {{?}}{{efn|Versal Premium are confirmed to be shipping in 1H 2021 but nothing was mentioned about the VP1802 in particular. Usually Xilinx makes separate news for the release of its biggest devices so the VP1802 is likely to be released later.}}
|Xilinx
|TSMC
|[[7 nanometer|7&nbsp;nm]]
|
|
|<ref>{{Cite news|url=https://www.anandtech.com/show/16002/hot-chips-2020-live-blog-xilinx-versal-acaps-900am-pt|title=Hot Chips 2020 Live Blog: Xilinx Versal ACAPs|date=August 2020|last=Cutress|first=Ian|access-date=2020-09-09}}</ref><ref>{{Cite news|url=https://www.xilinx.com/news/press/2021/xilinx-announces-full-production-shipments-of-7nm-versal-ai-core-and-versal-prime-series-devices.html|title=Xilinx Announces Full Production Shipments of 7nm Versal AI Core and Versal Prime Series Devices|date=April 27, 2021|access-date=2021-05-08}}</ref>
|}

=== Memory ===
{{See also|Random-access memory#Timeline|flash memory#Timeline|read-only memory#Timeline}}

[[Semiconductor memory]] is an electronic [[data storage device]], often used as [[computer memory]], implemented on [[integrated circuit]]s. Nearly all semiconductor memories since the 1970s have used [[MOSFET]]s (MOS transistors), replacing earlier [[bipolar junction transistor]]s. There are two major types of semiconductor memory: [[random-access memory]] (RAM) and [[non-volatile memory]] (NVM). In turn, there are two major RAM types: [[dynamic random-access memory]] (DRAM) and [[static random-access memory]] (SRAM), as well as two major NVM types: [[flash memory]] and [[read-only memory]] (ROM).

Typical [[CMOS]] SRAM consists of six transistors per cell. For DRAM, 1T1C, which means one transistor and one capacitor structure, is common. Capacitor charged or not{{clarify|date=June 2023}} is used to store 1 or 0. In flash memory, the data is stored in floating gates, and the resistance of the transistor is sensed{{clarify|date=June 2023}} to interpret the data stored. Depending on how fine scale the resistance could be separated{{clarify|date=June 2023}}, one transistor could store up to three [[bit]]s, meaning eight distinctive levels of resistance possible per transistor. However, a finer scale comes with the cost of repeatability issues, and hence reliability. Typically, low grade 2-bits [[MLC flash]] is used for [[flash drive]]s, so a 16&nbsp;[[Gigabyte|GB]] flash drive contains roughly 64 billion transistors.

For SRAM chips, six-transistor cells (six transistors per bit) was the standard.<ref name="HC"/> DRAM chips during the early 1970s had three-transistor cells (three transistors per bit), before single-transistor cells (one transistor per bit) became standard since the era of 4{{nbsp}}[[Kibibit|Kb]] DRAM in the mid-1970s.<ref name="shmj-mos">{{cite web |title=Late 1960s: Beginnings of MOS memory |url=http://www.shmj.or.jp/english/pdf/ic/exhibi718E.pdf |website=Semiconductor History Museum of Japan |date=2019-01-23 |access-date=27 June 2019}}</ref><ref name="computerhistory1970">{{cite web |title=1970: Semiconductors compete with magnetic cores |url=https://www.computerhistory.org/storageengine/semiconductors-compete-with-magnetic-cores/ |website=[[Computer History Museum]] |access-date=19 June 2019}}</ref> In [[Single-level cell|single-level]] flash memory, each cell contains one [[floating-gate MOSFET]] (one transistor per bit),<ref>{{cite web |title=2.1.1 Flash Memory |url=http://www.iue.tuwien.ac.at/phd/windbacher/node14.html |website=[[TU Wien]] |access-date=20 June 2019}}</ref> whereas [[multi-level cell|multi-level]] flash contains 2, 3 or 4 bits per transistor.

Flash memory chips are commonly stacked up in layers, up to 128-layer in production,<ref>{{Cite web|url=https://www.anandtech.com/show/14589/sk-hynix-128-layer-4d-nand|title=SK Hynix Starts Production of 128-Layer 4D NAND, 176-Layer Being Developed|last=Shilov|first=Anton|website=www.anandtech.com|access-date=2019-09-16}}</ref> and 136-layer managed,<ref>{{Cite web|url=https://pcper.com/2019/08/samsung-begins-production-of-100-layer-sixth-generation-v-nand-flash/|title=Samsung Begins Production of 100+ Layer Sixth-Generation V-NAND Flash|date=2019-08-11|website=PC Perspective|access-date=2019-09-16}}</ref> and available in end-user devices up to 69-layer from manufacturers.

{| class="wikitable sortable" style="text-align:center"
|+ [[Random-access memory]] (RAM)
! Chip name
! Capacity ([[bit]]s)
! RAM type
! data-sort-type="number" | Transistor count
! Date of introduction
! Manufacturer(s)
! data-sort-type="number" | [[Semiconductor device fabrication|Process]]
! data-sort-type="number" | Area
! data-sort-type="number" | Transistor<br>density<br>(tr./mm<sup>2</sup>)
! class="unsortable"| {{Abbr|Ref|Reference(s)}}
|-
|{{n/a}}
|[[1-bit computing|1-bit]]
|[[Static random-access memory|SRAM]] ([[Memory cell (computing)|cell]])
|6
|1963
|[[Fairchild Semiconductor|Fairchild]]
|{{n/a}}
|{{n/a}}
|{{?}}
|<ref name="computerhistory1966">{{cite web |title=1966: Semiconductor RAMs Serve High-speed Storage Needs |url=https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |website=[[Computer History Museum]] |access-date=19 June 2019}}</ref>
|-
|{{n/a}}
|1-bit
|[[Dynamic random-access memory|DRAM]] (cell)
|1
|1965
|[[Toshiba]]
|{{n/a}}
|{{n/a}}
|{{?}}
|<ref>{{cite web|url=http://www.oldcalculatormuseum.com/s-toshbc1411.html|title=Specifications for Toshiba "TOSCAL" BC-1411|website=Old Calculator Web Museum|access-date=8 May 2018|url-status=live|archive-url=https://web.archive.org/web/20170703071307/http://www.oldcalculatormuseum.com/s-toshbc1411.html|archive-date=3 July 2017}}</ref><ref>{{cite web|url=http://www.oldcalculatormuseum.com/toshbc1411.html |title=Toshiba "Toscal" BC-1411 Desktop Calculator|website=Old Calculator Web Museum|url-status=live|archive-url=https://web.archive.org/web/20070520202433/http://www.oldcalculatormuseum.com/toshbc1411.html |archive-date=2007-05-20}}</ref>
|-
|{{?}}
|[[8-bit computing|8-bit]]
|SRAM ([[Bipolar junction transistor|bipolar]])
|48
|1965
|[[Scientific Data Systems|SDS]], [[Signetics]]
|{{?}}
|{{?}}
|{{?}}
|<ref name="computerhistory1966"/>
|-
|SP95
|[[16-bit computing|16-bit]]
|SRAM (bipolar)
|80
|1965
|[[IBM]]
|{{?}}
|{{?}}
|{{?}}
|<ref>{{cite news |last=Castrucci|first=Paul |title=IBM first in IC memory |url=https://archive.computerhistory.org/resources/access/text/2017/02/102770626-05-01-acc.pdf |work=IBM News |volume=3|issue=9 |via=[[Computer History Museum]] |date=May 10, 1966 |publisher=IBM Corporation |access-date=19 June 2019}}</ref>
|-
|TMC3162
|16-bit
|SRAM ([[Transistor–transistor logic|TTL]])
|96
|1966
|[[Transitron]]
|{{n/a}}
|{{?}}
|{{?}}
|<ref name="computerhistory1970"/>
|-
| rowspan="4" |{{?}}
|{{?}}
|SRAM ([[MOSFET|MOS]])
|{{?}}
|1966
|[[NEC]]
|{{?}}
|{{?}}
|{{?}}
|<ref name="shmj-mos"/>
|-
|[[256-bit computing|256-bit]]
|DRAM ([[Integrated circuit|IC]])
|256
|1968
|Fairchild
|{{?}}
|{{?}}
|{{?}}
|<ref name="computerhistory1970" />
|-
|[[64-bit computing|64-bit]]
|SRAM ([[PMOS logic|PMOS]])
|384
|1968
|Fairchild
|rowspan="2" | {{?}}
|rowspan="2" | {{?}}
|rowspan="2" |{{?}}
|rowspan="2" | <ref name="shmj-mos"/>
|-
|144-bit
|SRAM ([[NMOS logic|NMOS]])
|864
|1968
|[[NEC]]
|-
|1101
|[[256-bit computing|256-bit]]
|SRAM (PMOS)
|1,536
|1969
|[[Intel]]
|12,000&nbsp;nm
|{{?}}
|{{?}}
|<ref name="Intel-Product-Timeline">{{cite web|url=http://download.intel.com/museum/research/arc_collect/timeline/TimelineDateSort7_05.pdf|title=A chronological list of Intel products. The products are sorted by date.|date=July 2005|work=Intel museum|publisher=Intel Corporation|archive-url=https://web.archive.org/web/20070809053720/http://download.intel.com/museum/research/arc_collect/timeline/TimelineDateSort7_05.pdf|archive-date=August 9, 2007|access-date=July 31, 2007}}</ref><ref name="shmj-1970s-sram">{{cite web |title=1970s: SRAM evolution |url=http://www.shmj.or.jp/english/pdf/ic/exhibi724E.pdf |website=Semiconductor History Museum of Japan |access-date=27 June 2019}}</ref><ref name="Pimbley">{{cite book |last1=Pimbley |first1=J. |title=Advanced CMOS Process Technology |date=2012 |publisher=[[Elsevier]] |isbn=9780323156806 |page=7 |url=https://books.google.com/books?id=8EUWHSqevQoC&pg=PA7}}</ref>
|-
|[[Intel 1102|1102]]
|1 [[Kibibit|Kb]]
|DRAM (PMOS)
|3,072
|1970
|[[Intel]], [[Honeywell]]
|{{?}}
|{{?}}
|{{?}}
|<ref name="shmj-mos" />
|-
|[[Intel 1103|1103]]
|1&nbsp;Kb
|DRAM (PMOS)
|3,072
|1970
|Intel
|8,000 [[Nanometre|nm]]
|10&nbsp;mm<sup>2</sup>
|307
|<ref name="Intel2003">{{cite web |title=Intel: 35 Years of Innovation (1968–2003) |url=https://www.intel.com/Assets/PDF/General/35yrs.pdf |publisher=Intel |year=2003 |access-date=26 June 2019 |archive-url=https://web.archive.org/web/20211104070452/https://www.intel.com/Assets/PDF/General/35yrs.pdf |archive-date=4 November 2021 |url-status=dead}}</ref><ref name="HC">[http://history-computer.com/ModernComputer/Basis/dram.html ''The DRAM memory of Robert Dennard''] history-computer.com</ref><ref name="Lojek-1103">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |pages=362–363 |url=https://books.google.com/books?id=2cu1Oh_COv8C&pg=PA362 |quote=The i1103 was manufactured on a 6-mask silicon-gate P-MOS process with 8 μm minimum features. The resulting product had a 2,400&nbsp;μm<sup>2</sup> memory cell size, a die size just under 10&nbsp;mm<sup>2</sup>, and sold for around $21.}}</ref><ref name="computerhistory1970" />
|-
|μPD403
|1&nbsp;Kb
|DRAM (NMOS)
|3,072
|1971
|NEC
|{{?}}
|{{?}}
|{{?}}
|<ref>{{cite web |title=Manufacturers in Japan enter the DRAM market and integration densities are improved |url=http://www.shmj.or.jp/english/pdf/ic/exhibi745E.pdf |website=Semiconductor History Museum of Japan |access-date=27 June 2019}}</ref>
|-
|{{?}}
|2&nbsp;Kb
|DRAM (PMOS)
|6,144
|1971
|[[General Instrument]]
|{{?}}
|12.7&nbsp;mm<sup>2</sup>
|484
|<ref name="Gealow">{{cite web |last1=Gealow |first1=Jeffrey Carl |title=Impact of Processing Technology on DRAM Sense Amplifier Design |url=https://core.ac.uk/download/pdf/4426308.pdf |publisher=[[Massachusetts Institute of Technology]] |via=[[CORE (research service)|CORE]] |date=10 August 1990 |pages=149–166 |access-date=25 June 2019}}</ref>
|-
|2102
|1&nbsp;Kb
|SRAM (NMOS)
|6,144
|1972
|Intel
|{{?}}
|{{?}}
|{{?}}
|<ref name="Intel-Product-Timeline" /><ref>{{cite web |title=Silicon Gate MOS 2102A |url=https://drive.google.com/file/d/0B9rh9tVI0J5mMmZlYWRlMDQtNDYzYS00OWJkLTg4YzYtZDYzMzc5Y2ZlYmVk/view |publisher=[[Intel]] |access-date=27 June 2019}}</ref>
|-
|{{?}}
|8&nbsp;Kb
|DRAM (PMOS)
|8,192
|1973
|IBM
|{{?}}
|18.8&nbsp;mm<sup>2</sup>
|436
|<ref name="Gealow" />
|-
|5101
|1&nbsp;Kb
|SRAM ([[CMOS]])
|6,144
|1974
|Intel
|{{?}}
|{{?}}
|{{?}}
|<ref name="Intel-Product-Timeline"/>
|-
|2116
|16&nbsp;Kb
|DRAM (NMOS)
|16,384
|1975
|Intel
|{{?}}
|{{?}}
|{{?}}
|<ref>{{cite web |title=One of the Most Successful 16K Dynamic RAMs: The 4116 |url=http://smithsonianchips.si.edu/augarten/p50.htm |website=[[National Museum of American History]] |publisher=[[Smithsonian Institution]] |access-date=20 June 2019}}</ref><ref name="computerhistory1970" />
|-
|2114
|4&nbsp;Kb
|SRAM (NMOS)
|24,576
|1976
|Intel
|{{?}}
|{{?}}
|{{?}}
|<ref name="Intel-Product-Timeline"/><ref>{{cite book |title=Component Data Catalog |date=1978 |publisher=[[Intel]] |pages=3–94 |url=http://bitsavers.trailing-edge.com/components/intel/_dataBooks/1978_Intel_Component_Data_Catalog.pdf |access-date=27 June 2019}}</ref>
|-
| rowspan="14" |{{?}}
|4&nbsp;Kb
|SRAM (CMOS)
|24,576
|1977
|Toshiba
|{{?}}
|{{?}}
|{{?}}
|<ref name="shmj-1970s-sram"/>
|-
| rowspan="2" | 64&nbsp;Kb
|DRAM (NMOS)
|65,536
|1977
|[[Nippon Telegraph and Telephone|NTT]]
|{{?}}
|35.4&nbsp;mm<sup>2</sup>
|1851
|<ref name="Gealow" />
|-
|DRAM ([[VMOS]])
|65,536
|1979
|[[Siemens]]
|{{?}}
|25.2&nbsp;mm<sup>2</sup>
|2601
|<ref name="Gealow" />
|-
|16&nbsp;Kb
|SRAM (CMOS)
|98,304
|1980
|[[Hitachi]], Toshiba
|{{?}}
|{{?}}
|{{?}}
|<ref name="stol">{{cite web|url=http://maltiel-consulting.com/Semiconductor_technology_memory.html|title=Memory|website=STOL (Semiconductor Technology Online)|access-date=25 June 2019|archive-date=November 2, 2023|archive-url=https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html|url-status=dead}}</ref>
|-
| rowspan="2" | 256&nbsp;Kb
| rowspan="2" | DRAM (NMOS)
| rowspan="2" | 262,144
| rowspan="2" | 1980
|NEC
|1,500&nbsp;nm
|41.6&nbsp;mm<sup>2</sup>
|6302
|<ref name="Gealow" />
|-
|NTT
|1,000&nbsp;nm
|34.4&nbsp;mm<sup>2</sup>
|7620
|<ref name="Gealow" />
|-
|64&nbsp;Kb
|SRAM (CMOS)
|393,216
|1980
|[[Panasonic|Matsushita]]
|{{?}}
|{{?}}
|{{?}}
|<ref name="stol"/>
|-
|288&nbsp;Kb
|DRAM
|294,912
|1981
|IBM
|{{?}}
|25&nbsp;mm<sup>2</sup>
|11,800
|<ref>{{cite web |title=The Cutting Edge of IC Technology: The First 294,912-Bit (288K) Dynamic RAM |url=http://smithsonianchips.si.edu/augarten/p66.htm |website=[[National Museum of American History]] |publisher=[[Smithsonian Institution]] |access-date=20 June 2019}}</ref>
|-
|64&nbsp;Kb
|SRAM (NMOS)
|393,216
|1982
|Intel
|1,500&nbsp;nm
|{{?}}
|{{?}}
|<ref name="stol"/>
|-
|256&nbsp;Kb
|SRAM (CMOS)
|1,572,864
|1984
|Toshiba
|1,200&nbsp;nm
|{{?}}
|{{?}}
|<ref name="stol"/><ref name="Pimbley"/>
|-
|8 [[Mebibit|Mb]]
|DRAM
|8,388,608
|{{sort|1984|January 5, 1984}}
|[[Hitachi]]
|{{?}}
|{{?}}
|{{?}}
|<ref>{{cite web |title=Computer History for 1984 |url=https://www.computerhope.com/history/1984.htm |website=Computer Hope |access-date=25 June 2019}}</ref><ref>{{cite journal |title=Japanese Technical Abstracts |journal=Japanese Technical Abstracts |date=1987 |volume=2 |issue=3–4 |page=161 |url=https://books.google.com/books?id=Fa0kAQAAIAAJ |publisher=University Microfilms |quote=The announcement of 1M DRAM in 1984 began the era of megabytes.}}</ref>
|-
|16&nbsp;Mb
|DRAM ([[CMOS]])
|16,777,216
|1987
|NTT
|700&nbsp;nm
|148&nbsp;mm<sup>2</sup>
|113,400
|<ref name="Gealow" />
|-
|4&nbsp;Mb
|SRAM (CMOS)
|25,165,824
|1990
|NEC, Toshiba, Hitachi, [[Mitsubishi Electric|Mitsubishi]]
|{{?}}
|rowspan="2" | {{?}}
|rowspan="2" | {{?}}
|rowspan="2" | <ref name="stol"/>
|-
|64&nbsp;Mb
|DRAM (CMOS)
|67,108,864
|1991
|[[Panasonic|Matsushita]], Mitsubishi, [[Fujitsu]], Toshiba
|400&nbsp;nm
|-
|KM48SL2000
|16&nbsp;Mb
|[[SDRAM]]
|16,777,216
|1992
|[[Samsung Electronics|Samsung]]
|{{?}}
|{{?}}
|{{?}}
|<ref>{{cite web |title=KM48SL2000-7 Datasheet |url=https://www.datasheetarchive.com/KM48SL2000-7-datasheet.html |publisher=[[Samsung]] |access-date=19 June 2019 |date=August 1992}}</ref><ref>{{cite journal |title=Electronic Design |journal=[[Electronic Design]] |date=1993 |volume=41 |issue=15–21 |url=https://books.google.com/books?id=QmpJAQAAIAAJ |publisher=Hayden Publishing Company |quote=The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.}}</ref>
|-
| rowspan="14" |{{?}}
|16&nbsp;Mb
|SRAM (CMOS)
|100,663,296
|1992
|Fujitsu, NEC
|400&nbsp;nm
|rowspan="2" | {{?}}
|rowspan="2" | {{?}}
|rowspan="2" | <ref name="stol"/>
|-
|256&nbsp;Mb
|DRAM (CMOS)
|268,435,456
|1993
|Hitachi, NEC
|250&nbsp;nm
|-
|rowspan="4" | 1 [[Gibibit|Gb]]
|rowspan="2" | DRAM
|rowspan="2" | 1,073,741,824
|rowspan="2" | {{sort|1995|January 9, 1995}}
|NEC
|250&nbsp;nm
|{{?}}
|{{?}}
|rowspan="2" | <ref name="HB19950109">''Breaking the gigabit barrier, DRAMs at ISSCC portend major system-design impact. (dynamic random access memory; International Solid-State Circuits Conference; Hitachi Ltd. and NEC Corp. research and development)'', January 9, 1995</ref><ref name="smithsonian-japan">{{cite web|url=http://smithsonianchips.si.edu/ice/cd/PROF96/JAPAN.PDF|title=Japanese Company Profiles|year=1996|publisher=[[Smithsonian Institution]]|access-date=27 June 2019}}</ref>
|-
|Hitachi
|160&nbsp;nm
|{{?}}
|{{?}}
|-
|SDRAM
|1,073,741,824
|1996
|[[Mitsubishi Electric|Mitsubishi]]
|150&nbsp;nm
|{{?}}
|{{?}}
|<ref name="stol"/>
|-
|SDRAM ([[Silicon on insulator|SOI]])
|1,073,741,824
|1997
|[[Hyundai Electronics|Hyundai]]
|{{?}}
|{{?}}
|{{?}}
|<ref name="hynix90s">{{cite web |title=History: 1990s |url=https://www.skhynix.com/eng/about/history1990.jsp |website=[[SK Hynix]] |access-date=6 July 2019 |archive-date=February 5, 2021 |archive-url=https://web.archive.org/web/20210205032928/https://www.skhynix.com/eng/about/history1990.jsp |url-status=dead }}</ref>
|-
| rowspan="2" | 4&nbsp;Gb
|DRAM ([[Multi-level cell|4-bit]])
|1,073,741,824
|1997
|NEC
|150&nbsp;nm
|{{?}}
|{{?}}
|<ref name="stol"/>
|-
|DRAM
|4,294,967,296
|1998
|Hyundai
|{{?}}
|{{?}}
|{{?}}
|<ref name="hynix90s" />
|-
|8&nbsp;Gb
|SDRAM ([[DDR3]])
|8,589,934,592
|{{sort|2008|April 2008}}
| rowspan="2" |Samsung
| rowspan="2" |50&nbsp;nm
| rowspan="2" |{{?}}
| rowspan="2" |{{?}}
| rowspan="2" |<ref>{{cite news |title=Samsung 50nm 2GB DDR3 chips are industry's smallest |url=https://www.slashgear.com/samsung-50nm-2gb-ddr3-chips-are-industrys-smallest-2917676/ |access-date=25 June 2019 |work=SlashGear |date=29 September 2008}}</ref>
|-
|16&nbsp;Gb
|SDRAM (DDR3)
|17,179,869,184
|2008
|-
|32&nbsp;Gb
|SDRAM ([[HBM2]])
|34,359,738,368
|2016
| rowspan="2" |Samsung
| rowspan="2" |20&nbsp;nm
| rowspan="2" |{{?}}
| rowspan="2" |{{?}}
| rowspan="2" |<ref>{{cite news |last1=Shilov |first1=Anton |title=Samsung Increases Production Volumes of 8 GB HBM2 Chips Due to Growing Demand |url=https://www.anandtech.com/show/11643/samsung-increases-8gb-hbm2-production-volume |access-date=29 June 2019 |work=[[AnandTech]] |date=July 19, 2017}}</ref>
|-
|64&nbsp;Gb
|SDRAM (HBM2)
|68,719,476,736
|2017
|-
|128&nbsp;Gb
|SDRAM ([[DDR4]])
|137,438,953,472
|2018
|Samsung
|10&nbsp;nm
|{{?}}
|{{?}}
|<ref>{{cite news |title=Samsung Unleashes a Roomy DDR4 256GB RAM |url=https://www.tomshardware.co.uk/samsung-256gb-ddr4-ram,news-59123.html |access-date=21 June 2019 |work=[[Tom's Hardware]] |date=6 September 2018 |archive-date=June 21, 2019 |archive-url=https://web.archive.org/web/20190621205106/https://www.tomshardware.co.uk/samsung-256gb-ddr4-ram,news-59123.html |url-status=dead }}</ref>
|-
|{{?}}
|[[Resistive random-access memory|RRAM]]<ref>{{Cite web|url=https://spectrum.ieee.org/first-3d-nanotube-and-rram-ics-come-out-of-foundry|title=First 3D Nanotube and RRAM ICs Come Out of Foundry|quote=This wafer was made just last Friday... and it's the first monolithic 3D IC ever fabricated within a foundry|date=19 July 2019|website=IEEE Spectrum: Technology, Engineering, and Science News|access-date=2019-09-16}}</ref> (3DSoC)<ref>{{Cite web|url=https://www.darpa.mil/program/three-dimensional-monolithic-system-on-a-chip|title=Three Dimensional Monolithic System-on-a-Chip|website=www.darpa.mil|access-date=2019-09-16}}</ref>
|{{?}} <!-- assuming less than 4GB since "DARPA wants a foundry technology that makes chips with 50-million logic gates, 4 gigabytes of nonvolatile memory, and 9 million interconnects per square millimeter between the layers that can transmit 50 terabits per second while consuming less than 2 picojoules per bit."-->
|2019
|[[SkyWater Technology]]<ref>{{Cite press release|url=https://www.skywatertechnology.com/press-releases/darpa-3dsoc-initiative-completes-first-year-update-provided-at-eri-summit-on-key-steps-achieved-to-transfer-technology-into-skywaters-200mm-u-s-foundry/|title=DARPA 3DSoC Initiative Completes First Year, Update Provided at ERI Summit on Key Steps Achieved to Transfer Technology into SkyWater's 200mm U.S. Foundry|date=2019-07-25|website=Skywater Technology Foundry|access-date=2019-09-16}}</ref>
|90&nbsp;nm
|{{?}}
|{{?}}
|
|}

{| class="wikitable sortable" style="text-align:center"
|+ [[Flash memory]]
! Chip name
! Capacity ([[bit]]s)
! Flash type
! data-sort-type="number" | [[Floating-gate MOSFET|FGMOS]] transistor count
! Date of introduction
! Manufacturer(s)
! data-sort-type="number" | [[Semiconductor device fabrication|Process]]
! data-sort-type="number" | Area
! data-sort-type="number" | Transistor<br>density<br>(tr./mm<sup>2</sup>)
! class="unsortable"| {{Abbr|Ref|Reference(s)}}
|-
| rowspan="4" |{{?}}
|256 [[Kibibit|Kb]]
|[[NOR flash|NOR]]
|262,144
|1985
|[[Toshiba]]
|2,000&nbsp;nm
|rowspan="4" | {{?}}
|rowspan="4" | {{?}}
|rowspan="4" | <ref name="stol"/>
|-
|1 [[Mebibit|Mb]]
|NOR
|1,048,576
|1989
|[[Seeq Corporation|Seeq]], [[Intel]]
|{{?}}
|-
|4&nbsp;Mb
|[[NAND flash|NAND]]
|4,194,304
|1989
|Toshiba
|1,000&nbsp;nm
|-
|16&nbsp;Mb
|NOR
|16,777,216
|1991
|[[Mitsubishi Electric|Mitsubishi]]
|600&nbsp;nm
|-
|DD28F032SA
|32&nbsp;Mb
|NOR
|33,554,432
|1993
|Intel
|{{?}}
|280&nbsp;mm<sup>2</sup>
|120,000
|<ref name="Intel-Product-Timeline"/><ref>{{cite web |title=DD28F032SA Datasheet |url=http://www.datasheetcatalog.com/datasheets_pdf/D/D/2/8/DD28F032SA.shtml |publisher=[[Intel]] |access-date=27 June 2019}}</ref>
|-
| rowspan="11" | {{?}}
| rowspan="2"  | 64&nbsp;Mb
|NOR
|67,108,864
|1994
|[[NEC]]
|rowspan="2" | 400&nbsp;nm
|rowspan="4" | {{?}}
|rowspan="4" | {{?}}
|rowspan="4" | <ref name="stol"/>
|-
|NAND
|67,108,864
|1996
|[[Hitachi]]
|-
|128&nbsp;Mb
|NAND
|134,217,728
|1996
|[[Samsung Electronics|Samsung]], Hitachi
|{{?}}
|-
|256&nbsp;Mb
|NAND
|268,435,456
|1999
|[[Hitachi]], Toshiba
|250&nbsp;nm
|-
|512&nbsp;Mb
|NAND
|536,870,912
|2000
|Toshiba
|{{?}}
|{{?}}
|{{?}}
|<ref>{{cite news |title=TOSHIBA ANNOUNCES 0.13 MICRON 1Gb MONOLITHIC NAND FEATURING LARGE BLOCK SIZE FOR IMPROVED WRITE/ERASE SPEED PERFORMANCE |url=http://www.toshiba.com/taec/news/press_releases/2002/to-230.jsp |archive-url=https://web.archive.org/web/20060311224004/http://www.toshiba.com/taec/news/press_releases/2002/to-230.jsp |url-status=dead |archive-date=March 11, 2006 |access-date=11 March 2006 |publisher=[[Toshiba]] |date=September 9, 2002}}</ref>
|-
| rowspan="2" |1 [[Gibibit|Gb]]
| rowspan="2" |[[Multi-level cell|2-bit]] NAND
| rowspan="2" |536,870,912
| rowspan="2" |2001
|Samsung
|{{?}}
|{{?}}
|{{?}}
|<ref name="stol"/>
|-
|Toshiba, [[SanDisk]]
|160&nbsp;nm
|{{?}}
|{{?}}
|<ref>{{cite news |title=TOSHIBA AND SANDISK INTRODUCE A ONE GIGABIT NAND FLASH MEMORY CHIP, DOUBLING CAPACITY OF FUTURE FLASH PRODUCTS |url=http://www.toshiba.co.jp/about/press/2001_11/pr1202.htm |access-date=20 June 2019 |publisher=[[Toshiba]] |date=12 November 2001}}</ref>
|-
|2&nbsp;Gb
|NAND
|2,147,483,648
|2002
|Samsung, Toshiba
|{{?}}
|{{?}}
|{{?}}
|<ref name="samsung2000s">{{cite web |title=Our Proud Heritage from 2000 to 2009 |url=https://www.samsung.com/semiconductor/about-us/history-03/ |website=[[Samsung Semiconductor]] |publisher=[[Samsung]] |access-date=25 June 2019}}</ref><ref>{{cite news |title=TOSHIBA ANNOUNCES 1 GIGABYTE COMPACTFLASH CARD |url=http://www.toshiba.com/taec/news/press_releases/2002/to-231.jsp |archive-url=https://web.archive.org/web/20060311212118/http://www.toshiba.com/taec/news/press_releases/2002/to-231.jsp |url-status=dead |archive-date=March 11, 2006 |access-date=11 March 2006 |publisher=[[Toshiba]] |date=September 9, 2002}}</ref>
|-
|8&nbsp;Gb
|NAND
|8,589,934,592
|2004
|Samsung
|60&nbsp;nm
|{{?}}
|{{?}}
|<ref name="samsung2000s"/>
|-
|16&nbsp;Gb
|NAND
|17,179,869,184
|2005
|Samsung
|50&nbsp;nm
|rowspan="2" | {{?}}
|rowspan="2" | {{?}}
|rowspan="2" | <ref name="samsung-history"/>
|-
|32&nbsp;Gb
|NAND
|34,359,738,368
|2006
|Samsung
|40&nbsp;nm
|-
|THGAM
|128&nbsp;Gb
|[[Three-dimensional integrated circuit|Stacked]] NAND
|128,000,000,000
|{{sort|2007|April 2007}}
|Toshiba
|56&nbsp;nm
|252&nbsp;mm<sup>2</sup>
|507,900,000
|<ref name="Toshiba2007">{{cite news |title=TOSHIBA COMMERCIALIZES INDUSTRY'S HIGHEST CAPACITY EMBEDDED NAND FLASH MEMORY FOR MOBILE CONSUMER PRODUCTS |url=http://www.toshiba.com/taec/news/press_releases/2007/memy_07_470.jsp |archive-url=https://web.archive.org/web/20101123023805/http://www.toshiba.com/taec/news/press_releases/2007/memy_07_470.jsp |url-status=dead |archive-date=November 23, 2010 |access-date=23 November 2010 |work=[[Toshiba]] |date=April 17, 2007}}</ref>
|-
|THGBM
|256&nbsp;Gb
|Stacked NAND
|256,000,000,000
|2008
|Toshiba
|43&nbsp;nm
|353&nbsp;mm<sup>2</sup>
|725,200,000
|<ref name="Toshiba2008">{{cite news |title=Toshiba Launches the Largest Density Embedded NAND Flash Memory Devices |url=https://www.toshiba.co.jp/about/press/2008_08/pr0701.htm |access-date=21 June 2019 |publisher=[[Toshiba]] |date=7 August 2008}}</ref>
|-
|THGBM2
|1 [[Terabit|Tb]]
|Stacked [[quad-level cell|4-bit]] NAND
|256,000,000,000
|2010
|Toshiba
|32&nbsp;nm
|374&nbsp;mm<sup>2</sup>
|684,500,000
|<ref name="toshiba2010">{{cite news |title=Toshiba Launches Industry's Largest Embedded NAND Flash Memory Modules |url=https://www.toshiba.co.jp/about/press/2010_06/pr1701.htm |access-date=21 June 2019 |work=[[Toshiba]] |date=17 June 2010}}</ref>
|-
|KLMCG8GE4A
|512&nbsp;Gb
|Stacked 2-bit NAND
|256,000,000,000
|2011
|Samsung
|{{?}}
|192&nbsp;mm<sup>2</sup>
|1,333,000,000
|<ref>{{cite web |title=Samsung e·MMC Product family |url=http://www.mt-system.ru/sites/default/files/klmxgxge4a-x001mmc4_41_2ynm_based_emmc1_1.pdf |publisher=[[Samsung Electronics]] |date=December 2011 |access-date=15 July 2019 |archive-date=November 8, 2019 |archive-url=https://web.archive.org/web/20191108055325/http://www.mt-system.ru/sites/default/files/klmxgxge4a-x001mmc4_41_2ynm_based_emmc1_1.pdf |url-status=dead }}</ref>
|-
|KLUFG8R1EM
|4&nbsp;Tb
|Stacked [[triple-level cell|3-bit]] [[V-NAND]]
|1,365,333,333,504
|2017
|Samsung
|{{?}}
|150&nbsp;mm<sup>2</sup>
|9,102,000,000
|<ref name="anandtech-samsung-2017">{{cite news|url=https://www.anandtech.com/show/12120/samsung-starts-production-of-512-gb-ufs-chips|title=Samsung Starts Production of 512&nbsp;GB UFS NAND Flash Memory: 64-Layer V-NAND, 860&nbsp;MB/s Reads|last1=Shilov|first1=Anton|date=December 5, 2017|work=[[AnandTech]]|access-date=23 June 2019}}</ref>
|-
|[[Universal Flash Storage|eUFS]] (1{{nbsp}}TB)
|8&nbsp;Tb
|Stacked 4-bit V-NAND
|2,048,000,000,000
|2019
|Samsung
|{{?}}
|150&nbsp;mm<sup>2</sup>
|13,650,000,000
|<ref name="electronicsweekly-samsung">{{cite news |last1=Manners |first1=David |title=Samsung makes 1TB flash eUFS module |url=https://www.electronicsweekly.com/news/business/samsung-makes-1tb-flash-module-2019-01/ |access-date=23 June 2019 |work=[[Electronics Weekly]] |date=30 January 2019}}</ref><ref name="anandtech-samsung-2018">{{cite news |last1=Tallis |first1=Billy |title=Samsung Shares SSD Roadmap for QLC NAND And 96-layer 3D NAND |url=https://www.anandtech.com/show/13497/samsung-shares-ssd-roadmap-for-qlc-nand-and-96layer-3d-nand |access-date=27 June 2019 |work=[[AnandTech]] |date=October 17, 2018}}</ref>
|-
|{{?}}
|1 Tb
|232L TLC NAND die
|333,333,333,333
|2022
|Micron
|{{?}}
|68.5&nbsp;mm<sup>2</sup><br>(memory array)
|4,870,000,000<br>(14.6 Gbit/mm<sup>2</sup>)
|<ref>{{cite web
 |url=https://www.anandtech.com/print/17509/microns-232-layer-nand-now-shipping
 |title=Micron's 232 Layer NAND Now Shipping
 |website=AnandTech
 |date=2022-07-26
}}</ref><ref>{{cite web
 |url=https://www.micron.com/products/nand-flash/232-layer-nand
 |title=232-Layer NAND
 |website=Micron
 |access-date=2022-10-17
}}</ref><ref>{{cite web
 |url=https://www.micron.com/about/blog/2022/july/first-to-market-second-to-none-the-worlds-first-232-layer-nand
 |title=First to Market, Second to None: the World's First 232-Layer NAND
 |website=Micron
 |date=2022-07-26
}}</ref><ref>{{cite web
 |url=https://www.techinsights.com/blog/comparison-latest-3d-nand-products-ymtc-samsung-sk-hynix-and-micron
 |title=Comparison: Latest 3D NAND Products from YMTC, Samsung, SK hynix and Micron
 |website=TechInsights
 |date=2023-01-11
}}</ref>
|-
|{{?}}
|16 Tb
|232L package
|5,333,333,333,333
|2022
|Micron
|{{?}}
|68.5&nbsp;mm<sup>2</sup><br>(memory array)
|77,900,000,000<br>(16×14.6 Gbit/mm<sup>2</sup>)
|
|}

{| class="wikitable sortable" style="text-align:center"
|+ [[Read-only memory]] (ROM)
|-
! Chip name
! Capacity ([[bit]]s)
! ROM type
! data-sort-type="number" | Transistor count
! Date of introduction
! Manufacturer(s)
! data-sort-type="number" | [[Semiconductor device fabrication|Process]]
! data-sort-type="number" | Area
! class="unsortable"| {{Abbr|Ref|Reference(s)}}
|-
| rowspan="2" |{{?}}
|{{?}}
|[[Programmable read-only memory|PROM]]
|{{?}}
|1956
|[[Wen Tsing Chow|Arma]]
|{{n/a}}
|{{?}}
|<ref name="Huang2008">{{cite book|author=Han-Way Huang|title=Embedded System Design with C805|url=https://books.google.com/books?id=3zRtCgAAQBAJ&pg=PA22|date=5 December 2008|publisher=Cengage Learning|isbn=978-1-111-81079-5|page=22|url-status=live|archive-url=https://web.archive.org/web/20180427092847/https://books.google.com/books?id=3zRtCgAAQBAJ&pg=PA22|archive-date=27 April 2018}}</ref><ref name="AufaureZimányi2013">{{cite book|author1=Marie-Aude Aufaure|author2=Esteban Zimányi|title=Business Intelligence: Second European Summer School, eBISS 2012, Brussels, Belgium, July 15-21, 2012, Tutorial Lectures|url=https://books.google.com/books?id=7iK5BQAAQBAJ&pg=PA136|date=17 January 2013|publisher=Springer|isbn=978-3-642-36318-4|page=136|url-status=live|archive-url=https://web.archive.org/web/20180427092847/https://books.google.com/books?id=7iK5BQAAQBAJ&pg=PA136|archive-date=27 April 2018}}</ref>
|-
|1 [[Kibibit|Kb]]
|[[Read-only memory|ROM]] ([[MOSFET|MOS]])
|1,024
|1965
|[[General Microelectronics]]
|{{?}}
|{{?}}
|<ref name="computerhistory1965">{{cite web |title=1965: Semiconductor Read-Only-Memory Chips Appear |url=https://www.computerhistory.org/siliconengine/semiconductor-read-only-memory-chips-appear/ |website=[[Computer History Museum]] |access-date=20 June 2019}}</ref>
|-
|3301
|1&nbsp;Kb
|ROM ([[Bipolar junction transistor|bipolar]])
|1,024
|1969
|[[Intel]]
|{{n/a}}
|{{?}}
|<ref name="computerhistory1965"/>
|-
|1702
|2&nbsp;Kb
|[[EPROM]] (MOS)
|2,048
|1971
|Intel
|{{?}}
|15&nbsp;mm<sup>2</sup>
|<ref>{{cite web |title=1971: Reusable semiconductor ROM introduced |url=https://www.computerhistory.org/storageengine/reusable-semiconductor-rom-introduced/ |website=The Storage Engine |publisher=[[Computer History Museum]] |access-date=19 June 2019}}</ref>
|-
|{{?}}
|4&nbsp;Kb
|ROM (MOS)
|4,096
|1974
|[[AMD]], [[General Instrument]]
|{{?}}
|{{?}}
|<ref name="computerhistory1965"/>
|-
|2708
|8&nbsp;Kb
|EPROM (MOS)
|8,192
|1975
|Intel
|{{?}}
|{{?}}
|<ref name="Intel-Product-Timeline"/>
|-
|{{?}}
|2&nbsp;Kb
|[[EEPROM]] (MOS)
|2,048
|1976
|[[Toshiba]]
|{{?}}
|{{?}}
|<ref name="Iizuka-1976">{{cite journal|last1=Iizuka|first1=H.|last2=Masuoka|first2=F.|last3=Sato|first3=Tai|last4=Ishikawa|first4=M.|title=Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure|journal=IEEE Transactions on Electron Devices|date=1976|volume=23|issue=4|pages=379–387|doi=10.1109/T-ED.1976.18415|issn=0018-9383|bibcode=1976ITED...23..379I|s2cid=30491074}}</ref>
|-
|μCOM-43 ROM
|16&nbsp;Kb
|PROM ([[PMOS logic|PMOS]])
|16,000
|1977
|[[NEC]]
|{{?}}
|{{?}}
|<ref>{{cite book |title=μCOM-43 SINGLE CHIP MICROCOMPUTER: USERS' MANUAL |date=January 1978 |publisher=[[NEC|NEC Microcomputers]] |url=https://en.wikichip.org/w/images/9/9c/%C2%B5COM-43_SINGLE_CHIP_MICROCOMPUTER_USERS_MANUAL.pdf |access-date=27 June 2019}}</ref>
|-
|2716
|16&nbsp;Kb
|EPROM ([[Transistor–transistor logic|TTL]])
|16,384
|1977
|Intel
|{{n/a}}
|{{?}}
|<ref name="Intel2003"/><ref>{{cite web |title=2716: 16K (2K x 8) UV ERASABLE PROM |url=https://amigan.yatho.com/2716EPROM.pdf |publisher=Intel |access-date=27 June 2019 |archive-date=September 13, 2020 |archive-url=https://web.archive.org/web/20200913213609/https://amigan.yatho.com/2716EPROM.pdf |url-status=dead }}</ref>
|-
|EA8316F
|16&nbsp;Kb
|ROM ([[NMOS logic|NMOS]])
|16,384
|1978
|[[NEC|Electronic Arrays]]
|{{?}}
|436&nbsp;mm<sup>2</sup>
|<ref name="computerhistory1965"/><ref>{{cite web |title=1982 CATALOG |url=http://bitsavers.trailing-edge.com/components/nec/_dataBooks/1982_NEC_Microcomputer_Catalog.pdf |publisher=[[NEC Electronics]] |access-date=20 June 2019}}</ref>
|-
|2732
|32&nbsp;Kb
|[[EPROM]]
|32,768
|1978
|Intel
|{{?}}
|{{?}}
|<ref name="Intel-Product-Timeline"/>
|-
|2364
|64&nbsp;Kb
|ROM
|65,536
|1978
|Intel
|{{?}}
|{{?}}
|<ref>{{cite book |title=Component Data Catalog |date=1978 |publisher=[[Intel]] |pages=1–3 |url=http://bitsavers.trailing-edge.com/components/intel/_dataBooks/1978_Intel_Component_Data_Catalog.pdf |access-date=27 June 2019}}</ref>
|-
|2764
|64&nbsp;Kb
|EPROM
|65,536
|1981
|Intel
|3,500 [[Nanometre|nm]]
|rowspan="2" | {{?}}
|rowspan="2" | <ref name="Intel-Product-Timeline"/><ref name="stol"/>
|-
|27128
|128&nbsp;Kb
|EPROM
|131,072
|1982
|Intel
|{{?}}
|-
|27256
|256&nbsp;Kb
|EPROM ([[HMOS]])
|262,144
|1983
|Intel
|{{?}}
|{{?}}
|<ref name="Intel-Product-Timeline"/><ref>{{cite web |title=27256 Datasheet |url=https://datasheet.octopart.com/D27256-2-Intel-datasheet-17852618.pdf |publisher=[[Intel]] |access-date=2 July 2019}}</ref>
|-
| rowspan="2" |{{?}}
|256&nbsp;Kb
|EPROM ([[CMOS]])
|262,144
|1983
|[[Fujitsu]]
|{{?}}
|{{?}}
|<ref>{{cite web |title=History of Fujitsu's Semiconductor Business |url=https://www.fujitsu.com/jp/group/fsl/en/business/semiconductor/history/ |publisher=[[Fujitsu]] |access-date=2 July 2019}}</ref>
|-
|512&nbsp;Kb
|EPROM (NMOS)
|524,288
|1984
|[[AMD]]
|1,700&nbsp;nm
|{{?}}
|<ref name="stol"/>
|-
|27512
|512&nbsp;Kb
|EPROM (HMOS)
|524,288
|1984
|Intel
|{{?}}
|{{?}}
|<ref name="Intel-Product-Timeline"/><ref>{{cite web |title=D27512-30 Datasheet |url=https://www.datasheet.live/index.php?title=Special:PdfViewer&url=https%3A%2F%2Fpdf.datasheet.live%2Fe6dbd5cf%2Fintel.com%2FD27512-30.pdf |publisher=[[Intel]] |access-date=2 July 2019}}</ref>
|-
| rowspan="4" |{{?}}
|1 [[Mebibit|Mb]]
|EPROM (CMOS)
|1,048,576
|1984
|NEC
|1,200&nbsp;nm
|rowspan="3" | {{?}}
|rowspan="3" | <ref name="stol"/>
|-
|4&nbsp;Mb
|EPROM (CMOS)
|4,194,304
|1987
|Toshiba
|800&nbsp;nm
|-
| rowspan="2" | 16&nbsp;Mb
|EPROM (CMOS)
|16,777,216
|1990
|NEC
|600&nbsp;nm
|-
|[[Mask ROM|MROM]]
|16,777,216
|1995
|[[AKM Semiconductor, Inc.|AKM]], [[Hitachi]]
|{{?}}
|{{?}}
|<ref name="smithsonian-japan"/>
|}

=== Transistor computers ===
[[File:IBM 7070.jpg|thumb|upright|Part of an [[IBM 7070]] card cage populated with [[Standard Modular System]] cards]]
{{main|Transistor computer}}
Before transistors were invented, [[relay]]s were used in commercial [[tabulating machines]] and experimental early computers. The world's first working [[computer programming|programmable]], fully automatic [[digital computer]],<ref>{{cite news|url=https://www.nytimes.com/1994/04/20/news/20iht-zuse.html|title=A Computer Pioneer Rediscovered, 50 Years On|date=April 20, 1994|newspaper=The New York Times|url-status=dead|archive-url=https://web.archive.org/web/20161104051054/http://www.nytimes.com/1994/04/20/news/20iht-zuse.html|archive-date=November 4, 2016|df=mdy-all}}</ref> the 1941 [[Z3 (computer)|Z3]] 22-[[bit]] [[Word (data type)|word]] length computer, had 2,600 relays, and operated at a [[clock frequency]] of about 4–5&nbsp;[[Hertz|Hz]]. The 1940 Complex Number Computer <!-- later renamed Model 1--> had fewer than 500 relays,<ref>{{Cite web|url=https://history-computer.com/ModernComputer/Relays/Stibitz.html|title=History of Computers and Computing, Birth of the modern computer, Relays computer, George Stibitz|quote=Initially the 'Complex Number Computer' performed only complex multiplication and division, but later a simple modification enabled it to add and subtract as well. It used about 400-450 binary relays, 6-8 panels, and ten multiposition, multipole relays called "crossbars" for temporary storage of numbers.|website=history-computer.com|access-date=2019-08-22}}</ref> but it was not fully programmable. The earliest practical computers used [[vacuum tubes]] and solid-state [[diode logic]]. [[ENIAC]] had 18,000 vacuum tubes, 7,200 crystal diodes, and 1,500 relays, with many of the vacuum tubes containing two [[triode]] elements.

The second generation of computers were [[transistor computer]]s that featured boards filled with discrete transistors, solid-state diodes and [[magnetic-core memory|magnetic memory cores]]. The experimental 1953 [[48-bit computing|48-bit]] [[Manchester computers#Transistor Computer|Transistor Computer]], developed at the [[University of Manchester]], is widely believed to be the first transistor computer to come into operation anywhere in the world (the prototype had 92 point-contact transistors and 550 diodes).<ref name="computerhistory"/> A later version the 1955 machine had a total of 250 junction transistors and 1,300 point-contact diodes. The Computer also used a small number of tubes in its clock generator, so it was not the first {{Em|fully}} transistorized. The ETL Mark III, developed at the [[Electrotechnical Laboratory]] in 1956, may have been the first transistor-based electronic computer using the [[stored program]] method. It had about "130 point-contact transistors and about 1,800 germanium diodes were used for logic elements, and these were housed on 300 plug-in packages which could be slipped in and out."<ref name="etl3"/> The 1958 [[decimal architecture]] [[IBM 7070]] was the first transistor computer to be fully programmable. It had about 30,000 alloy-junction germanium transistors and 22,000 germanium diodes, on approximately 14,000 [[Standard Modular System]] (SMS) cards. The 1959 [[MOBIDIC]], short for "MOBIle DIgital Computer", at 12,000 pounds (6.0 short tons) mounted in the trailer of a [[semi-trailer]] truck, was a transistorized computer for battlefield data.<!-- how many transistors?-->

The third generation of computers used [[integrated circuit]]s (ICs).<ref name="ipsj-history">{{cite web |title=Brief History |url=http://museum.ipsj.or.jp/en/computer/main/history.html |website=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |access-date=19 June 2019}}</ref> The 1962 [[16-bit computing|15-bit]] <!-- 16-bit w/parity--> [[Apollo Guidance Computer]] used "about 4,000 "Type-G" (3-input NOR gate) circuits" for about 12,000 transistors plus 32,000 resistors.<ref>{{Cite web|url=https://www.computerhistory.org/siliconengine/aerospace-systems-are-first-the-applications-for-ics-in-computers/|title=1962: Aerospace systems are first the applications for ICs in computers {{!}} The Silicon Engine {{!}} Computer History Museum|website=www.computerhistory.org|access-date=2019-09-02}}</ref>
<!--
33 modules (for logic, excluding RAM?) = 3960 ICs?

http://www.righto.com/2019/01/inside-apollo-guidance-computers-core.html
"The AGC is implemented with dozens of modules in two trays. [..]
The AGC's logic is entirely built from 3-input NOR gates (two per integrated circuit), and the address decoder is no exception. The image below shows logic module A14. (The other logic modules look essentially the same, but the internal printed circuit board is wired differently.) The logic modules all have a similar design: two rows of 30 ICs on each side, for 120 ICs in total, or 240 3-input NOR gates. (Module A14 has one blank location on each side, for 118 ICs in total.) [..]
Each integrated circuit implemented two NOR gates using RTL (resistor-transistor logic), an early logic family. These ICs were costly; they cost $20-$30 each (around $150 in current dollars). There wasn't much inside each IC, just three transistors and eight resistors.
-->
The [[IBM System/360]], introduced 1964, used discrete transistors in [[hybrid circuit]] packs.<ref name="ipsj-history"/> The 1965 [[12-bit computing|12-bit]] [[PDP-8]] CPU had 1409 discrete transistors and over 10,000 diodes, on many cards. Later versions, starting with the 1968 PDP-8/I, used integrated circuits. The PDP-8 was later reimplemented as a microprocessor as the [[Intersil 6100]], see below.<ref name="straight 8" >{{Cite web|url=https://www.pdp8.net/straight8/functional_restore.shtml|title=PDP-8 (Straight 8) Computer Functional Restoration|website=www.pdp8.net|access-date=2019-08-22|quote=backplanes contain 230 cards, approximately 10,148 diodes, 1409 transistors, 5615 resistors, and 1674 capacitors}}</ref>

The next generation of computers were the [[microcomputer]]s, starting with the 1971 [[Intel 4004]], which used [[MOSFET|MOS]] transistors. These were used in [[home computer]]s or [[personal computer]]s (PCs).

This list includes early transistorized computers (second generation) and IC-based computers (third generation) from the 1950s and 1960s.

{| class="wikitable sortable" style="text-align:center"
|-
! Computer
! data-sort-type="number" | Transistor count
! Year
! Manufacturer
! Notes
! class="unsortable"| {{Abbr|Ref|Reference(s)}}
|-
|[[Manchester computers#Transistor Computer|Transistor Computer]]
|92 <!-- this prototype, didn't have stored program capability; "The 48-bit machine used 92 point-contact transistors and 550 diodes". The second version was completed in April 1955. The 1955 version used 250 junction transistors, 1,300 solid-state diodes -->
|1953
|[[University of Manchester]]
|[[Point-contact transistor]]s, 550 diodes. Lacked stored program capability. 
|<ref name="computerhistory">{{cite web |title=1953: Transistorized Computers Emerge |url=https://www.computerhistory.org/siliconengine/transistorized-computers-emerge/ |website=[[Computer History Museum]] |access-date=19 June 2019}}</ref>
|-
|[[TRADIC]]
|700
|1954
|[[Bell Labs]]
|Point-contact transistors
|<ref name="computerhistory"/>
|-
|[[Manchester computers#Transistor Computer|Transistor Computer]] (full size)
|250 <!-- Neither stored program?  -->
|1955
|University of Manchester
|[[Discrete transistor|Discrete]] point-contact transistors, 1,300 diodes
|<ref name="computerhistory"/>
|-
|[[IBM 608]]
|3,000
|1955
|[[IBM]]
|[[Germanium]] transistors
|<ref>{{cite web |title=IBM 608 calculator |url=https://www.ibm.com/ibm/history/exhibits/vintage/vintage_4506VV2214.html |website=[[IBM]] |date=January 23, 2003 |access-date=8 March 2021}}</ref>
|-
|[[Electrotechnical Laboratory|ETL]] Mark III
|130 
|1956
|[[Electrotechnical Laboratory]]
|Point-contact transistors, 1,800 diodes, stored program capability 
|<ref name="computerhistory"/><ref name="etl3">{{cite web |title=ETL Mark III Transistor-Based Computer |url=http://museum.ipsj.or.jp/en/computer/dawn/0011.html |website=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |access-date=19 June 2019}}</ref>
|-
|[[Metrovick 950]]
|200
|1956
|[[Metropolitan-Vickers]]
|Discrete [[junction transistor]]s
|
|-
|[[NEC]] NEAC-2201
|600
|1958
|[[NEC]]
|[[Germanium]] transistors
|<ref>{{cite web |title=【NEC】 NEAC-2201 |url=http://museum.ipsj.or.jp/en/computer/dawn/0018.html |website=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |access-date=19 June 2019}}</ref>
|-
|[[Hitachi]] MARS-1
|1,000
|1958
|[[Hitachi]]
|
|<ref>{{cite web |title=【Hitachi and Japanese National Railways】 MARS-1 |url=http://museum.ipsj.or.jp/en/computer/dawn/0030.html |website=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |access-date=19 June 2019}}</ref>
|-
|[[IBM 7070]]
|30,000
|1958
|[[IBM]]
|[[Alloy-junction transistor|Alloy-junction]] germanium transistors, 22,000 diodes
|<ref name=DPS>[https://www.computer.org/csdl/proceedings/afips/1958/5053/00/50530165.pdf The IBM 7070 Data Processing System. Avery et al.] (page 167)</ref>
|-
|[[Matsushita Electric|Matsushita]] MADIC-I
|400
|1959
|[[Matsushita Electric|Matsushita]]
|[[Bipolar transistors]]
|<ref>{{cite web |title=【Matsushita Electric Industrial】 MADIC-I transistor-based computer |url=http://museum.ipsj.or.jp/en/computer/dawn/0066.html |website=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |access-date=19 June 2019}}</ref>
|-
|NEC NEAC-2203
|2,579
|1959
|NEC
|
|<ref>{{cite web |title=【NEC】 NEAC-2203 |url=http://museum.ipsj.or.jp/en/computer/dawn/0025.html |website=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |access-date=19 June 2019}}</ref>
|-
|[[Toshiba]] TOSBAC-2100
|5,000
|1959
|[[Toshiba]]
|
|<ref>{{cite web |title=【Toshiba】 TOSBAC-2100 |url=http://museum.ipsj.or.jp/en/computer/dawn/0022.html |website=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |access-date=19 June 2019}}</ref>
|-
|[[IBM 7090]]
|50,000
|1959
|IBM
|Discrete germanium transistors
|<ref name=IBM-7090>[https://web.archive.org/web/20050121014723/http://www-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP7090.html 7090 Data Processing System]</ref>
|-
|[[PDP-1]]
|2,700
|1959
|[[Digital Equipment Corporation]]
|[[Discrete transistor]]s
|
|-
| [[Olivetti Elea]] 9003
| ?
| 1959
| [[Olivetti]]
| 300,000 (?) [[discrete transistor]]s and diodes
| <ref>
Luigi Logrippo.
[https://www.site.uottawa.ca/~luigi/papers/elea.htm "My first two computers: Elea 9003 and Elea 6001: Memories of a 'bare-metal' programmer"].
</ref>
|-
|[[Mitsubishi]] MELCOM 1101
|3,500
|1960
|[[Mitsubishi]]
|Germanium transistors
|<ref>{{cite web |title=【Mitsubishi Electric】 MELCOM 1101 |url=http://museum.ipsj.or.jp/en/computer/dawn/0039.html |website=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |access-date=19 June 2019}}</ref>
|-
|[[M18 FADAC]]
|1,600
|1960
|[[Autonetics]]
|Discrete transistors
|
|-
|CPU of [[IBM 7030 Stretch]]
|169,100
|1961
|[[IBM]]
|World's fastest computer from 1961 to 1964
|<ref>{{cite conference
|url=http://www.bitsavers.org/pdf/ibm/7030/Bloch_EngrDesOfStretch_1959.pdf
|title=The Engineering Design of the Stretch Computer
|author=Erich Bloch
|author-link=Erich Bloch
|conference=Eastern Joint Computer Conference
|year=1959
}}</ref>
|-
|[[D-17B]]
|1,521
|1962
|Autonetics
|Discrete transistors <!-- plus "6,282 diodes, 1,116 capacitors, and 504 resistors." -->
|
|-
|NEC NEAC-L2
|16,000
|1964
|NEC
|Ge transistors
|<ref>{{cite web |title=【NEC】NEAC-L2 |url=http://museum.ipsj.or.jp/en/computer/main/0102.html |website=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |access-date=19 June 2019}}</ref>
|-
|[[CDC 6600]] (entire computer)
|400,000
|1964
|[[Control Data Corporation]]
|World's fastest computer from 1964 to 1969
|<ref>{{cite book 
|last=Thornton
|first=James
|author-link=James E. Thornton
|date=1970
|title=Design of a Computer: the Control Data 6600
|page=20
}}</ref>
|-
|[[IBM System/360]]
|?
|1964
|IBM
|[[Hybrid circuit]]s
|
|-
|[[PDP-8|PDP-8 "Straight-8"]]
|1,409<ref name="straight 8" /> <!--[[Intersil 6100|Intersil IM6100]] clone of it had 4,000-->
|1965
|[[Digital Equipment Corporation]]
|discrete transistors, 10,000 diodes
|
|-
|[[PDP-8|PDP-8/S]]
|1,001<ref>
[https://www.ricomputermuseum.org/collections-gallery/equipment/pdp-8s "Digital Equipment PDP-8/S"].
</ref><ref>
[https://retrocomputingforum.com/t/the-pdp-8-s-an-exercise-in-cost-reduction/1599 "The PDP-8/S - an exercise in cost reduction"]
</ref><ref>
[http://computermuseum.informatik.uni-stuttgart.de/dev_en/pdp8s/index.html "PDP-8/S"]
</ref>
|1966
|[[Digital Equipment Corporation]]
|discrete transistors, diodes
|
|-
|[[PDP-8|PDP-8/I]]
|1,409{{Citation needed|date=April 2022|reason=this seems to be the transistor count for the discrete-transistor "straight 8"; I expected the integrated circuit "PDP-8/I" to have roughly twice as many transistors.}} <!--[[Intersil 6100|Intersil IM6100]] clone of it had 4,000-->
|1968<ref>
[http://homepage.divms.uiowa.edu/~jones/pdp8/models/#PDP8I "The Digital Equipment Corporation PDP-8: Models and Options: The PDP-8/I"].
</ref>
|[[Digital Equipment Corporation]]
|74 series [[Transistor–transistor logic|TTL]] circuits<ref>
James F. O'Loughlin.
[http://bitsavers.org/magazines/Electronics/Electronics_V41_N19_19680916_PDP8I.pdf "PDP-8/I: bigger on the inside yet smaller on the outside"].
</ref>
|
|-
|[[Apollo Guidance Computer]] Block I
|12,300
|1966
|[[Raytheon]] / [[MIT Instrumentation Laboratory]]
|4,100 [[Integrated circuit|ICs]], each containing a 3-transistor, 3-input NOR gate. (Block II had 2,800 dual 3-input NOR gates ICs.)
|
|}

=== Logic functions ===
Transistor count for generic logic functions is based on static [[CMOS]] implementation.<ref>Jan M. Rabaey, Digital Integrated Circuits, Fall 2001: [http://bwrc.eecs.berkeley.edu/Classes/ic541ca/ic541ca%5Ff01/Notes/chapter6.pdf ''Course Notes, Chapter 6: Designing Combinatorial Logic Gates in CMOS''], retrieved October 27, 2012.</ref>

{| class="wikitable sortable" style="text-align: center;"
|-
! Function
! data-sort-type="number" | Transistor count
! class="unsortable"| Ref
|-
|[[NOT gate|NOT]]
|2
|rowspan="16" |
|-
|Buffer
|4
|-
|[[NAND gate|NAND 2-input]]
|4
|-
|[[NOR gate|NOR 2-input]]
|4
|-
|[[AND gate|AND 2-input]]
|6
|-
|[[OR gate|OR 2-input]]
|6
|-
|[[NAND gate|NAND 3-input]]
|6
|-
|[[NOR gate|NOR 3-input]]
|6
|-
|[[XOR gate|XOR 2-input]]
|6
|-
|[[XNOR gate|XNOR 2-input]]
|8
|-
|[[Digital multiplexer|MUX 2-input]] with [[Transmission gate|TG]]
|6
|-
|[[Digital multiplexer|MUX 4-input]] with [[Transmission gate|TG]]
|18
|-
|[[Digital multiplexer|NOT MUX 2-input]]
|8
|-
|[[Digital multiplexer|MUX 4-input]]
|24
|-
|1-bit [[full adder]]
|24
|-
|1-bit [[adder–subtractor]]
|48
|-
|[[AND-OR-Invert|AND-OR-INVERT]] 
|6
|<ref name="Tinder2000">{{cite book|author=Richard F. Tinder|title=Engineering Digital Design|url=https://books.google.com/books?id=C9HlLsKgIi0C|date=January 2000|publisher=Academic Press|isbn=978-0-12-691295-1}}</ref>
|-
|[[Latch (electronics)#Gated D latch|Latch, D gated]]
|8
|rowspan="2" |
|-
|[[Flip-flop (electronics)#Edge-triggered dynamic D storage element|Flip-flop, edge triggered dynamic D with reset]]
|12
|-
|8-bit multiplier
|3,000
|
|-
|16-bit multiplier
|9,000
|
|-
|32-bit multiplier
|21,000
|{{citation needed|date=June 2020}}
|-
|[[small-scale integration]]
|2–100
|<ref name="ieee_100">{{cite book |edition=7th |id=IEEE Std 100-2000 |year=2000 |doi=10.1109/IEEESTD.2000.322230 |isbn=978-0-7381-2601-2 |last1=Engineers |first1=Institute of Electrical Electronics |title=100-2000 |url=https://repositorio.unal.edu.co/handle/unal/79391 }}</ref>
|-
|[[medium-scale integration]]
|100–500
|<ref name="ieee_100" />
|-
|[[large-scale integration]]
|500–20,000
|<ref name="ieee_100" />
|-
|[[very-large-scale integration]]
|20,000–1,000,000
|<ref name="ieee_100" />
|-
|ultra-large scale integration
|>1,000,000
|
|}

=== Parallel systems ===
Historically, each processing element in earlier parallel systems—like all CPUs of that time—was a [[serial computer]] built out of multiple chips. As transistor counts per chip increases, each processing element could be built out of fewer chips, and then later each [[multi-core processor]] chip could contain more processing elements.<ref name="kevin" >
{{cite journal |first=Kevin |last=Smith |title=Image processor handles 256 pixels simultaneously |journal=Electronics |date=August 11, 1983 }}
</ref>

[[Goodyear MPP]]: (1983?) 8 pixel processors per chip, 3,000 to 8,000 transistors per chip.<ref name="kevin"/>

Brunel University Scape (single-chip array-processing element): (1983) 256 pixel processors per chip, 120,000 to 140,000 transistors per chip.<ref name="kevin" />

[[Cell Broadband Engine]]: (2006) with 9 cores per chip, had 234 million transistors per chip.<ref>
{{cite news|url=https://news.cnet.com/Cell-chip-Hit-or-hype/2010-1006_3-5568046.html|archive-url=https://web.archive.org/web/20121025113906/https://news.cnet.com/Cell-chip-Hit-or-hype/2010-1006_3-5568046.html|archive-date=2012-10-25|title=Cell chip: Hit or hype?|work=CNET News|first=Michael|last=Kanellos|date=February 9, 2005}}
</ref>

=== Other devices ===
{| class="wikitable sortable"
|-
! Device type
! Device name
! data-sort-type="number" | Transistor count
! Date of introduction
! Designer(s)
! [[Semiconductor manufacturer|Manufacturer(s)]]
! data-sort-type="number" | [[MOSFET|MOS]] [[Semiconductor device fabrication|process]]
! data-sort-type="number" | Area
! data-sort-type="number" | Transistor density, tr./mm<sup>2</sup>
! class="unsortable"| {{Abbr|Ref|Reference(s)}}
|-
|[[Deep learning]] engine / IPU{{efn|"Intelligence Processing Unit"}}
|Colossus GC2
|23,600,000,000
|2018
|[[Graphcore]]
|[[TSMC]]
|16&nbsp;nm
|~800&nbsp;mm<sup>2</sup>
|29,500,000
|<ref>{{Cite web |url=https://www.servethehome.com/hands-on-with-a-graphcore-c2-ipu-pcie-card-at-dell-tech-world/ |title=Hands-on With a Graphcore C2 IPU PCIe Card at Dell Tech World|website=servethehome.com |last=Kennedy |first=Patrick |date=June 2019 |access-date=2019-12-29}}</ref><ref>{{Cite web |url=https://en.wikichip.org/wiki/graphcore/microarchitectures/colossus |title=Colossus{{Snd}} Graphcore |website=en.wikichip.org |author=<!--Not stated--> |date=<!--Not stated--> |access-date=2019-12-29}}</ref><ref>{{Cite web |url=https://www.graphcore.ai/products/ipu |title=IPU Technology |website=www.graphcore.ai |author=Graphcore |date=<!--Not stated-->}}</ref>{{Better source needed|date=December 2019}}
|-
|[[Deep learning]] engine / IPU
|Wafer Scale Engine
|1,200,000,000,000
|2019
|Cerebras
|[[TSMC]]
|16&nbsp;nm
|46,225&nbsp;mm<sup>2</sup>
|25,960,000
|<ref name="ExtremeTech-WSE">{{Cite web|url=https://www.extremetech.com/extreme/296906-cerebras-systems-unveils-1-2-trillion-transistor-wafer-scale-processor-for-ai|title=Cerebras Systems Unveils 1.2 Trillion Transistor Wafer-Scale Processor for AI|website=extremetech.com|last=Hruska|first=Joel|date=August 2019|access-date=2019-09-06}}</ref><ref name="NextPlatform-WSE">{{Cite web|url=https://www.nextplatform.com/2019/08/21/machine-learning-chip-breaks-new-ground-with-waferscale-integration/|title=Machine Learning chip breaks new ground with waferscale integration|website=nextplatform.com|last=Feldman|first=Michael|date=August 2019|access-date=2019-09-06}}</ref><ref name="AnandTech-WSE">{{Cite web|url=https://www.anandtech.com/show/14758/hot-chips-31-live-blogs-cerebras-wafer-scale-deep-learning|title=Hot Chips 31 Live Blogs: Cerebras' 1.2 Trillion Transistor Deep Learning Processor|website=anandtech.com|last=Cutress|first=Ian|date=August 2019|access-date=2019-09-06}}</ref><ref name="WikichipFuse-WSE">{{Cite web|url=https://fuse.wikichip.org/news/3010/a-look-at-cerebras-wafer-scale-engine-half-square-foot-silicon-chip/|title=A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip|date=2019-11-16|website=WikiChip Fuse|language=en-US|access-date=2019-12-02}}</ref>
|-
|[[Deep learning]] engine / IPU
|Wafer Scale Engine 2
|2,600,000,000,000
|2020
|Cerebras
|[[TSMC]]
|7&nbsp;nm
|46,225&nbsp;mm<sup>2</sup>
|56,250,000
|<ref name=":1" /><ref>{{Cite web|title=Cerebras Unveils 2nd Gen Wafer Scale Engine: 850,000 Cores, 2.6 Trillion Transistors - ExtremeTech|url=https://www.extremetech.com/computing/322070-cerebras-unveils-2nd-gen-wafer-scale-engine-850000-cores-2-6-trillion-transistors|access-date=2021-04-22|website=www.extremetech.com|date=April 21, 2021 }}</ref><ref>{{cite web|url=https://www.servethehome.com/cerebras-wafer-scale-engine-wse-2-and-cs-2-at-hot-chips-34/|title=Cerebras Wafer Scale Engine WSE-2 and CS-2 at Hot Chips 34|website=ServeTheHome|date=2022-08-23}}</ref>
|-
|Network switch
|NVLink4 NVSwitch
|25,100,000,000
|2022
|Nvidia
|[[TSMC]]
|N4 (4&nbsp;nm)
|294&nbsp;mm<sup>2</sup>
|85,370,000
|<ref>{{cite web|url=https://www.servethehome.com/nvidia-nvlink4-nvswitch-at-hot-chips-34/|title=NVIDIA NVLink4 NVSwitch at Hot Chips 34|website=ServeTheHome|date=2022-08-22}}</ref>
|}

== Transistor density ==
The transistor density is the number of transistors that are [[Semiconductor device fabrication|fabricated]] per unit area, typically measured in terms of the number of transistors per [[square millimeter]] (mm<sup>2</sup>). The transistor density usually correlates with the [[Gate (transistor)|gate]] length of a [[semiconductor node]] (also known as a [[semiconductor manufacturing process]]), typically measured in [[nanometers]] (nm). {{As of|2019}}, the semiconductor node with the highest transistor density is TSMC's [[5 nanometer]] node, with 171.3{{nbsp}}million transistors per square millimeter (note this corresponds to a transistor-transistor spacing of 76.4&nbsp;nm, far greater than the relative meaningless "5nm")<ref name="tmsc5nm"/>

=== MOSFET nodes ===
{{Further|List of semiconductor scale examples}}

{| class="wikitable sortable"
|+ [[Semiconductor node]]s
|-
! [[Semiconductor node|Node]] name
! data-sort-type="number" | Transistor density (transistors/mm<sup>2</sup>)
! data-sort-type="number" | Production year
! data-sort-type="number" | [[Semiconductor device fabrication|Process]]
! [[MOSFET]]
! Manufacturer(s)
! class="unsortable"| {{Abbr|Ref|Reference(s)}}
|-
| {{?}}
| {{?}}
| 1960
| 20,000 [[Nanometre|nm]]
| [[PMOS logic|PMOS]]
| rowspan="2" | [[Bell Labs]]
| rowspan="2" | <ref>{{cite web |title=1960: Metal Oxide Semiconductor (MOS) Transistor Demonstrated |url=https://www.computerhistory.org/siliconengine/metal-oxide-semiconductor-mos-transistor-demonstrated/ |website=[[Computer History Museum]] |access-date=17 July 2019}}</ref><ref name="Lojek">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |pages=321–3}}</ref>
|-
| {{?}}
| {{?}}
| 1960
| 20,000&nbsp;nm
| [[NMOS logic|NMOS]]
|-
| {{?}}
| {{?}}
| 1963
| {{?}}
| [[CMOS]]
| [[Fairchild Semiconductor|Fairchild]]
| <ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |access-date=6 July 2019 |website=[[Computer History Museum]]}}</ref>
|-
| {{?}}
| {{?}}
| 1964
| {{?}}
| PMOS
| [[General Microelectronics]]
| <ref>{{cite web |title=1964: First Commercial MOS IC Introduced |url=https://www.computerhistory.org/siliconengine/first-commercial-mos-ic-introduced/ |website=[[Computer History Museum]] |access-date=17 July 2019}}</ref>
|-
| {{?}}
| {{?}}
| 1968
| 20,000&nbsp;nm
| CMOS
| [[RCA]]
| <ref name="Lojek330">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |page=330 |url=https://books.google.com/books?id=2cu1Oh_COv8C&pg=PA330}}</ref>
|-
| {{?}}
| {{?}}
| 1969
| 12,000&nbsp;nm
| PMOS
| [[Intel]]
| <ref name="stol"/><ref name="Pimbley"/>
|-
| {{?}}
| {{?}}
| 1970
| [[10 μm process|10,000&nbsp;nm]]
| CMOS
| RCA
| <ref name="Lojek330"/>
|-
| {{?}}
| {{#expr:(1024*3)/10 round -2}}
| 1970
| 8,000&nbsp;nm
| PMOS
| Intel
| <ref name="Lojek-1103"/><ref name="computerhistory1970"/>
|-
| {{?}}
| {{?}}
| 1971
| 10,000&nbsp;nm
| PMOS
| Intel
| <ref>{{cite book |last1=Lambrechts |first1=Wynand |last2=Sinha |first2=Saurabh |last3=Abdallah |first3=Jassem Ahmed |last4=Prinsloo |first4=Jaco |title=Extending Moore's Law through Advanced Semiconductor Design and Processing Techniques |date=2018 |publisher=[[CRC Press]] |isbn=9781351248655 |page=59 |url=https://books.google.com/books?id=5m5uDwAAQBAJ&pg=PT59}}</ref>
|-
| {{?}}
| {{formatnum:{{#expr:(2*1024)*3/12.7 round -1}}|}}
| 1971
| {{?}}
| PMOS
| [[General Instrument]]
| <ref name="Gealow"/>
|-
| {{?}}
| {{?}}
| 1973
| {{?}}
| NMOS
| [[Texas Instruments]]
| <ref name="Gealow"/>
|-
| {{?}}
| {{formatnum:{{#expr:(4*1024)/18.5 round -1}}|}}
| 1973
| {{?}}
| NMOS
| [[Mostek]]
| <ref name="Gealow"/>
|-
| {{?}}
| {{?}}
| 1973
| 7,500&nbsp;nm
| NMOS
| [[NEC]]
| <ref name="shmj70s"/><ref name="ucom-4"/>
|-
| {{?}}
| {{?}}
| 1973
| [[6 μm process|6,000&nbsp;nm]]
| PMOS
| [[Toshiba]]
| <ref name="shmj-1973-toshiba"/><ref>{{cite book |last1=Belzer |first1=Jack |last2=Holzman |first2=Albert G. |last3=Kent |first3=Allen |title=Encyclopedia of Computer Science and Technology: Volume 10{{Snd}} Linear and Matrix Algebra to Microorganisms: Computer-Assisted Identification |date=1978 |publisher=[[CRC Press]] |isbn=9780824722609 |page=402 |url=https://books.google.com/books?id=iBsUXrgKBKkC&pg=PA402}}</ref>
|-
| {{?}}
| {{?}}
| 1976
| 5,000&nbsp;nm
| NMOS
| [[Hitachi]], Intel
| <ref name="Gealow"/>
|-
| {{?}}
| {{?}}
| 1976
| 5,000&nbsp;nm
| CMOS
| RCA
|
|-
| {{?}}
| {{?}}
| 1976
| 4,000&nbsp;nm
| NMOS
| [[Zilog]]
|
|-
| {{?}}
| {{?}}
| 1976
| [[3 μm process|3,000&nbsp;nm]]
| NMOS
| Intel
| <ref>{{cite web|url=https://www.intel.com/pressroom/kits/quickrefyr.htm|title=Intel Microprocessor Quick Reference Guide|website=[[Intel]]|access-date=27 June 2019}}</ref>
|-
| {{?}}
| {{formatnum:{{#expr:(64*1024)/35.4 round -1}}|}}
| 1977
| {{?}}
| NMOS
| [[Nippon Telegraph and Telephone|NTT]]
| <ref name="Gealow"/>
|-
| {{?}}
| {{?}}
| 1978
| 3,000&nbsp;nm
| CMOS
| [[Hitachi]]
| <ref>{{cite web |title=1978: Double-well fast CMOS SRAM (Hitachi) |url=http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf |website=Semiconductor History Museum of Japan |access-date=5 July 2019}}</ref>
|-
| {{?}}
| {{?}}
| 1978
| 2,500&nbsp;nm
| NMOS
| [[Texas Instruments]]
| rowspan="5" | <ref name="Gealow"/>
|-
| {{?}}
| {{?}}
| 1978
| 2,000&nbsp;nm
| NMOS
| NEC, NTT
|-
| {{?}}
| {{formatnum:{{#expr:(64*1024)/25.2 round -1}}|}}
| 1979
| {{?}}
| [[VMOS]]
| [[Siemens]]
|-
| {{?}}
| {{formatnum:{{#expr:(64*1024)/9 round -1}}|}}
| 1979
| [[1 μm process|1,000&nbsp;nm]]
| NMOS
| NTT
|-
| {{?}}
| {{formatnum:{{#expr:(256*1024)/34.4 round -1}}|}}
| 1980
| 1,000&nbsp;nm
| NMOS
| NTT
|-
| {{?}}
| {{?}}
| 1983
| 2,000&nbsp;nm
| CMOS
| Toshiba
| <ref name="stol"/>
|-
| {{?}}
| {{?}}
| 1983
| [[1.5 μm process|1,500&nbsp;nm]]
| CMOS
| Intel
| rowspan="4" | <ref name="Gealow"/>
|-
| {{?}}
| {{?}}
| 1983
| 1,200&nbsp;nm
| CMOS
| Intel
|-
| {{?}}
| {{?}}
| 1984
| [[800 nanometer|800 nm]]
| CMOS
| NTT
|-
| {{?}}
| {{?}}
| 1987
| 700&nbsp;nm
| CMOS
| [[Fujitsu]]
|-
| {{?}}
| {{?}}
| 1989
| [[600 nanometer|600 nm]]
| CMOS
| [[Mitsubishi Electric|Mitsubishi]], NEC, Toshiba
| rowspan="5" | <ref name="stol"/>
|-
| {{?}}
| {{?}}
| 1989
| [[600 nm process|500 nm]]
| CMOS
| Hitachi, Mitsubishi, NEC, Toshiba
|-
| {{?}}
| {{?}}
| 1991
| 400&nbsp;nm
| CMOS
| [[Panasonic|Matsushita]], Mitsubishi, Fujitsu, Toshiba
|-
| {{?}}
| {{?}}
| 1993
| [[350 nanometer|350 nm]]
| CMOS
| [[Sony]]
|-
| {{?}}
| {{?}}
| 1993
| [[250 nanometer|250 nm]]
| CMOS
| Hitachi, NEC
|-
| 3LM
| 32,000
| 1994
| 350&nbsp;nm
| CMOS
| NEC
| <ref name="rcp"/>
|-
| {{?}}
| {{?}}
| 1995
| 160&nbsp;nm
| CMOS
| Hitachi
| rowspan="2" | <ref name="stol"/>
|-
| {{?}}
| {{?}}
| 1996
| 150&nbsp;nm
| CMOS
| [[Mitsubishi Electric|Mitsubishi]]
|-
| TSMC 180{{nbsp}}nm
| {{?}}
| 1998
| [[180 nanometer|180 nm]]
| CMOS
| [[TSMC]]
| <ref>{{cite web |title=0.18-micron Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/0.18um.htm |publisher=[[TSMC]] |access-date=30 June 2019}}</ref>
|-
| CS80
| {{?}}
| 1999
| 180&nbsp;nm
| CMOS
| Fujitsu
| <ref name="fujitsu">[http://www.fujitsu.com/downloads/MICRO/fma/pr/PressKit/65nmProcessTechnology.pdf 65nm CMOS Process Technology]</ref>
|-
| {{?}}
| {{?}}
| 1999
| [[180 nanometer|180 nm]]
| CMOS
| Intel, Sony, Toshiba
| <ref name="Intel-Product-Timeline"/><ref name="sony2003"/>
|-
| CS85
| {{?}}
| 1999
| 170&nbsp;nm
| CMOS
| Fujitsu
| <ref>[[Keith Diefendorff|Diefendorff, Keith]] (15 November 1999). "Hal Makes Sparcs Fly". ''[[Microprocessor Report]]'', Volume 13, Number 5.</ref>
|-
| Samsung 140{{nbsp}}nm
| {{?}}
| 1999
| 140&nbsp;nm
| CMOS
| [[Samsung]]
| <ref name="stol"/>
|-
| {{?}}
| {{?}}
| 2001
| [[130 nanometer|130 nm]]
| CMOS
| Fujitsu, Intel
| <ref name="fujitsu"/><ref name="Intel-Product-Timeline"/>
|-
| Samsung 100{{nbsp}}nm
| {{?}}
| 2001
| 100&nbsp;nm
| CMOS
| Samsung
| <ref name="stol"/>
|-
| {{?}}
| {{?}}
| 2002
| [[90 nanometer|90 nm]]
| CMOS
| Sony, Toshiba, Samsung
| <ref name="sony2003"/><ref name="samsung2000s"/>
|-
| CS100
| {{?}}
| 2003
| 90&nbsp;nm
| CMOS
| Fujitsu
| <ref name="fujitsu"/>
|-
| Intel 90{{nbsp}}nm
| 1,450,000
| 2004
| 90&nbsp;nm
| CMOS
| Intel
| <ref name="intel-anandtech">{{cite web |last1=Cutress |first1=Ian |title=Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review |url=https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review/3 |website=[[AnandTech]] |access-date=19 June 2019}}</ref><ref name="Intel-Product-Timeline"/>
|-
| Samsung 80{{nbsp}}nm
| {{?}}
| 2004
| 80&nbsp;nm
| CMOS
| Samsung
| <ref name="samsung2004">{{cite news|url=https://www.samsung.com/semiconductor/insights/news-events/samsung-shows-industrys-first-2-gigabit-ddr2-sdram/|title=Samsung Shows Industry's First 2-Gigabit DDR2 SDRAM|date=20 September 2004|work=[[Samsung Semiconductor]]|access-date=25 June 2019|publisher=[[Samsung]]}}</ref>
|-
| {{?}}
| {{?}}
| 2004
| [[65 nanometer|65 nm]]
| CMOS
| Fujitsu, Toshiba
| <ref>{{cite news |last1=Williams |first1=Martyn |title=Fujitsu, Toshiba begin 65nm chip trial production |url=https://www.infoworld.com/article/2667082/fujitsu--toshiba-begin-65nm-chip-trial-production.html |access-date=26 June 2019 |work=[[InfoWorld]] |date=12 July 2004}}</ref>
|-
| Samsung 60{{nbsp}}nm
| {{?}}
| 2004
| 60&nbsp;nm
| CMOS
| Samsung
| <ref name="samsung2000s"/>
|-
| TSMC 45{{nbsp}}nm
| {{?}}
| 2004
| [[45 nanometer|45 nm]]
| CMOS
| TSMC
|
|-
| Elpida 90{{nbsp}}nm
| {{?}}
| 2005
| 90&nbsp;nm
| CMOS
| [[Elpida Memory]]
| <ref>Elpida's presentation at Via Technology Forum 2005 and Elpida 2005 Annual Report</ref>
|-
| CS200
| {{?}}
| 2005
| 65&nbsp;nm
| CMOS
| Fujitsu
| <ref>{{Cite web |url=http://www.fujitsu.com/us/news/pr/fma_20050920-1.html |title=Fujitsu Introduces World-class 65-Nanometer Process Technology for Advanced Server, Mobile Applications |access-date=June 20, 2019 |archive-date=September 27, 2011 |archive-url=https://web.archive.org/web/20110927115254/http://www.fujitsu.com/us/news/pr/fma_20050920-1.html |url-status=dead }}</ref><ref name="fujitsu"/>
|-
| Samsung 50{{nbsp}}nm
| {{?}}
| 2005
| 50&nbsp;nm
| CMOS
| Samsung
| <ref name="samsung-history">{{cite web |title=History |url=https://www.samsung.com/us/aboutsamsung/company/history/ |website=[[Samsung Electronics]] |publisher=[[Samsung]] |access-date=19 June 2019}}</ref>
|-
| Intel 65{{nbsp}}nm
| 2,080,000
| 2006
| 65&nbsp;nm
| CMOS
| Intel
| <ref name="intel-anandtech"/>
|-
| Samsung 40{{nbsp}}nm
| {{?}}
| 2006
| [[40 nanometer|40 nm]]
| CMOS
| Samsung
| <ref name="samsung-history"/>
|-
| Toshiba 56{{nbsp}}nm
| {{?}}
| 2007
| 56&nbsp;nm
| CMOS
| [[Toshiba]]
| <ref name="Toshiba2007"/>
|-
| Matsushita 45{{nbsp}}nm
| {{?}}
| 2007
| 45&nbsp;nm
| CMOS
| [[Panasonic|Matsushita]]
| <ref name="panasonic2007"/>
|-
| Intel 45{{nbsp}}nm
| 3,300,000
| 2008
| 45&nbsp;nm
| CMOS
| Intel
| <ref name="intel-ieee">{{Cite web|url=https://spectrum.ieee.org/intel-now-packs-100-million-transistors-in-each-square-millimeter|title=Intel Now Packs 100 Million Transistors in Each Square Millimeter|website=IEEE Spectrum: Technology, Engineering, and Science News|date=March 30, 2017 |access-date=2018-11-14}}</ref>
|-
| Toshiba 43{{nbsp}}nm
| {{?}}
| 2008
| 43&nbsp;nm
| CMOS
| Toshiba
| <ref name="Toshiba2008"/>
|-
| TSMC 40{{nbsp}}nm
| {{?}}
| 2008
| 40&nbsp;nm
| CMOS
| TSMC
| <ref>{{cite web |title=40nm Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/40nm.htm |publisher=[[TSMC]] |access-date=30 June 2019}}</ref>
|-
| Toshiba 32{{nbsp}}nm
| {{?}}
| 2009
| [[32 nanometer|32 nm]]
| CMOS
| Toshiba 
| <ref name="toshiba2009">{{cite news|url=http://www.toshiba.co.jp/about/press/2009_02/pr1102.htm|title=Toshiba Makes Major Advances in NAND Flash Memory with 3-bit-per-cell 32nm generation and with 4-bit-per-cell 43nm technology|date=11 February 2009|work=[[Toshiba]]|access-date=21 June 2019}}</ref>
|-
| Intel 32{{nbsp}}nm
| 7,500,000
| 2010
| 32&nbsp;nm
| CMOS
| Intel
| <ref name="intel-ieee"/>
|-
| {{?}}
| {{?}}
| 2010
| [[20 nanometer|20 nm]]
| CMOS
| [[Hynix]], Samsung
| <ref name="hynix2010s">{{cite web |title=History: 2010s |url=https://www.skhynix.com/eng/about/history2010.jsp |website=[[SK Hynix]] |access-date=8 July 2019 |archive-date=April 29, 2021 |archive-url=https://web.archive.org/web/20210429202547/https://www.skhynix.com/eng/about/history2010.jsp |url-status=dead }}</ref><ref name="samsung-history"/>
|-
| Intel 22{{nbsp}}nm
| 15,300,000
| 2012
| [[22 nanometer|22 nm]]
| CMOS
| Intel
| <ref name="intel-ieee"/>
|-
| IMFT 20{{nbsp}}nm
| {{?}}
| 2012
| 20&nbsp;nm
| CMOS
| [[IM Flash Technologies|IMFT]]
| rowspan="2" | <ref>{{cite news |last1=Shimpi |first1=Anand Lal |title=SandForce Demos 19nm Toshiba & 20nm IMFT NAND Flash |url=https://www.anandtech.com/show/5960/sandforce-demos-19nm-toshiba-20nm-imft-nand-flash |access-date=19 June 2019 |work=[[AnandTech]] |date=June 8, 2012}}</ref>
|-
| Toshiba 19{{nbsp}}nm
| {{?}}
| 2012
| 19&nbsp;nm
| CMOS
| Toshiba
|-
| Hynix 16{{nbsp}}nm
| {{?}}
| 2013
| [[16 nanometer|16 nm]]
| [[FinFET]]
| [[SK Hynix]]
| <ref name="hynix2010s"/>
|-
| TSMC [[16 nanometer|16{{nbsp}}nm]]
| 28,880,000
| 2013
| 16&nbsp;nm
| FinFET
| TSMC
| <ref name="tsmc-6nm">{{Cite web|url=https://fuse.wikichip.org/news/2261/tsmc-announces-6-nanometer-process/|title=TSMC Announces 6-Nanometer Process|last=Schor|first=David|date=2019-04-16|website=WikiChip Fuse|access-date=2019-05-31}}</ref><ref>{{cite web |title=16/12nm Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/16nm.htm |publisher=[[TSMC]] |access-date=30 June 2019}}</ref>
|-
| Samsung [[10 nanometer|10{{nbsp}}nm]]
| 51,820,000
| 2013
| [[10 nanometer|10 nm]]
| FinFET
| Samsung
| <ref name="8lpp">{{Cite web|url=https://fuse.wikichip.org/news/1443/vlsi-2018-samsungs-8nm-8lpp-a-10nm-extension/|title=VLSI 2018: Samsung's 8nm 8LPP, a 10nm extension|date=2018-07-01|website=WikiChip Fuse|access-date=2019-05-31}}</ref><ref name="tomshardware">{{cite news|url=https://www.tomshardware.co.uk/NAND-128Gb-Mass-Production-3-bit-MLC,news-43458.html|title=Samsung Mass Producing 128Gb 3-bit MLC NAND Flash|date=11 April 2013|work=[[Tom's Hardware]]|access-date=21 June 2019|archive-date=June 21, 2019|archive-url=https://web.archive.org/web/20190621175628/https://www.tomshardware.co.uk/NAND-128Gb-Mass-Production-3-bit-MLC,news-43458.html|url-status=dead}}</ref>
|-
| Intel [[14 nanometer|14{{nbsp}}nm]]
| 37,500,000
| 2014
| [[14 nanometer|14 nm]]
| FinFET
| Intel
| <ref name="intel-ieee"/>
|-
| [[14 nanometer|14LP]]
| 32,940,000
| 2015
| 14&nbsp;nm
| FinFET
| Samsung
| <ref name="8lpp"/>
|-
| TSMC [[10 nanometer|10{{nbsp}}nm]]
| 52,510,000
| 2016
| 10&nbsp;nm
| FinFET
| TSMC
| <ref name="tsmc-6nm"/><ref>{{cite web |title=10nm Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/10nm.htm |publisher=[[TSMC]] |access-date=30 June 2019}}</ref>
|-
| [[Die shrink#Half-shrink|12LP]]
| 36,710,000
| 2017
| [[Die shrink#Half-shrink|12 nm]]
| FinFET
| [[GlobalFoundries]], Samsung
| <ref name="gf-samsung">{{Cite web|url=https://fuse.wikichip.org/news/1497/vlsi-2018-globalfoundries-12nm-leading-performance-12lp/|title=VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP|last=Schor|first=David|date=2018-07-22|website=WikiChip Fuse|access-date=2019-05-31}}</ref>
|-
| [[7 nanometer|N7FF]]
| 96,500,000 
101,850,000<ref name=sw_jones2020>{{cite web|url=https://semiwiki.com/semiconductor-manufacturers/intel/285192-can-tsmc-maintain-their-process-technology-lead/|title=Can TSMC maintain their process technology lead|website=SemiWiki|date=2020-04-29}}</ref>
| 2017
| [[7 nanometer|7 nm]]
| FinFET
| TSMC
| <ref name="Jones">{{cite web |last1=Jones |first1=Scotten |title=TSMC and Samsung 5nm Comparison |url=https://semiwiki.com/semiconductor-manufacturers/samsung-foundry/8157-tsmc-and-samsung-5nm-comparison/ |website=Semiwiki |date=May 3, 2019 |access-date=30 July 2019}}</ref><ref name="Nenni">{{cite web |last1=Nenni |first1=Daniel |title=Samsung vs TSMC 7nm Update |url=https://semiwiki.com/semiconductor-manufacturers/samsung-foundry/7926-samsung-vs-tsmc-7nm-update/ |website=Semiwiki |date=2019-01-02 |access-date=6 July 2019}}</ref><ref>{{cite web |title=7nm Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/7nm.htm |publisher=[[TSMC]] |access-date=30 June 2019}}</ref>
|-
| 8LPP
| 61,180,000
| 2018
| 8&nbsp;nm
| FinFET
| Samsung
| <ref name="8lpp"/>
|-
| [[7 nanometer|7LPE]]
| 95,300,000
| 2018
| 7&nbsp;nm
| FinFET
| Samsung
| <ref name="Nenni"/>
|-
| Intel [[10 nanometer|10{{nbsp}}nm]]
| 100,760,000 
106,100,000<ref name=sw_jones2020 />
| 2018
| 10&nbsp;nm
| FinFET
| Intel
| <ref>{{Cite web|url=https://fuse.wikichip.org/news/1371/a-look-at-intels-10nm-std-cell-as-techinsights-reports-on-the-i3-8121u-finds-ruthenium/|title=A Look at Intel's 10nm Std Cell as TechInsights Reports on the i3-8121U, finds Ruthenium|last=Schor|first=David|date=2018-06-15|website=WikiChip Fuse|access-date=2019-05-31}}</ref>
|-
| [[5 nanometer|5LPE]]
| 126,530,000 
133,560,000<ref name=sw_jones2020 /> 
134,900,000<ref name=sw_samsung2019>{{cite web|url=https://semiwiki.com/semiconductor-manufacturers/samsung-foundry/259664-samsung-foundry-update-2019/|title=Samsung Foundry update 2019|website=SemiWiki|date=2019-08-06}}</ref>
| 2018
| [[5 nanometer|5 nm]]
| FinFET
| Samsung
| <ref>{{citation| url =https://semiwiki.com/semiconductor/intel/7544-7nm-5nm-and-3nm-logic-current-and-projected-processes/| title = 7nm, 5nm and 3nm Logic, current and projected processes | first = Scotten|last = Jones }}</ref><ref>{{Cite web|url=https://www.anandtech.com/show/14231/samsung-completes-development-of-5-nm-euv-process-technology|title=Samsung Completes Development of 5nm EUV Process Technology|last=Shilov|first=Anton|website=[[AnandTech]]|access-date=2019-05-31}}</ref>
|-
| [[7 nanometer|N7FF+]]
| 113,900,000
| 2019
| 7&nbsp;nm
| FinFET
| TSMC
| <ref name="Jones"/><ref name="Nenni"/>
|-
| [[5 nanometer|CLN5FF]]
| 171,300,000 
185,460,000<ref name=sw_jones2020 />
| 2019
| 5&nbsp;nm
| FinFET
| TSMC
| <ref name="tmsc5nm">{{Cite web|url=https://fuse.wikichip.org/news/2207/tsmc-starts-5-nanometer-risk-production/|title=TSMC Starts 5-Nanometer Risk Production|last=Schor|first=David|date=2019-04-06|website=WikiChip Fuse|access-date=2019-04-07}}</ref>
|-
| [[7 nm process|Intel 7]]
| 100,760,000 
106,100,000<ref name=sw_jones2020 />
| 2021
| 7&nbsp;nm
| FinFET
| Intel
|
|-
| [[5 nm process|4LPE]]
| 145,700,000<ref name=sw_samsung2019 />
| 2021
| 4&nbsp;nm
| FinFET
| Samsung
| <ref name="samsung">{{cite web|url=https://news.samsung.com/global/samsung-foundry-innovations-power-the-future-of-big-data-ai-ml-and-smart-connected-devices|title=Samsung Foundry Innovations Power the Future of Big Data, AI/ML and Smart, Connected Devices|date=2021-10-07}}</ref><ref>{{cite web|url=https://www.sammobile.com/news/qualcomm-snapdragon-8-gen-1-made-using-samsung-4nm-process/|title=Qualcomm confirms Snapdragon 8 Gen 1 is made using Samsung's 4nm process|date=2021-12-02}}</ref><ref>{{cite web|url=https://9to5google.com/2022/01/14/heres-every-smartphone-confirmed-to-use-the-qualcomm-snapdragon-8-gen-1-chip/|title=List of Snapdragon 8 Gen 1 smartphones available since December 2021|work=9to5Google |date=2022-01-14 |last1=Wilde |first1=Damien }}</ref>
|-
| [[5 nm process|N4]]
| 196,600,000<ref name=sw_jones2020 /><ref name=n4p_wikichip>{{cite web|url=https://fuse.wikichip.org/news/6439/tsmc-extends-its-5nm-family-with-a-new-enhanced-performance-n4p-node/|title=TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node|website=WikiChip|date=2021-10-26}}</ref>
| 2021
| 4&nbsp;nm
| FinFET
| TSMC
| <ref>{{cite web|url=https://corp.mediatek.com/news-events/press-releases/mediatek-officially-launches-dimensity-9000-flagship-chip-and-announces-adoption-by-global-device-makers|title=MediaTek Launches Dimensity 9000 built on TSMC N4 process|date=2021-12-16}}</ref>
|-
| [[5 nm process|N4P]]
| 196,600,000<ref name=sw_jones2020 /><ref name=n4p_wikichip />
| 2022
| 4&nbsp;nm
| FinFET
| TSMC
| <ref>{{cite web|url=https://pr.tsmc.com/english/news/2874|title=TSMC Expands Advanced Technology Leadership with N4P Process (press release)|website=TSMC|date=2021-10-26}}</ref>
|-
| [[3 nm process|3GAE]]
| 202,850,000<ref name=sw_jones2020 />
| 2022
| 3&nbsp;nm
| [[MBCFET]]
| Samsung
| <ref>{{citation| url  =https://www.tomshardware.com/news/samsung-3nm-gaafet-production-2021,38426.html | title = Samsung Plans Mass Production of 3nm GAAFET Chips in 2021 | first = Lucian |last = Armasu | date = 11 January 2019| work = www.tomshardware.com }}</ref><ref name="samsung" /><ref>{{cite web|title=Samsung Starts 3nm Production: The Gate-All-Around (GAAFET) Era Begins|url=https://www.anandtech.com/print/17474/samsung-starts-3nm-production-the-gaafet-era-begins|website=AnandTech|date=2022-06-30}}</ref>
|-
| [[3 nm process|N3]]
| 314,730,000<ref name=sw_jones2020 />
| 2022
| [[3 nm process|3{{nbsp}}nm]]
| FinFET
| TSMC
| <ref>{{cite news |title=TSMC Plans New Fab for 3nm |url=https://www.eetimes.com/document.asp?doc_id=1330971 |access-date=26 September 2019 |work=[[EE Times]] |date=12 December 2016}}</ref><ref name=tsmc_rm_2021>{{Cite web|url=https://www.anandtech.com/show/17013/tsmc-update-3nm-in-q1-2023-3nm-enhanced-in-2024-2nm-in-2025|title=TSMC Roadmap Update: 3nm in Q1 2023, 3nm Enhanced in 2024, 2nm in 2025|date=2021-10-18|website=www.anandtech.com|language=en-us}}</ref>
|-
| [[5 nm process|N4X]]
| {{?}}
| 2023
| [[5 nm process|4{{nbsp}}nm]]
| FinFET
| TSMC
| <ref name=n4x_pr>{{cite web|url=https://pr.tsmc.com/english/news/2895|title=TSMC Introduces N4X Process (press release)|website=TSMC|date=2021-12-16}}</ref><ref name=n4x_blog>{{cite web|url=https://www.tsmc.com/english/news-events/blog-article-20211216|title=The Future Is Now (blog post)|website=TSMC|date=2021-12-16}}</ref><ref name=n4x_at>{{cite web|url=https://www.anandtech.com/print/17123/tsmc-unveils-n4x-node-high-voltages-for-high-clocks|title=TSMC Unveils N4X Node|website=AnandTech|date=2021-12-17}}</ref>
|-
| [[3 nm process|N3E]]
| {{?}}
| 2023
| [[3 nm process|3{{nbsp}}nm]]
| FinFET
| TSMC
| <ref name=tsmc_rm_2021 /><ref name=tsmc_rm_2022 />
|-
| [[3 nm process|3GAP]]
| {{?}}
| 2023
| 3&nbsp;nm
| [[MBCFET]]
| Samsung
| <ref name="samsung" />
|-
| [[5 nm process|Intel 4]]
| 160,000,000<ref>{{Cite web|last=Smith|first=Ryan|title=Intel 4 Process Node In Detail: 2x Density Scaling, 20% Improved Performance|url=https://www.anandtech.com/print/17448/intel-4-process-node-in-detail-2x-density-scaling-20-improved-performance|date=2022-06-13|website=AnandTech}}</ref>
| 2023
| 4&nbsp;nm
| FinFET
| Intel
| <ref>{{Cite news|last=Alcorn|first=Paul|date=24 March 2021|title=Intel Fixes 7nm, Meteor Lake and Granite Rapids Coming in 2023|work=Tom's Hardware|url=https://www.tomshardware.com/news/intel-fixes-7nm-meteor-lake-and-granite-rapids-coming-in-2023|access-date=1 June 2021}}</ref><ref name=intelrm>{{Cite web|last=Cutress|first=Dr Ian|title=Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!|url=https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros|access-date=2021-07-27|website=www.anandtech.com}}</ref><ref name=intelrm2>{{Cite web|last=Cutress|first=Dr Ian|url=https://www.anandtech.com/show/17259/intel-discloses-multigeneration-xeon-scalable-roadmap-new-ecore-only-xeons-in-2024|title=Intel Discloses Multi-Generation Xeon Scalable Roadmap: New E-Core Only Xeons in 2024|date=2022-02-17|website=www.anandtech.com}}</ref>
|-
| [[3 nm process|Intel 3]]
| {{?}}
| 2023
| 3&nbsp;nm
| FinFET
| Intel
| <ref name=intelrm /><ref name=intelrm2 />
|-
| [[Intel 20A]]
| {{?}}
| 2024
| [[2 nm process|2&nbsp;nm]]
| [[RibbonFET]]
| Intel
| <ref name=intelrm /><ref name=intelrm2 />
|-
| Intel 18A
| {{?}}
| 2025
| sub-[[2 nm process|2&nbsp;nm]]
| [[RibbonFET]]
| Intel
| <ref name=intelrm />
|-
| [[2 nm process|2GAP]]
| {{?}}
| 2025
| 2&nbsp;nm
| [[MBCFET]]
| Samsung
| <ref name="samsung" />
|-
| [[2 nm process|N2]]
| {{?}}
| 2025
| 2&nbsp;nm
| [[GAAFET]]
| TSMC
| <ref name=tsmc_rm_2021 /><ref name=tsmc_rm_2022>{{cite web|url=https://www.anandtech.com/print/17356/tsmc-roadmap-update-n3e-in-2024-n2-in-2026-major-changes-incoming|title=TSMC roadmap update|website=AnandTech|date=2022-04-22}}</ref>
|-
| Samsung 1.4&nbsp;nm
| {{?}}
| 2027
| 1.4&nbsp;nm
| {{?}}
| Samsung
| <ref>{{cite web
 |url=https://news.samsung.com/global/samsung-electronics-unveils-plans-for-1-4nm-process-technology-and-investment-for-production-capacity-at-samsung-foundry-forum-2022
 |title=Samsung Electronics Unveils Plans for 1.4nm Process Technology and Investment for Production Capacity at Samsung Foundry Forum 2022
 |website=Samsung Global Newsroom
 |date=2022-10-04}}</ref>
|}

== Gate count ==
In certain applications, the term '''gate count''' is preferred over the term transistor count. It refers to the number of [[logic gate]]s built with transistors and other electronic devices needed to implement a design.<ref>[https://journals.aps.org/pra/abstract/10.1103/PhysRevA.90.022305 Gate-count estimates for performing quantum chemistry on small quantum computers]</ref><ref>[https://csrc.nist.gov/CSRC/media/Events/lightweight-cryptography-workshop-2019/documents/papers/does-gate-count-matter-lwc2019.pdf Does gate count matter? Hardware efficiency of logic-minimization techniques for cryptographic primitives]</ref><ref>[https://ieeexplore.ieee.org/abstract/document/5537061 Quantum Algorithm for Spectral Measurement with a Lower Gate Count]</ref><ref>[https://ieeexplore.ieee.org/abstract/document/10391119 Quantum Gate Count Analysis]</ref>

== See also ==
{{div col|colwidth=20em}}
* [[Dennard scaling]]
* [[Electronics industry]]
* [[Integrated circuit]]
* [[List of best-selling electronic devices]]
* [[List of semiconductor scale examples]]
* [[MOSFET]]
* [[Semiconductor]]
* [[Semiconductor device]]
* [[Semiconductor device fabrication]]
* [[Semiconductor industry]]
* [[Transistor]]
*[[Cerebras|Cerebras Systems]]
{{div col end}}

== Notes ==
{{notelist}}

== References ==
{{reflist|30em}}

== External links ==
* [https://www.intel.com/pressroom/kits/events/moores_law_40th/ Transistor counts of Intel processors]
* [https://www.xilinx.com/company/press/kits/asmbl/asmbl_arch_pres.pdf Evolution of FPGA Architecture]

{{CPU technologies}}
{{Graphics Processing Unit}}

{{DEFAULTSORT:Transistor Count}}
[[Category:Integrated circuits]]
[[Category:MOSFETs]]
[[Category:Transistors|Count]]