View source for Toshiba TLCS

{{Short description|Prefix applied to microcontrollers made by Toshiba}}
{{More footnotes|date=July 2009}}

'''TLCS''' is a prefix applied to [[microcontroller]]s made by [[Toshiba]]. The product line includes multiple families of [[Complex instruction set computer|CISC]] and [[Reduced instruction set computer|RISC]] architectures. Individual components generally have a part number beginning with "TMP". E.g. the TMP8048AP is a member of the TLCS-48 family.{{r|TLCS-48-90|p=11}}

== TLCS-12 ==
{{See|Ford EEC}}

The TLCS-12 was a [[12-bit computing|12-bit]] [[microprocessor]] and [[central processing unit]] manufactured by Toshiba. It began development in 1971, and was completed in 1973. It was a 32{{nbsp}}mm<sup>2</sup> [[MOS integrated circuit]] chip with about 2,800 [[silicon gate]]s, [[semiconductor device fabrication|fabricated]] on a [[6 μm process]] with [[NMOS logic]]. It was used in the [[Ford EEC]] [[engine control unit]] system, which began production in 1974 and went into mass production in 1975. The [[computer memory|system memory]] included 512-bit [[random-access memory|RAM]], 2{{nbsp}}[[kibibit|kb]] [[ROM]] and 2{{nbsp}}kb [[EPROM]].<ref name="shmj-1973-toshiba">{{cite web |title=1973: 12-bit engine-control microprocessor (Toshiba) |url=http://www.shmj.or.jp/english/pdf/ic/exhibi739E.pdf |website=Semiconductor History Museum of Japan |access-date=27 June 2019}}</ref><ref name="Belzer">{{cite book |last1=Belzer |first1=Jack |last2=Holzman |first2=Albert G. |last3=Kent |first3=Allen |title=Encyclopedia of Computer Science and Technology: Volume 10 - Linear and Matrix Algebra to Microorganisms: Computer-Assisted Identification |date=1978 |publisher=[[CRC Press]] |isbn=9780824722609 |page=402 |url=https://books.google.com/books?id=iBsUXrgKBKkC&pg=PA402}}</ref> The TLCS-12A, an improved version of the TLCS-12, was announced in 1975.<ref>{{cite web |url=https://www.hpcwire.jp/archives/48576 |title=新HPCの歩み（第54回）－1975年(b)－ |accessdate=2023-11-20}}</ref>

== {{anchor|47}}TLCS-47 family ==
The microcontrollers in the TLCS-47 category are [[4-bit computing|4-bit]] systems. These are no longer advertised on the Toshiba website.

== {{anchor|48}}TLCS-48 family ==
The TLCS-48 family were clones of the [[Intel MCS-48]] (8048) microcontroller.<ref name=TLCS-48-90>{{cite book
 |title=8-Bit Microcontroller: TLCS-48, -90
 |publisher=Toshiba
 |date=November 1988
 |url=http://www.bitsavers.org/components/toshiba/_dataBook/1988_Toshiba_TLCS-48_90_8_Bit_Microcontroller.pdf
 |archive-url=https://web.archive.org/web/20200328232535/http://bitsavers.org/components/toshiba/_dataBook/1988_Toshiba_TLCS-48_90_8_Bit_Microcontroller.pdf
 |archive-date=2020-03-28
 |url-status=live
}} [https://archive.org/details/bitsavers_toshibadatCS48908BitMicrocontroller_11918240 Alt URL]</ref>

== {{anchor|Z80}}TLCS-Z80 family ==
[[File:TMPZ84C00.jpg|thumb|right|Toshiba Z84C00]]
These were a series of [[Zilog Z80]] compatible microcontrollers.

== {{anchor|90}}TLCS-90 family ==
[[File:Piggyback40 Toshiba.jpg|thumb|Development version of a TLCS-90 family microcontroller with [[EPROM]] socket]]
The microcontrollers in the TLCS-90 family use a [[8-bit computing|8-bit]]/[[16-bit computing|16-bit]] architecture reminiscent of the [[Z80]].{{r|TLCS-48-90}} These are no longer advertised on the Toshiba website.

The TLCS-90 inherits most Z80 features, such as:
* seven 8-bit registers (A, B, C, D, E, H and L),
* six 16-bit registers (BC, DE, HL, IX, IY, and SP), three of which are 8-bit register pairs,
* the combined parity/overflow flag,
* the {{code|EX DE,HL}}, {{code|EX AF,AF'}} and {{code|EXX}} 16-bit exchange instructions,{{r|TLCS-48-90|p=Appendix-2}} and
* the {{code|LDIR}} and {{code|LDDR}} memory copy instructions.

There are, however, significant differences. It omits the separate I/O address space of the Z80, but adds more flexibility to operand combinations, some new operations (notably multiply and divide), and several additional [[addressing mode]]s:
* {{code|(SP+d)}} and {{code|(HL+A)}} indexed modes operating similarly to {{code|(IX+d)}} and {{code|(IY+d)}}
* single-byte "[[zero page]]" addressing of memory from FF00&ndash;FFFF<sub>16</sub>
*{{code|(IX)}} and {{code|(IY)}}addressing without a displacement, enabling a single byte of machine code to be saved and the execution time to be decreased
*PC-relative long (-32768 to +32767 bytes from the program counter, rather than the shorter -128 to +127)
Most of the functionality of 8-bit accumulator A has also been implemented for the 16-bit HL register pair, such as the missing {{code|SUB}} and {{code|CP}} instructions, and the {{code|AND}}, {{code|XOR}}, and {{code|OR}} bitwise instructions. The {{code|ADD HL,rr}} flag quirk from the Z80 is implemented. Furthermore, the {{code|DJNZ BC,addr}}instruction was added to ease 16-bit loop counting.

TLCS-90 SoC packages include the 4-bit BX and BY registers, which get concatenated with effective addresses based on the IX or IY register, allowing the processor to address up to one [[megabyte]] of memory.{{r|TLCS-48-90|p=MPU90-16}} The processor includes the {{code|INCX ($FF00+n)}} and {{code|DECX ($FF00+n)}} instructions, which are useful for performing 20-bit pointer arithmetic using the IX and BX registers or the IY and BY registers.

Instructions are divided into one-byte basic and two-byte extended instructions. Opcodes E0<sub>16</sub> through FE<sub>16</sub> are [[Opcode prefix|prefixes]] which begin an extended instruction. The instruction encoding is unusual in that the prefix specifies one operand of the extended instruction, and unlike the single-byte prefixes used by the Z80 or [[x86]] architecture, may itself be followed by operand bytes.{{r|TLCS-48-90|p=MPU90-23,Appendix-12}}  After the prefix bytes, the second opcode byte specifies the operation and second operand.

For example, the instruction {{code|ADD (IX+127),5}} is encoded as {{code|F4 7F 68 05}}, where the first two bytes specify the destination address, the third byte specifies the operation, and the fourth byte provides the source operand.

== {{anchor|870}}TLCS-870 family ==
The microcontrollers in the TLCS-870 family (TLCS-870, TLCS-870/X, TLCS-870/C and TLCS-870/C1 series) use a [[8-bit computing|8-bit]]/[[16-bit computing|16-bit]] architecture inspired by the TLCS-90, but less like the Z80.

The TLCS-870 is the original, with a 16-bit address space, which was extended in two different directions:
* TLCS-870/X extends the architecture to 20 bits in an upward-compatible way.<ref name=mame>{{cite web
 |url=https://github.com/mamedev/mame/blob/master/src/devices/cpu/tlcs870/tlcs870d.h
 |title=MAME soure code: src/devices/cpu/tlcs870/tlcs870d.cpp
 |first=David |last=Haywood
 |website=[[GitHub]]
 |access-date=25 April 2020
}}</ref>
* TLCS-870/C retains the 16-bit address space, and provides a compatible [[assembly language]], but changes the instruction encoding{{r|mame}} so that a different [[object code]] is required.
* TLCS-870/C1 is an upward-compatible variant of the 870/C with minor extensions.<ref>{{cite web
 |url=http://www.bdtic.com/download/toshiba/870c1_cpu_book_ch4_en_090115.pdf
 |title=TLCS-870/C1 Series Instruction Set
 |publisher=Toshiba Corporation Semiconductor Company
 |date=16 December 2008
}}</ref>

== {{anchor|900|900/L|900/H|900/L1|900/H1}}TLCS-900 family ==
The TLCS-900 family inherits most features from the TLCS-90 architecture, and includes 32-bit registers and a 24-bit address bus. Most implementations (TLCS-900,<ref name=tlcs900>{{cite web
 |url=http://www.bitsavers.org/components/toshiba/_dataBook/1994_Toshiba_TLCS-900_16_Bit_Microcontroller.pdf#page=200
 |title=TLCS-900 Series 16-bit Microcontroller User's Manual
 |publisher=Toshiba corporation
 |year=1994
 |via=Bitsavers.org
}}</ref> TLCS-900/L,{{r|tlcs900}} TLCS-900/H and TLCS-900/L1 series) have [[16-bit computing|16-bit]] internal data paths, like the [[MC68000]], while the TLCS-900/H1 series is [[32-bit computing|32 bit]]s wide internally (like the [[MC68020]]).

The instruction set is mostly upward-compatible with the TLCS-90, although the binary encoding differs.{{r|tlcs900|p=182–184}} The same scheme of encoding the addressing mode before the instruction's opcode and additional operands is implemented. The early models supported both a "minimum mode" where the banked registers and [[program counter]] were 16 bits wide, and a "maximum mode" which had all 32-bit general purpose registers. Later models omitted the minimum mode.

In maximum mode, there are 4 banks of four 32-bit registers, each of which can be split into two 16-bit halves or four 8-bit quarters. In the minimum mode of early models, there are 8 banks of four 16-bit registers, which can be split into 8-bit halves. The processor can use the current bank (pointed to by the {{code|RFP}} field in the 16-bit status register SR), the previous bank to be compatible with the alternate register scheme of the TLCS-90, or any arbitrary bank number from 0 to 7. There is also a fixed set of four 32-bit registers, with one of them dedicated as the stack pointer. Early models had two separate stack pointers for user and system modes. Normally, only a set of 8 registers can be addressed from a 3-bit code; addressing all registers requires an additional 6/8-bit code byte that can only be inserted in the prefixed addressing mode operand, restricting which combinations of registers can be used for the source and destination operands.<ref name="tlcs900" />

The F register (low 8-bit half of the 16-bit register SR) has an alternate register called F'. Executing {{code|EX AF,AF'}} from the TLCS-90 requires executing both {{code|EX A,A'}} and {{code|EX F,F'}}.

The TLCS-900 also includes 4 "microDMA" transfer channels, each of which have programmable source and destination addresses, transfer counts, data sizes (byte, word, and longword), and various transfer modes. These are triggered the same way as normal interrupts, and interrupt program execution upon the transferring process.

The TLCS-900/H model was most prominently used in the [[Neo Geo Pocket]] and [[Neo Geo Pocket Color]].

== Features and differences ==
Current TLCS processors offer some or all of the following features:
* multifunction, bi-directional general purpose I/O ports with optional built-in [[pull-up resistor]]s
* [[mask programmable]], [[Programmable read-only memory|one time programmable]], [[flash memory]] or [[EEPROM]] type of ROM. [[ROMless]] versions are also available
* a variety of serial interfaces:
** [[I²C]]
** Synchronous/Asynchronous Serial Peripherals ([[UART]]/USART) (used with [[RS-232]], [[RS-485]], and more)
** [[Serial Peripheral Interface Bus]] (SPI)
** [[USB]]
* [[watchdog timer]] (WDT)
* multiplexed 10-bit [[analog-to-digital converter|A/D converters]]; [[Digital-to-analog converter|D/A converters]]
* dual clock inputs and on-line clock switching by selecting different ''gear values'' ([[frequency divider]]), thus allowing either low-power low-frequency modes or high-performance high-frequency modes
* [[Prescaler|prescalable]] 8-bit and 16-bit timers (may be used as [[Programmable Interval Timer]]s)
* 8-bit and 16-bit [[pulse-width modulation]] (PWM) and [[programmable pulse generation]] (PPG) output
* power [[voltage]] supply range between 1.8 and 5.5 [[Volt]]
* external [[interrupt]] control
* [[pattern generator]], suitable for [[stepper motor]] control
* [[Chip select|Chip select/wait]] controller
* different [[chip carrier]] formats

As demand for these features differs widely depending on the requirements for a specific project (low energy consumption; high number of I/O ports; etc.), customers can choose from a wide range of different versions.

== Development tools ==
Toshiba offers an [[ANSI C]] compatible [[C (programming language)|C]] [[compiler]] and an [[Assembly language#Assembler|assembler]]. Neither tool is available for free.

The free [[Small Device C Compiler]] supports the TLCS-90.

There is a [https://code.google.com/archive/p/tlcs900archc/ project for porting GNU assembler] to the TLCS-900 family.

Alfred Arnold's The Macroassembler AS [http://john.ccac.rwth-aachen.de:8000/as/index.html] is a free assembler supporting the TLCS-47, TLCS-870, TLCS-90, TLCS-900 and TLCS-9000 families.

== References ==
{{reflist}}

== External links ==
*[http://www.semicon.toshiba.co.jp/eng/product/micro/index.html Toshiba Japan website about the TLCS series]
*[http://www.toshiba.com/taec/Catalog/Family.do?familyid=14 Toshiba USA website about the TLCS series]

{{Microcontrollers}}

{{DEFAULTSORT:Toshiba Tlcs}}
[[Category:Microcontrollers]]
[[Category:Toshiba]]