View source for Synchronous dynamic random-access memory

{{Short description|Type of computer memory}}
{{redirect|PC100|the Japanese home computer|NEC PC-100}}
{{Memory types}}
[[File:SDRAM_memory_module.jpg|thumb|SDRAM memory modules]]
'''Synchronous dynamic random-access memory''' ('''synchronous dynamic RAM''' or '''SDRAM''') is any [[Dynamic random-access memory|DRAM]] where the operation of its external pin interface is coordinated by an externally supplied [[clock signal]].

DRAM [[integrated circuit]]s (ICs) produced from the early 1970s to the early 1990s used an ''asynchronous'' interface, in which input control signals have a direct effect on internal functions delayed only by the trip across its semiconductor pathways. SDRAM has a ''synchronous'' interface, whereby changes on control inputs are recognised after a rising edge of its clock input. In SDRAM families standardized by [[JEDEC]], the clock signal controls the stepping of an internal [[finite-state machine]] that responds to incoming commands. These commands can be pipelined to improve performance, with previously started operations completing while new commands are received. The memory is divided into several equally sized but independent sections called ''[[Memory bank|bank]]s'', allowing the device to operate on a memory access command in each bank simultaneously and speed up access in an [[Interleaved memory|interleaved]] fashion. This allows SDRAMs to achieve greater concurrency and higher data transfer rates than asynchronous DRAMs could.

[[Pipeline (computing)|Pipelining]] means that the chip can accept a new command before it has finished processing the previous one. For a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written into the memory array. For a pipelined read, the requested data appears a fixed number of clock cycles (latency) after the read command, during which additional commands can be sent.

== History ==
[[Image:SDR SDRAM-1.jpg|thumb|Eight [[Hyundai Electronics|Hyundai]] SDRAM ICs on a PC100 [[DIMM]] package]]

The earliest DRAMs were often synchronized with the CPU clock (clocked) and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.<ref>{{cite book | author=P. Darche | title=Microprocessor: Prolegomenes – Calculation and Storage Functions – Calculation Models and Computer | year=2020 | page=59 | publisher=John Wiley & Sons | isbn=9781786305633 | url=https://books.google.com/books?id=rLC9zQEACAAJ}}</ref><ref>{{cite book |author1=B. Jacob |author2=S. W. Ng |author3=D. T. Wang | title=Memory Systems: Cache, DRAM, Disk | year=2008 | publisher=Morgan Kaufmann | page=324 | isbn=9780080553849 | url=https://books.google.com/books?id=SrP3aWed-esC}}</ref> In the late 1980s [[IBM]] had built DRAMs using a [[double data rate|dual-edge clocking]] feature and presented their results at the International Solid-State Circuits Convention in 1990. However, it was standard [[DRAM]], not SDRAM.<ref>{{cite book |first1=B. |last1=Jacob |first2=S. W. |last2=Ng |first3=D. T. |last3=Wang | title=Memory Systems: Cache, DRAM, Disk | year=2008 | publisher=Morgan Kaufmann | page=333 | isbn=9780080553849 | url=https://books.google.com/books?id=SrP3aWed-esC}}</ref><ref>{{cite journal |first1=H. L. |last1=Kalter |first2=C. H. |last2=Stapper |first3=J. E. |last3=Barth |first4=J. |last4=Dilorenzo |first5=C. E. |last5=Drake |first6=J. A. |last6=Fifield |first7=G. A. |last7=Kelley |first8=S. C. |last8=Lewis |first9=W. B. |last9=van der Hoeven |first10=J. A. |last10=Jankosky | title=A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC | year=1990 | journal=IEEE Journal of Solid-State Circuits | volume=25 | issue=5| page=1118 | doi=10.1109/4.62132 | bibcode=1990IJSSC..25.1118K }}</ref>

The first commercial SDRAM was the [[Samsung]] KM48SL2000 [[memory chip]], which had a capacity of 16{{nbsp}}Mbit.<ref name="electronic-design">{{cite journal|date=1993|title=Electronic Design|url=https://books.google.com/books?id=QmpJAQAAIAAJ|journal=[[Electronic Design]]|publisher=Hayden Publishing Company|volume=41|issue=15–21|quote=The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.}}</ref> It was manufactured by [[Samsung Electronics]] using a [[CMOS]] (complementary [[metal–oxide–semiconductor]]) [[fabrication process]] in 1992,<ref name="KM48SL2000"/> and mass-produced in 1993.<ref name="electronic-design"/> By 2000, SDRAM had replaced virtually all other types of [[DRAM]] in modern computers, because of its greater performance.

SDRAM latency is not inherently lower (faster access times) than asynchronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous [[burst EDO DRAM]] due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective [[Bandwidth (computing)|bandwidth]].

[[Double data rate]] SDRAM, known as [[DDR SDRAM]], was first demonstrated by Samsung in 1997.<ref name="techpowerup">{{cite web |title=Samsung 30 nm Green PC3-12800 Low Profile 1.35 V DDR3 Review |url=https://www.techpowerup.com/review/samsung-mv-3v4g3/ |website=TechPowerUp |access-date=25 June 2019 |date= March 8, 2012}}</ref> Samsung released the first commercial DDR SDRAM chip (64{{nbsp}}Mbit{{binpre}}) in June 1998,<ref name="samsung99"/><ref name="samsung98"/><ref name="phys"/> followed soon after by [[Hyundai Electronics]] (now [[SK Hynix]]) the same year.<ref name="hynix90s"/>

Today, virtually all SDRAM is manufactured in compliance with standards established by [[JEDEC]], an electronics industry association that adopts [[open standards]] to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for [[DDR SDRAM|DDR]], [[DDR2 SDRAM|DDR2]] and [[DDR3 SDRAM]].

SDRAM is also available in [[Registered memory|registered]] varieties, for systems that require greater scalability such as [[Server (computing)|server]]s and [[workstations]].

Today, the world's largest manufacturers of SDRAM include [[Samsung Electronics]], [[SK Hynix]], [[Micron Technology]], and [[Nanya Technology]].

== Timing ==
There are several limits on DRAM performance. Most noted is the read cycle time, the time between successive read operations to an open row. This time decreased from 15&nbsp;ns for 66&nbsp;MHz SDRAM (1&nbsp;MHz = 10<sup>6</sup>&nbsp;Hz) to 5&nbsp;ns for DDR-400, but remained relatively unchanged through DDR2-800 and DDR3-1600 generations. However, by operating the interface circuitry at increasingly higher multiples of the fundamental read rate, the achievable bandwidth has increased rapidly.

Another limit is the [[CAS latency]], the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through the last few generations of DDR SDRAM.

In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15&nbsp;ns is 2–3 cycles (CL2–3) of the 200&nbsp;MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.

SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100&nbsp;MHz SDRAM chips first appeared, some manufacturers sold "100&nbsp;MHz" modules that could not reliably operate at that clock rate. In response, Intel published the PC100 standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100&nbsp;MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100&nbsp;MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (PC66, PC100 or PC133 – although the actual meaning of the numbers has changed).

== Control signals ==
All commands are timed relative to the rising edge of a clock signal. In addition to the clock, there are six control signals, mostly [[Logic level|active low]], which are sampled on the rising edge of the clock:
* '''CKE''' clock enable. When this signal is low, the chip behaves as if the clock has stopped. No commands are interpreted and command latency times do not elapse. The state of other control lines is not relevant. The effect of this signal is actually delayed by one clock cycle. That is, the current clock cycle proceeds as usual, but the following clock cycle is ignored, except for testing the CKE input again. Normal operations resume on the rising edge of the clock after the one where CKE is sampled high. Put another way, all other chip operations are timed relative to the rising edge of a masked clock. The masked clock is the logical AND of the input clock and the state of the CKE signal during the previous rising edge of the input clock.
* '''{{overline|CS}}''' chip select. When this signal is high, the chip ignores all other inputs (except for CKE), and acts as if a NOP command is received.
* '''DQM''' data mask. (The letter ''Q'' appears because, following digital logic conventions, the data lines are known as "DQ" lines.) When high, these signals suppress data I/O. When accompanying write data, the data is not actually written to the DRAM. When asserted high two cycles before a read cycle, the read data is not output from the chip. There is one DQM line per 8 bits on a x16 memory chip or DIMM.

=== Command signals ===
* '''{{overline|RAS}}''', row address strobe. Despite the name, this is ''not'' a strobe, but rather simply a command bit. Along with {{overline|CAS}} and {{overline|WE}}, this selects one of eight commands.
* '''{{overline|CAS}}''', column address strobe. This is also not a strobe, rather a command bit. Along with {{overline|RAS}} and {{overline|WE}}, this selects one of eight commands.
* '''{{overline|WE}}''', write enable. Along with {{overline|RAS}} and {{overline|CAS}}, this selects one of eight commands. It generally distinguishes read-like commands from write-like commands.

=== Bank selection (BAn) ===
SDRAM devices are internally divided into either two, four or eight independent internal data banks. One to three bank address inputs (BA0, BA1 and BA2) are used to select which bank a command is directed toward.

=== Addressing (A10/An) ===
Many commands also use an address presented on the address input pins. Some commands, which either do not use an address, or present a column address, also use A10 to select variants.

=== Commands ===
The SDR SDRAM commands are defined as follows:

{| class="wikitable" style="text-align:center"
! {{overline|CS}} || {{overline|RAS}} || {{overline|CAS}} || {{overline|WE}} || BA''n'' || A10 || A''n'' || Command
|-
|bgcolor=#ffcccc| H   ||bgcolor=lightgrey| x  ||bgcolor=lightgrey| x  ||bgcolor=lightgrey| x ||bgcolor=lightgrey| x       ||bgcolor=lightgrey| x   ||bgcolor=lightgrey| x      ||align="left"| Command inhibit (no operation)
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ffcccc| H    ||bgcolor=#ffcccc| H   ||bgcolor=lightgrey| x       ||bgcolor=lightgrey| x   ||bgcolor=lightgrey| x      ||align="left"| No operation
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L   ||bgcolor=lightgrey| x       ||bgcolor=lightgrey| x   ||bgcolor=lightgrey| x      ||align="left"| Burst terminate: stop a burst read or burst write in progress
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H   || bank    ||bgcolor=#ccffcc| L   || column ||align="left"| Read: read a burst of data from the currently active row
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H   || bank    ||bgcolor=#ffcccc| H   || column ||align="left"| Read with auto precharge: as above, and precharge (close row) when done
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L    ||bgcolor=#ccffcc| L   || bank    ||bgcolor=#ccffcc| L   || column ||align="left"| Write: write a burst of data to the currently active row
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L    ||bgcolor=#ccffcc| L   || bank    ||bgcolor=#ffcccc| H   || column ||align="left"| Write with auto precharge: as above, and precharge (close row) when done
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H    ||bgcolor=#ffcccc| H   || bank  ||colspan="2"| row ||align="left"| Active (activate): open a row for read and write commands
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L   || bank    ||bgcolor=#ccffcc| L   ||bgcolor=lightgrey| x      ||align="left"| Precharge: deactivate (close) the current row of selected bank
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L   ||bgcolor=lightgrey| x       ||bgcolor=#ffcccc| H   ||bgcolor=lightgrey| x      ||align="left"| Precharge all: deactivate (close) the current row of all banks
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ccffcc| L    ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H   ||bgcolor=lightgrey| x       ||bgcolor=lightgrey| x   ||bgcolor=lightgrey| x      ||align="left"| Auto refresh: refresh one row of each bank, using an internal counter. All banks must be precharged.
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ccffcc| L    ||bgcolor=#ccffcc| L    ||bgcolor=#ccffcc| L   || 0 0  ||colspan="2"| mode ||align="left"| Load mode register: A0 through A9 are loaded to configure the DRAM chip.<br/>The most significant settings are CAS latency (2 or 3 cycles) and burst length (1, 2, 4 or 8 cycles)
|}

All SDRAM generations (SDR and DDRx) use essentially the same commands, with the changes being:
* Additional address bits to support larger devices
* Additional bank select bits
* Wider mode registers (DDR2 and up use 13 bits, A0–A12)
* Additional extended mode registers (selected by the bank address bits)
* DDR2 deletes the burst terminate command; DDR3 reassigns it as "ZQ calibration"
* DDR3 and DDR4 use A12 during read and write command to indicate "burst chop", half-length data transfer
* [[DDR4#Command encoding|DDR4 changes the encoding]] of the activate command. A new signal {{overline|ACT}} controls it, during which the other control lines are used as row address bits 16, 15 and 14. When {{overline|ACT}} is high, other commands are the same as above.

== Construction and operation==
[[File:SDRAM_memory_module,_zoomed.jpg|thumb|SDRAM [[memory module]], zoomed]]
As an example, a 512&nbsp;MB SDRAM DIMM (which contains 512&nbsp;MB), might be made of eight or nine SDRAM chips, each containing 512&nbsp;Mbit of storage, and each one contributing 8 bits to the DIMM's 64- or 72-bit width. A typical 512&nbsp;Mbit SDRAM ''chip'' internally contains four independent 16&nbsp;MB memory banks. Each bank is an array of 8,192 rows of 16,384 bits each. (2048 8-bit columns). A bank is either idle, active, or changing from one to the other.{{binpre}}

The ''active'' command activates an idle bank. It presents a two-bit bank address (BA0&ndash;BA1) and a 13-bit row address (A0&ndash;A12), and causes a read of that row into the bank's array of all 16,384 column sense amplifiers. This is also known as "opening" the row. This operation has the side effect of [[Memory refresh|refresh]]ing the dynamic (capacitive) memory storage cells of that row.

Once the row has been activated or "opened", ''read'' and ''write'' commands are possible to that row. Activation requires a minimum amount of time, called the row-to-column delay, or t<sub>RCD</sub> before reads or writes to it may occur. This time, rounded up to the next multiple of the clock period, specifies the minimum number of wait cycles between an ''active'' command, and a ''read'' or ''write'' command. During these wait cycles, additional commands may be sent to other banks; because each bank operates completely independently.

Both ''read'' and ''write'' commands require a column address. Because each chip accesses eight bits of data at a time, there are 2,048 possible column addresses thus requiring only 11 address lines (A0&ndash;A9, A11).

When a ''read'' command is issued, the SDRAM will produce the corresponding output data on the DQ lines in time for the rising edge of the clock a few clock cycles later, depending on the configured CAS latency. Subsequent words of the burst will be produced in time for subsequent rising clock edges.

A ''write'' command is accompanied by the data to be written driven on to the DQ lines during the same rising clock edge. It is the duty of the memory controller to ensure that the SDRAM is not driving read data on to the DQ lines at the same time that it needs to drive write data on to those lines. This can be done by waiting until a read burst has finished, by terminating a read burst, or by using the DQM control line.

When the memory controller needs to access a different row, it must first return that bank's sense amplifiers to an idle state, ready to sense the next row. This is known as a "precharge" operation, or "closing" the row. A precharge may be commanded explicitly, or it may be performed automatically at the conclusion of a read or write operation. Again, there is a minimum time, the row precharge delay, t<sub>RP</sub>, which must elapse before that row is fully "closed" and so the bank is idle in order to receive another activate command on that bank.

Although refreshing a row is an automatic side effect of activating it, there is a minimum time for this to happen, which requires a minimum row access time t<sub>RAS</sub> delay between an ''active'' command opening a row, and the corresponding precharge command closing it. This limit is usually dwarfed by desired read and write commands to the row, so its value has little effect on typical performance.

== Command interactions ==
The no operation command is always permitted, while the load mode register command requires that all banks be idle, and a delay afterward for the changes to take effect. The auto refresh command also requires that all banks be idle, and takes a refresh cycle time t<sub>RFC</sub> to return the chip to the idle state. (This time is usually equal to t<sub>RCD</sub>+t<sub>RP</sub>.) The only other command that is permitted on an idle bank is the active command. This takes, as mentioned above, t<sub>RCD</sub> before the row is fully open and can accept read and write commands.

When a bank is open, there are four commands permitted: read, write, burst terminate, and precharge. Read and write commands begin bursts, which can be interrupted by following commands.

=== Interrupting a read burst ===
A read, burst terminate, or precharge command may be issued at any time after a read command, and will interrupt the read burst after the configured CAS latency. So if a read command is issued on cycle 0, another read command is issued on cycle 2, and the CAS latency is 3, then the first read command will begin bursting data out during cycles 3 and 4, then the results from the second read command will appear beginning with cycle 5.

If the command issued on cycle 2 were burst terminate, or a precharge of the active bank, then no output would be generated during cycle 5.

Although the interrupting read may be to any active bank, a precharge command will only interrupt the read burst if it is to the same bank or all banks; a precharge command to a different bank will not interrupt a read burst.

Interrupting a read burst by a write command is possible, but more difficult. It can be done if the DQM signal is used to suppress output from the SDRAM so that the memory controller may drive data over the DQ lines to the SDRAM in time for the write operation. Because the effects of DQM on read data are delayed by two cycles, but the effects of DQM on write data are immediate, DQM must be raised (to mask the read data) beginning at least two cycles before write command but must be lowered for the cycle of the write command (assuming the write command is intended to have an effect).

Doing this in only two clock cycles requires careful coordination between the time the SDRAM takes to turn off its output on a clock edge and the time the data must be supplied as input to the SDRAM for the write on the following clock edge. If the clock frequency is too high to allow sufficient time, three cycles may be required.

If the read command includes auto-precharge, the precharge begins the same cycle as the interrupting command.

== {{Anchor|BURST}} Burst ordering ==
A modern microprocessor with a [[CPU cache|cache]] will generally access memory in units of [[cache line]]s. To transfer a 64-byte cache line requires eight consecutive accesses to a 64-bit DIMM, which can all be triggered by a single read or write command by configuring the SDRAM chips, using the mode register, to perform eight-word [[Burst mode (computing)|bursts]]. A cache line fetch is typically triggered by a read from a particular address, and SDRAM allows the "critical word" of the cache line to be transferred first. ("Word" here refers to the width of the SDRAM chip or DIMM, which is 64 bits for a typical DIMM.) SDRAM chips support two possible conventions for the ordering of the remaining words in the cache line.

Bursts always access an aligned block of BL consecutive words beginning on a multiple of BL. So, for example, a four-word burst access to any column address from four to seven will return words four to seven. The ordering, however, depends on the requested address, and the configured burst type option: sequential or interleaved. Typically, a memory controller will require one or the other. When the burst length is one or two, the burst type does not matter. For a burst length of one, the requested word is the only word accessed. For a burst length of two, the requested word is accessed first, and the other word in the aligned block is accessed second. This is the following word if an even address was specified, and the previous word if an odd address was specified.

For the sequential [[Burst mode (computing)|burst mode]], later words are accessed in increasing address order, wrapping back to the start of the block when the end is reached. So, for example, for a burst length of four, and a requested column address of five, the words would be accessed in the order 5-6-7-4. If the burst length were eight, the access order would be 5-6-7-0-1-2-3-4. This is done by adding a counter to the column address, and ignoring carries past the burst length. The interleaved burst mode computes the address using an [[exclusive or]] operation between the counter and the address. Using the same starting address of five, a four-word burst would return words in the order 5-4-7-6. An eight-word burst would be 5-4-7-6-1-0-3-2.<ref>{{cite web
 | url = http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/nanya-nt5ds-datasheet.pdf#page=13
 | title = Nanya 256&nbsp;Mb DDR SDRAM Datasheet
 | date = April 2003 | access-date = 2015-08-02
 | website = intel.com
}}</ref> Although more confusing to humans, this can be easier to implement in hardware, and is preferred by [[Intel]] for its microprocessors.{{Citation needed|date=August 2015}}

If the requested column address is at the start of a block, both burst modes (sequential and interleaved) return data in the same sequential sequence 0-1-2-3-4-5-6-7. The difference only matters if fetching a cache line from memory in critical-word-first order.

== Mode register ==
Single data rate SDRAM has a single 10-bit programmable mode register. Later double-data-rate SDRAM standards add additional mode registers, addressed using the bank address pins. For SDR SDRAM, the bank address pins and address lines A10 and above are ignored, but should be zero during a mode register write.

The bits are M9 through M0, presented on address lines A9 through A0 during a load mode register cycle.
* M9: Write burst mode. If 0, writes use the read burst length and mode. If 1, all writes are non-burst (single location).
* M8, M7: Operating mode. Reserved, and must be 00.
* M6, M5, M4: CAS latency. Generally only 010 (CL2) and 011 (CL3) are legal. Specifies the number of cycles between a read command and data output from the chip. The chip has a fundamental limit on this value in nanoseconds; during initialization, the memory controller must use its knowledge of the clock frequency to translate that limit into cycles.
* M3: Burst type. 0 – requests sequential burst ordering, while 1 requests interleaved burst ordering.
* M2, M1, M0: Burst length. Values of 000, 001, 010 and 011 specify a burst size of 1, 2, 4 or 8 words, respectively. Each read (and write, if M9 is 0) will perform that many accesses, unless interrupted by a burst stop or other command. A value of 111 specifies a full-row burst. The burst will continue until interrupted. Full-row bursts are only permitted with the sequential burst type.

Later (double data rate) SDRAM standards use more mode register bits, and provide additional mode registers called "extended mode registers". The register number is encoded on the bank address pins during the load mode register command. For example, DDR2 SDRAM has a 13-bit mode register, a 13-bit extended mode register No. 1 (EMR1), and a 5-bit extended mode register No. 2 (EMR2).

== Auto refresh ==
It is possible to refresh a RAM chip by opening and closing (activating and precharging) each row in each bank. However, to simplify the memory controller, SDRAM chips support an "auto refresh" command, which performs these operations to one row in each bank simultaneously. The SDRAM also maintains an internal counter, which iterates over all possible rows. The memory controller must simply issue a sufficient number of auto refresh commands (one per row, 8192 in the example we have been using) every refresh interval (t<sub>REF</sub> = 64 ms is a common value). All banks must be idle (closed, precharged) when this command is issued.

== Low power modes ==
As mentioned, the clock enable (CKE) input can be used to effectively stop the clock to an SDRAM. The CKE input is sampled each rising edge of the clock, and if it is low, the following rising edge of the clock is ignored for all purposes other than checking CKE. As long as CKE is low, it is permissible to change the clock rate, or even stop the clock entirely.

If CKE is lowered while the SDRAM is performing operations, it simply "freezes" in place until CKE is raised again.

If the SDRAM is idle (all banks precharged, no commands in progress) when CKE is lowered, the SDRAM automatically enters power-down mode, consuming minimal power until CKE is raised again. This must not last longer than the maximum refresh interval t<sub>REF</sub>, or memory contents may be lost. It is legal to stop the clock entirely during this time for additional power savings.

Finally, if CKE is lowered at the same time as an auto-refresh command is sent to the SDRAM, the SDRAM enters self-refresh mode. This is like power down, but the SDRAM uses an on-chip timer to generate internal refresh cycles as necessary. The clock may be stopped during this time. While self-refresh mode consumes slightly more power than power-down mode, it allows the memory controller to be disabled entirely, which commonly more than makes up the difference.

SDRAM designed for battery-powered devices offers some additional power-saving options. One is temperature-dependent refresh; an on-chip temperature sensor reduces the refresh rate at lower temperatures, rather than always running it at the worst-case rate. Another is selective refresh, which limits self-refresh to a portion of the DRAM array. The fraction which is refreshed is configured using an extended mode register. The third, implemented in [[Mobile DDR]] (LPDDR) and LPDDR2 is "deep power down" mode, which invalidates the memory and requires a full reinitialization to exit from. This is activated by sending a "burst terminate" command while lowering CKE.

== {{Anchor|PREFETCH}} DDR SDRAM prefetch architecture==
DDR SDRAM employs prefetch architecture to allow quick and easy access to multiple [[data word]]s located on a common physical row in the memory.

The prefetch architecture takes advantage of the specific characteristics of memory accesses to DRAM. Typical DRAM memory operations involve three phases: [[bitline]] precharge, row access, column access. Row access is the heart of a read operation, as it involves the careful sensing of the tiny signals in DRAM memory cells; it is the slowest phase of memory operation. However, once a row is read, subsequent column accesses to that same row can be very quick, as the sense amplifiers also act as latches. For reference, a row of a 1 [[Gigabit|Gbit]]{{binpre}} [[DDR3]] device is 2,048 [[bit]]s wide, so internally 2,048 bits are read into 2,048 separate sense amplifiers during the row access phase. Row accesses might take 50 [[nanosecond|ns]], depending on the speed of the DRAM, whereas column accesses off an open row are less than 10 ns.

Traditional DRAM architectures have long supported fast column access to bits on an open row. For an 8-bit-wide memory chip with a 2,048 bit wide row, accesses to any of the 256 datawords (2048/8) on the row can be very quick, provided no intervening accesses to other rows occur.

The drawback of the older fast column access method was that a new column address had to be sent for each additional dataword on the row. The address bus had to operate at the same frequency as the data bus. Prefetch architecture simplifies this process by allowing a single address request to result in multiple data words.

In a prefetch buffer architecture, when a memory access occurs to a row the buffer grabs a set of adjacent data words on the row and reads them out ("bursts" them) in rapid-fire sequence on the IO pins, without the need for individual column address requests. This assumes the CPU wants adjacent datawords in memory, which in practice is very often the case. For instance, in DDR1, two adjacent data words will be read from each chip in the same clock cycle and placed in the pre-fetch buffer. Each word will then be transmitted on consecutive rising and falling edges of the clock cycle. Similarly, in DDR2 with a 4n pre-fetch buffer, four consecutive data words are read and placed in buffer while a clock, which is twice faster than the internal clock of DDR, transmits each of the word in consecutive rising and falling edge of the faster external clock <ref>Micron, General DDR SDRAM Functionality, Technical Note, TN-46-05</ref>

The prefetch buffer depth can also be thought of as the ratio between the core memory frequency and the IO frequency. In an 8n prefetch architecture (such as [[DDR3]]), the IOs will operate 8 times faster than the memory core (each memory access results in a burst of 8 datawords on the IOs). Thus, a 200&nbsp;MHz memory core is combined with IOs that each operate eight times faster (1600 megabits per second). If the memory has 16 IOs, the total read bandwidth would be 200&nbsp;MHz x 8 datawords/access x 16 IOs = 25.6 gigabits per second (Gbit/s) or 3.2 gigabytes per second (GB/s). Modules with multiple DRAM chips can provide correspondingly higher bandwidth.

Each generation of SDRAM has a different prefetch buffer size:

* [[DDR SDRAM]]'s prefetch buffer size is 2n (two datawords per memory access)
* [[DDR2 SDRAM]]'s prefetch buffer size is 4n (four datawords per memory access)
* [[DDR3 SDRAM]]'s prefetch buffer size is 8n (eight datawords per memory access)
* [[DDR4 SDRAM]]'s prefetch buffer size is 8n (eight datawords per memory access)
* [[DDR5 SDRAM]]'s prefetch buffer size is 8n; there is an additional mode of 16n

== Generations ==
{| class="wikitable floatright"
|+ SDRAM feature map
! scope="col" | Type
! scope="col" | Feature changes<!-- That impacts interfacing to the memory chip -->
|-
! scope="row" | SDRAM
| {{Unbulleted list
| {{Nowrap|V{{Sub|cc}} {{=}} 3.3&nbsp;V}}
| Signal: [[Transistor–transistor logic#Sub-types|LVTTL]]
}}
|-
! scope="row" | [[DDR SDRAM|DDR1]]
| {{Unbulleted list
| Access is ≥&nbsp;2 words
| [[Double data rate|Double clocked]]
| {{Nowrap|V{{Sub|cc}} {{=}} 2.5&nbsp;V}}
| {{Nowrap|2.5&nbsp;−&nbsp;7.5&nbsp;ns}} per cycle
| Signal: [[Stub Series Terminated Logic|SSTL_2]] (2.5&nbsp;V)<ref name="edn-dramconsumer">{{cite web|title=The outlook for DRAMs in consumer electronics|url=https://www.edn.com/the-outlook-for-drams-in-consumer-electronics/|last=Graham |first=Allan |publisher=AspenCore Media |website=EDN|date=2007-01-12 |access-date=2021-04-13}}</ref>
}}
|-
! scope="row" | [[DDR2 SDRAM|DDR2]]
| Access is ≥&nbsp;4 words<br/> "Burst terminate" removed<br/> 4 units used in parallel<br/> {{Nowrap|1.25&nbsp;−&nbsp;5&nbsp;ns}} per cycle<br/> Internal operations are<br>&nbsp;at 1/2 the clock rate.<br/> Signal: [[Stub Series Terminated Logic|SSTL_18]] (1.8&nbsp;V)<ref name="edn-dramconsumer"/>
|-
! scope="row" | [[DDR3 SDRAM|DDR3]]
| Access is ≥&nbsp;8 words<br/> Signal: [[Stub Series Terminated Logic|SSTL_15]] (1.5&nbsp;V)<ref name="edn-dramconsumer"/><br/> Much longer CAS latencies
|-
! scope="row" | [[DDR4 SDRAM|DDR4]]
| {{Nowrap|V{{Sub|cc}} ≤&nbsp;1.2&nbsp;V}} point-to-point<br>(single module per channel)
|}

=== SDR ===
[[Image:Micron 48LC32M8A2-AB.jpg|thumb|upright=1.25|The 64&nbsp;MB{{binpre}} of sound memory on the [[Sound Blaster X-Fi|Sound Blaster X-Fi Fatality Pro]] [[sound card]] is built from 2 [[Micron Technology|Micron]] 48LC32M8A2 SDRAM chips. They run at 133&nbsp;MHz (7.5&nbsp;ns clock period) and have 8-bit wide data buses.<!-- x8 3.3V TSOP-54 CL=3 PC133 --><ref>{{cite web|title=SDRAM Part Catalog|url=http://www.micron.com/products/dram/sdram/partlist}} 070928 micron.com</ref>]]

Originally simply known as ''SDRAM'', single data rate SDRAM can accept one command and transfer one word of data per clock cycle. Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits), but chips are generally assembled into 168-pin [[DIMM]]s that read or write 64 (non-ECC) or 72 ([[ECC memory|ECC]]) bits at a time.

Use of the data bus is intricate and thus requires a complex DRAM controller circuit. This is because data written to the DRAM must be presented in the same cycle as the write command, but reads produce output 2 or 3 cycles after the read command. The DRAM controller must ensure that the data bus is never required for a read and a write at the same time.

Typical SDR SDRAM clock rates are 66, 100, and 133&nbsp;MHz (periods of 15, 10, and 7.5&nbsp;ns), respectively denoted PC66, PC100, and PC133. Clock rates up to 200&nbsp;MHz were available. It operates at a voltage of 3.3&nbsp;V.

This type of SDRAM is slower than the DDR variants, because only one word of data is transmitted per clock cycle (single data rate). But this type is also faster than its predecessors [[extended data out DRAM]] (EDO-RAM) and [[fast page mode DRAM]] (FPM-RAM) which took typically two or three clocks to transfer one word of data.

==== PC66 ====
'''PC66''' refers to internal removable computer [[random-access memory|memory]] standard defined by the [[Joint Electron Device Engineering Council|JEDEC]]. PC66 is Synchronous DRAM operating at a clock frequency of 66.66&nbsp;MHz, on a 64-bit bus, at a voltage of 3.3&nbsp;V. PC66 is available in 168-pin [[DIMM]] and 144-pin [[SO-DIMM]] form factors. The theoretical bandwidth is 533&nbsp;MB/s. (1&nbsp;MB/s = one million bytes per second)

This standard was used by [[Original Intel Pentium (P5 microarchitecture)|Intel Pentium]] and [[AMD K6]]-based PCs. It also features in the Beige [[Power Mac G3]], early [[iBook]]s and [[PowerBook G3]]s. It is also used in many early [[Intel Celeron]] systems with a 66&nbsp;MHz [[front-side bus|FSB]]. It was superseded by the PC100 and PC133 standards.

==== PC100 ====
{{For|the Japanese home computer|NEC PC-100}}
[[Image:SDRAM 128MB 133MHz.jpg|thumb|upright=1.25|DIMM: 168 pins and two notches]]
'''PC100''' is a standard for internal removable computer [[random-access memory]], defined by the [[Joint Electron Device Engineering Council|JEDEC]]. PC100 refers to Synchronous DRAM operating at a clock frequency of 100&nbsp;MHz, on a 64-bit-wide bus, at a voltage of 3.3&nbsp;V. PC100 is available in 168-pin [[DIMM]] and 144-pin [[SO-DIMM]] [[Computer form factor|form factor]]s. PC100 is [[backward compatible]] with PC66 and was superseded by the PC133 standard.

A module built out of 100&nbsp;MHz SDRAM chips is not necessarily capable of operating at 100&nbsp;MHz. The PC100 standard specifies the capabilities of the [[memory module]] as a whole. PC100 is used in many older computers; PCs around the late 1990s were the most common computers with PC100 memory.

==== PC133 ====
'''PC133''' is a computer memory standard defined by the [[Joint Electron Device Engineering Council|JEDEC]]. PC133 refers to [[SDR SDRAM]] operating at a clock frequency of 133&nbsp;MHz, on a 64-bit-wide bus, at a voltage of 3.3&nbsp;V. PC133 is available in 168-pin [[DIMM]] and 144-pin [[SO-DIMM]] form factors. PC133 is the fastest and final SDR SDRAM standard ever approved by the JEDEC, and delivers a bandwidth of 1.066&nbsp;GB per second ([133.33&nbsp;MHz * 64/8]=1.066&nbsp;GB/s). (1&nbsp;GB/s = one billion bytes per second) PC133 is [[backward compatible]] with PC100 and PC66.

=== {{Anchor|DDR1}} DDR ===
{{Main|DDR SDRAM}}

While the access latency of DRAM is fundamentally limited by the DRAM array, DRAM has very high potential bandwidth because each internal read is actually a row of many thousands of bits. To make more of this bandwidth available to users, a [[double data rate]] interface was developed. This uses the same commands, accepted once per cycle, but reads or writes two words of data per clock cycle. The DDR interface accomplishes this by reading and writing data on both the rising and falling edges of the clock signal. In addition, some minor changes to the SDR interface timing were made in hindsight, and the supply voltage was reduced from 3.3 to 2.5&nbsp;V. As a result, DDR SDRAM is not backwards compatible with SDR SDRAM.

DDR SDRAM (sometimes called ''DDR1'' for greater clarity) doubles the minimum read or write unit; every access refers to at least two consecutive words.

Typical DDR SDRAM clock rates are 133, 166 and 200&nbsp;MHz (7.5, 6, and 5 ns/cycle), generally described as DDR-266, DDR-333 and DDR-400 (3.75, 3, and 2.5&nbsp;ns per beat). Corresponding 184-pin DIMMs are known as PC-2100, PC-2700 and PC-3200. Performance up to DDR-550 (PC-4400) is available.

=== DDR2 ===
{{Main|DDR2 SDRAM}}

DDR2 SDRAM is very similar to DDR SDRAM, but doubles the minimum read or write unit again, to four consecutive words. The bus protocol was also simplified to allow higher performance operation. (In particular, the "burst terminate" command is deleted.) This allows the bus rate of the SDRAM to be doubled without increasing the clock rate of internal RAM operations; instead, internal operations are performed in units four times as wide as SDRAM. Also, an extra bank address pin (BA2) was added to allow eight banks on large RAM chips.

Typical DDR2 SDRAM clock rates are 200, 266, 333 or 400&nbsp;MHz (periods of 5, 3.75, 3 and 2.5&nbsp;ns), generally described as DDR2-400, DDR2-533, DDR2-667 and DDR2-800 (periods of 2.5, 1.875, 1.5 and 1.25&nbsp;ns). Corresponding 240-pin DIMMs are known as PC2-3200 through PC2-6400. DDR2 SDRAM is now available at a clock rate of 533&nbsp;MHz generally described as DDR2-1066 and the corresponding DIMMs are known as PC2-8500 (also named PC2-8600 depending on the manufacturer). Performance up to DDR2-1250 (PC2-10000) is available.

Note that because internal operations are at 1/2 the clock rate, DDR2-400 memory (internal clock rate 100&nbsp;MHz) has somewhat higher latency than DDR-400 (internal clock rate 200&nbsp;MHz).

=== DDR3 ===
{{Main|DDR3 SDRAM}}

DDR3 continues the trend, doubling the minimum read or write unit to eight consecutive words. This allows another doubling of bandwidth and external bus rate without having to change the clock rate of internal operations, just the width. To maintain 800–1600&nbsp;M transfers/s (both edges of a 400–800&nbsp;MHz clock), the internal RAM array has to perform 100–200&nbsp;M fetches per second.

Again, with every doubling, the downside is the increased [[Latency (engineering)|latency]]. As with all DDR SDRAM generations, commands are still restricted to one clock edge and command latencies are given in terms of clock cycles, which are half the speed of the usually quoted transfer rate (a [[CAS latency]] of 8 with DDR3-800 is 8/(400&nbsp;MHz) = 20 ns, exactly the same latency of CAS2 on PC100 SDR SDRAM).

DDR3 memory chips are being made commercially,<ref>{{cite web|url=http://www.simmtester.com/page/news/showpubnews.asp?num=145|title=What is DDR memory?}}</ref> and computer systems using them were available from the second half of 2007,<ref>{{cite news|url=http://www.tomshardware.com/2007/06/05/pipe_dreams_six_p35-ddr3_motherboards_compared/|title=Pipe Dreams: Six P35-DDR3 Motherboards Compared |date=June 5, 2007 |author=Thomas Soderstrom |newspaper=Tom's Hardware}}</ref> with significant usage from 2008 onwards.<ref>{{cite web|url=http://news.softpedia.com/news/AMD-to-Adopt-DDR3-in-Three-Years-13486.shtml|title=AMD to Adopt DDR3 in Three Years|date=28 November 2005}}</ref> Initial clock rates were 400 and 533&nbsp;MHz, which are described as DDR3-800 and DDR3-1066 (PC3-6400 and PC3-8500 modules), but 667 and 800&nbsp;MHz, described as DDR3-1333 and DDR3-1600 (PC3-10600 and PC3-12800 modules) are now common.<ref>{{cite web|url=http://www.anandtech.com/printarticle.aspx?i=3045|archive-url=https://archive.today/20120719141605/http://www.anandtech.com/printarticle.aspx?i=3045|url-status=dead|archive-date=July 19, 2012|title=Super Talent & TEAM: DDR3-1600 Is Here! |date=July 20, 2007 |author=Wesly Fink |publisher=Anandtech}}</ref> Performance up to DDR3-2800 (PC3 22400 modules) are available.<ref>{{cite web |url=http://hothardware.com/News/GSKILL-Announces-DDR3-Memory-Kit-For-Ivy-Bridge/ |title=G.SKILL Announces DDR3 Memory Kit For Ivy Bridge |date=24 April 2012 |author=Jennifer Johnson}}</ref>

=== DDR4 ===
{{Main|DDR4 SDRAM}}

DDR4 SDRAM is the successor to [[DDR3 SDRAM]]. It was revealed at the [[Intel Developer Forum]] in San Francisco in 2008, and was due to be released to market during 2011. The timing varied considerably during its development – it was originally expected to be released in 2012,<ref>[http://intel.wingateweb.com/US08/published/sessions/MASS006/SF08_MASS006_100s.pdf DDR4 PDF page 23]</ref> and later (during 2010) expected to be released in 2015,<ref>{{cite web|url=http://www.semiaccurate.com/2010/08/16/ddr4-not-expected-until-2015/|title=DDR4 not expected until 2015|work=semiaccurate.com|date=16 August 2010}}</ref> before samples were announced in early 2011 and manufacturers began to announce that commercial production and release to market was anticipated in 2012. DDR4 reached mass market adoption around 2015, which is comparable with the approximately five years taken for DDR3 to achieve mass market transition over DDR2.

The DDR4 chips run at 1.2&nbsp;[[Volt|V]] or less,<ref>{{cite web|url=http://www.pcpro.co.uk/news/220257/idf-ddr3-wont-catch-up-with-ddr2-during-2009.html|title=IDF: "DDR3 won't catch up with DDR2 during 2009"|work=Alphr}}</ref><ref>{{cite web|url=http://www.heise-online.co.uk/news/IDF-DDR4-the-successor-to-DDR3-memory--/111367|title=heise online – IT-News, Nachrichten und Hintergründe|work=heise online}}</ref> compared to the 1.5&nbsp;V of DDR3 chips, and have in excess of 2 billion [[data transfer]]s per second. They were expected to be introduced at frequency rates of 2133&nbsp;MHz, estimated to rise to a potential 4266&nbsp;MHz<ref>{{cite web |url=http://www.xbitlabs.com/news/memory/display/20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report.html |title=Next-Generation DDR4 Memory to Reach 4.266GHz – Report |date=August 16, 2010 |publisher=Xbitlabs.com |access-date=2011-01-03 |url-status=dead |archive-url=https://web.archive.org/web/20101219085440/http://www.xbitlabs.com/news/memory/display/20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report.html |archive-date=December 19, 2010 }}</ref> and lowered voltage of 1.05&nbsp;V<ref>{{cite news|url=http://www.hardware-infos.com/news.php?news=2332|title=IDF: DDR4 memory targeted for 2012|publisher=hardware-infos.com|language=de|access-date=2009-06-16|archive-url=https://web.archive.org/web/20090713025046/http://www.hardware-infos.com/news.php?news=2332|archive-date=2009-07-13|url-status=dead}}</ref> by 2013.

DDR4 did ''not'' double the internal prefetch width again, but uses the same 8''n'' prefetch as DDR3.<ref name="jedec_ddr3_ddr4">{{cite press release |url=http://www.jedec.org/news/pressreleases/jedec-announces-key-attributes-upcoming-ddr4-standard |title=JEDEC Announces Key Attributes of Upcoming DDR4 Standard |publisher=[[JEDEC]] |date=2011-08-22 |access-date=2011-01-06}}</ref> Thus, it will be necessary to interleave reads from several banks to keep the data bus busy.

In February 2009, [[Samsung]] validated 40&nbsp;nm DRAM chips, considered a "significant step" towards DDR4 development<ref>{{cite news |url=http://www.tgdaily.com/content/view/41316/139/ |title=Samsung hints to DDR4 with first validated 40&nbsp;nm DRAM |last=Gruener |first=Wolfgang |date=February 4, 2009 |publisher=tgdaily.com |access-date=2009-06-16 |url-status=dead |archive-url=https://web.archive.org/web/20090524133306/http://www.tgdaily.com/content/view/41316/139/ |archive-date=May 24, 2009 }}</ref> since, as of 2009, current DRAM chips were only beginning to migrate to a 50&nbsp;nm process.<ref>{{cite web |url=http://www.dailytech.com/DDR3+Will+be+Cheaper+Faster+in+2009/article13977.htm |title=DDR3 Will be Cheaper, Faster in 2009 |last=Jansen |first=Ng |date=January 20, 2009 |publisher=dailytech.com |access-date=2009-06-17 |url-status=dead |archive-url=https://web.archive.org/web/20090622084614/http://www.dailytech.com/DDR3+Will+be+Cheaper+Faster+in+2009/article13977.htm |archive-date=June 22, 2009 }}</ref> In January 2011, [[Samsung]] announced the completion and release for testing of a 30&nbsp;nm 2048&nbsp;MB{{binpre}} DDR4 DRAM module. It has a maximum bandwidth of 2.13&nbsp;[[Gbit/s]] at 1.2&nbsp;V, uses [[pseudo open drain]] technology and draws 40% less power than an equivalent DDR3 module.<ref>{{cite web |title=Samsung Develops Industry's First DDR4 DRAM, Using 30nm Class Technology |url=http://www.samsung.com/us/business/semiconductor/newsView.do?news_id=1202 |publisher=Samsung |access-date=2011-03-13 |date=2011-01-04}}</ref><ref>{{cite web |url=http://www.techspot.com/news/41818-samsung-develops-ddr4-memory-up-to-40-more-efficient.html |title=Samsung develops DDR4 memory, up to 40% more efficient |work=TechSpot|date=4 January 2011 }}</ref>

=== DDR5 ===
{{Main|DDR5 SDRAM}}

In March 2017, JEDEC announced a DDR5 standard is under development,<ref>{{cite press release |title=JEDEC DDR5 & NVDIMM-P Standards Under Development |url=https://www.jedec.org/news/pressreleases/jedec-ddr5-nvdimm-p-standards-under-development |date=30 March 2017 |publisher=[[JEDEC]]}}</ref> but provided no details except for the goals of doubling the bandwidth of DDR4, reducing power consumption, and publishing the standard in 2018. The standard was released on 14 July 2020.<ref name="anandtech-ddr5">{{cite web|url=https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond|archive-url=https://web.archive.org/web/20200714225042/https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond|url-status=dead|archive-date=July 14, 2020|title=DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond|last=Smith|first=Ryan|date=2020-07-14|website=AnandTech|access-date=2020-07-15}}</ref>

== Failed successors ==
In addition to DDR, there were several other proposed memory technologies to succeed SDR SDRAM.

=== Rambus DRAM (RDRAM) ===
[[RDRAM]] was a proprietary technology that competed against DDR. Its relatively high price and disappointing performance (resulting from high latencies and a narrow 16-bit data channel versus DDR's 64 bit channel) caused it to lose the race to succeed SDR SDRAM.

=== Synchronous-link DRAM (SLDRAM) ===
SLDRAM boasted higher performance and competed against RDRAM. It was developed during the late 1990s by the SLDRAM Consortium. The SLDRAM Consortium consisted of about 20 major DRAM and computer industry manufacturers. (The SLDRAM Consortium became incorporated as SLDRAM Inc. and then changed its name to Advanced Memory International, Inc.) SLDRAM was an [[open standard]] and did not require licensing fees. The specifications called for a 64-bit bus running at a 200, 300 or 400&nbsp;MHz clock frequency. This is achieved by all signals being on the same line and thereby avoiding the synchronization time of multiple lines. Like [[DDR SDRAM]], SLDRAM uses a double-pumped bus, giving it an effective speed of 400,<ref>{{Citation |url=http://www.tomshardware.com/reviews/ram-guide,89-15.html |title=RAM Guide: SLDRAM |author=Dean Kent |publisher=Tom's Hardware |date=1998-10-24 |access-date=2011-01-01}}</ref> 600,<ref>{{Citation |url=http://icwic.cn/icwic/data/pdf/cd/cd011/12452.pdf |title=HYSL8M18D600A 600 Mb/s/pin 8M x 18 SLDRAM |type=data sheet |author=Hyundai Electronics |date=1997-12-20 |access-date=2011-12-27 |archive-url=https://web.archive.org/web/20120426081302/http://icwic.cn/icwic/data/pdf/cd/cd011/12452.pdf |archive-date=2012-04-26 |url-status=dead }}</ref> or 800&nbsp;[[MT/s]]. (1&nbsp;MT/s&nbsp;=&nbsp;1000<sup>2</sup> transfers per second)

SLDRAM used an 11-bit command bus (10 command bits CA9:0 plus one start-of-command FLAG line) to transmit 40-bit command packets on 4 consecutive edges of a differential command clock (CCLK/CCLK#). Unlike SDRAM, there were no per-chip select signals; each chip was assigned an ID when reset, and the command contained the ID of the chip that should process it. Data was transferred in 4- or 8-word bursts across an 18-bit (per chip) data bus, using one of two differential data clocks (DCLK0/DCLK0# and DCLK1/DCLK1#). Unlike standard SDRAM, the clock was generated by the data source (the SLDRAM chip in the case of a read operation) and transmitted in the same direction as the data, greatly reducing data skew. To avoid the need for a pause when the source of the DCLK changes, each command specified which DCLK pair it would use.<ref>{{Citation |url=http://icwic.cn/icwic/data/pdf/cd/cd011/12407.pdf |pages=32–33 |title=SLD4M18DR400 400 Mb/s/pin 4M x 18 SLDRAM |type=data sheet |author=SLDRAM Inc. |date=1998-07-09 |access-date=2011-12-27 |archive-url=https://web.archive.org/web/20120426081159/http://icwic.cn/icwic/data/pdf/cd/cd011/12407.pdf |archive-date=2012-04-26 |url-status=dead }}</ref>

The basic read/write command consisted of (beginning with CA9 of the first word):
{|class="wikitable" style="text-align:center"
|+ SLDRAM Read, write or row op request packet
! FLAG || CA9 || CA8 || CA7 || CA6 || CA5 || CA4 || CA3 || CA2 || CA1 || CA0
|-
! 1 
|colspan="9" bgcolor="#FFCCCC"| Device ID 8:0 ||bgcolor="#CCFFCC"| Co...
|-
! 0 
|colspan="5" bgcolor="#ccffcc"| ...mmand Code 5:0 ||colspan="3" bgcolor="#eeAAff"| Bank Addr. 2:0 ||colspan="2" bgcolor="#ffffcc"| Ro...
|-
! 0 
|colspan=9 bgcolor=#ffffcc| ...w Address 11:0 ||bgcolor=white| 0
|-
! 0 
|colspan="3" bgcolor="white"| 0 0 0 ||colspan="7" bgcolor="#ccffff"| Column address 6:0
|}

* 9 bits of Device ID
* 6 bits of Command Code
* 3 bits of Bank address
* 10 or 11 bits of row address
* 5 or 4 bits spare for row or column expansion
* 7 bits of column address

Individual devices had 8-bit IDs. The 9th bit of the ID sent in commands was used to address multiple devices. Any aligned power-of-2 sized group could be addressed. If the transmitted msbit was set, all least-significant bits up to and including the least-significant 0 bit of the transmitted address were ignored for "is this addressed to me?" purposes. (If the ID8 bit is actually considered less significant than ID0, the unicast address matching becomes a special case of this pattern.)

A read/write command had the msbit clear:
* CMD5=0
* CMD4=1 to open (activate) the specified row; CMD4=0 to use the currently open row
* CMD3=1 to transfer an 8-word burst; CMD3=0 for a 4-word burst
* CMD2=1 for a write, CMD2=0 for a read
* CMD1=1 to close the row after this access; CMD1=0 to leave it open
* CMD0 selects the DCLK pair to use (DCLK1 or DCLK0)

A notable omission from the specification was per-byte write enables; it was designed for systems with [[CPU cache|cache]]s and [[ECC memory]], which always write in multiples of a cache line.

Additional commands (with CMD5 set) opened and closed rows without a data transfer, performed refresh operations, read or wrote configuration registers, and performed other maintenance operations. Most of these commands supported an additional 4-bit sub-ID (sent as 5 bits, using the same multiple-destination encoding as the primary ID) which could be used to distinguish devices that were assigned the same primary ID because they were connected in parallel and always read/written at the same time.

There were a number of 8-bit control registers and 32-bit status registers to control various device timing parameters.

=== Virtual channel memory (VCM) SDRAM ===
VCM was a proprietary type of SDRAM that was designed by [[NEC]], but released as an open standard with no licensing fees. It is pin-compatible with standard SDRAM, but the commands are different. The technology was a potential competitor of [[RDRAM]] because VCM was not nearly as expensive as RDRAM was. A Virtual Channel Memory (VCM) module is mechanically and electrically compatible with standard SDRAM, so support for both depends only on the capabilities of the [[memory controller]]. In the late 1990s, a number of PC [[Northbridge (computing)|northbridge]] chipsets (such as the popular [[List of VIA chipsets#Slot A and Socket A|VIA KX133 and KT133]]) included VCSDRAM support.

VCM inserts an SRAM cache of 16 "channel" buffers, each 1/4 row "segment" in size, between DRAM banks' sense amplifier rows and the data I/O pins. "Prefetch" and "restore" commands, unique to VCSDRAM, copy data between the DRAM's sense amplifier row and the channel buffers, while the equivalent of SDRAM's read and write commands specify a channel number to access. Reads and writes may thus be performed independent of the currently active state of the DRAM array, with the equivalent of four full DRAM rows being "open" for access at a time. This is an improvement over the two open rows possible in a standard two-bank SDRAM. (There is actually a 17th "dummy channel" used for some operations.)

To read from VCSDRAM, after the active command, a "prefetch" command is required to copy data from the sense amplifier array to the channel SDRAM. This command specifies a bank, two bits of column address (to select the segment of the row), and four bits of channel number. Once this is performed, the DRAM array may be precharged while read commands to the channel buffer continue. To write, first the data is written to a channel buffer (typically previous initialized using a Prefetch command), then a restore command, with the same parameters as the prefetch command, copies a segment of data from the channel to the sense amplifier array.

Unlike a normal SDRAM write, which must be performed to an active (open) row, the VCSDRAM bank must be precharged (closed) when the restore command is issued. An active command immediately after the restore command specifies the DRAM row completes the write to the DRAM array. There is, in addition, a 17th "dummy channel" which allows writes to the currently open row. It may not be read from, but may be prefetched to, written to, and restored to the sense amplifier array.<ref>{{Citation |url=https://www.notebookservice030.de/downloads/docs/HYB39V64x0yT.pdf |archive-url=https://web.archive.org/web/20181112021502/https://www.notebookservice030.de/downloads/docs/HYB39V64x0yT.pdf |archive-date=2018-11-12 |url-status=live |title=HYB39V64x0yT 64MBit Virtual Channel SDRAM |author=Siemens Semiconductor Group }}</ref><ref>{{Citation |url=http://www.ic72.com/pdf_file/u/32271.pdf |archive-url=https://web.archive.org/web/20131203022329/http://www.ic72.com/pdf_file/u/32271.pdf |archive-date=2013-12-03 |url-status=live |title=128M-BIT VirtualChannel SDRAM preliminary datasheet |author=NEC |year=1999 |access-date=2012-07-17}}</ref>

Although normally a segment is restored to the same memory address as it was prefetched from, the channel buffers may also be used for very efficient copying or clearing of large, aligned memory blocks. (The use of quarter-row segments is driven by the fact that DRAM cells are narrower than SRAM cells.) The SRAM bits are designed to be four DRAM bits wide, and are conveniently connected to one of the four DRAM bits they straddle.) Additional commands prefetch a pair of segments to a pair of channels, and an optional command combines prefetch, read, and precharge to reduce the overhead of random reads.

The above are the JEDEC-standardized commands. Earlier chips did not support the dummy channel or pair prefetch, and use a different encoding for precharge.

A 13-bit address bus, as illustrated here, is suitable for a device up to 128&nbsp;Mbit{{binpre}}. It has two banks, each containing 8,192 rows and 8,192 columns. Thus, row addresses are 13 bits, segment addresses are two bits, and eight column address bits are required to select one byte from the 2,048 bits (256 bytes) in a segment.

== {{Anchor|SGRAM}}Synchronous Graphics RAM (SGRAM) ==
Synchronous graphics RAM (SGRAM) is a specialized form of SDRAM for graphics adaptors. It is designed for graphics-related tasks such as [[texture memory]] and [[framebuffer]]s, found on [[video card]]s. It adds functions such as [[bit mask]]ing (writing to a specified bit plane without affecting the others) and block write (filling a block of memory with a single colour). Unlike [[Video RAM (dual-ported DRAM)|VRAM]] and [[WRAM (memory)|WRAM]], SGRAM is single-ported. However, it can open two memory pages at once, which simulates the [[Dual-ported RAM|dual-port]] nature of other video RAM technologies.

The earliest known SGRAM memory are 8{{nbsp}}Mbit{{binpre}} chips dating back to 1994: the [[Hitachi]] HM5283206, introduced in November 1994,<ref name="HM5283206"/> and the [[NEC]] μPD481850, introduced in December 1994.<ref name="D481850"/> The earliest known commercial device to use SGRAM is [[Sony]]'s [[PlayStation (console)|PlayStation]] (PS) [[video game console]], starting with the Japanese [[PlayStation models|SCPH-5000]] model released in December 1995, using the NEC μPD481850 chip.<ref>{{cite web |title=PU-18 |url=http://wiki.psxdev.ru/index.php/PU-18 |website=PSXDEV |access-date=10 July 2019}}</ref><ref name="nec1995"/>

Compared to SDRAM which is byte-accessible, SGRAM is block-accessible.<ref>{{Cite web| title=Highest-Performance, Highest-Bandwidth GDDR6 | url=https://assets.micron.com/adobe/assets/urn:aaid:aem:d5533dc7-d0ed-4fb2-a784-2208c94e7a9b/renditions/original/as/gddr6-product-flyer.pdf | archive-url=https://web.archive.org/web/20250603162904/https://assets.micron.com/adobe/assets/urn:aaid:aem:d5533dc7-d0ed-4fb2-a784-2208c94e7a9b/renditions/original/as/gddr6-product-flyer.pdf | archive-date=2025-06-03}}</ref>

=== Graphics double data rate SDRAM (GDDR SDRAM) ===
{{Main|GDDR SDRAM}}

Graphics [[double data rate]] SDRAM ([[GDDR SDRAM]]) is a type of specialized [[DDR SDRAM]] designed to be used as the main memory of [[graphics processing unit]]s (GPUs). GDDR SDRAM is distinct from commodity types of DDR SDRAM such as DDR3, although they share some core technologies. Their primary characteristics are higher clock frequencies for both the DRAM core and I/O interface, which provides greater memory bandwidth for GPUs. As of 2025, there are nine successive generations of GDDR: [[GDDR2]], [[GDDR3]], [[GDDR4]], [[GDDR5]], [[GDDR5X]], [[GDDR6]], [[GDDR6X]], [[GDDR6W]], and [[GDDR7]].

GDDR was initially known as DDR SGRAM. It was commercially introduced as a 16{{nbsp}}[[Megabit|Mbit]]{{binpre}} memory chip by [[Samsung Electronics]] in 1998.<ref name="samsung98"/>

== High Bandwidth Memory (HBM) ==
{{Main|High Bandwidth Memory}}

[[High Bandwidth Memory]] (HBM) is a high-performance RAM interface for [[three-dimensional integrated circuit|3D-stacked]] SDRAM from [[Samsung Electronics|Samsung]], [[Advanced Micro Devices|AMD]] and [[SK Hynix]]. It is designed to be used in conjunction with high-performance graphics accelerators and network devices.<ref>[http://isscc.org/doc/2014/2014_Trends.pdf ISSCC 2014 Trends] {{webarchive|url=https://web.archive.org/web/20150206093927/http://isscc.org/doc/2014/2014_Trends.pdf |date=2015-02-06 }} page&nbsp;118 "High-Bandwidth DRAM"</ref> The first HBM memory chip was produced by SK Hynix in 2013.<ref name="hynix2010s"/>

== Timeline ==
{{See also|Random-access memory#Timeline|Flash memory#Timeline|Transistor count#Memory}}{{Update section|date=December 2023|reason=Advances in DDR5 need to be included}}

=== SDRAM ===
<section begin="SDRAM timeline"/>
{| class="wikitable sortable" style="text-align:center; white-space:nowrap;"
|+ Synchronous dynamic random-access memory (SDRAM)
|-
! style="line-height:110%"|Date of<br>intro-<br>duction
! Chip<br>name
! Capacity<br>([[bit]]s){{binpre|first}}
! SDRAM<br>type
! Manufac-<br>turer(s)
! data-sort-type="number" |[[Semiconductor device fabrication|Pro-<br>cess]]
! [[MOSFET|MOS-<br>FET]]
! data-sort-type="number" | Area<br>(mm<sup>2</sup>)
! {{Abbr|Ref|Reference(s)}}
|-
|1992
|KM48SL2000
|16 [[Megabit|Mbit]]
|[[SDR SDRAM|SDR]]
|[[Samsung Electronics|Samsung]]
|style="color:#AAAAAA"| ''?''
|[[CMOS]]
|style="color:#AAAAAA"| ''?''
|<ref name="KM48SL2000">{{cite web |title=KM48SL2000-7 Datasheet |url=https://www.datasheetarchive.com/KM48SL2000-7-datasheet.html |publisher=[[Samsung]] |access-date=19 June 2019 |date=August 1992}}</ref><ref name="electronic-design"/>
|-
|rowspan="3" |1996
|MSM5718C50
|18 Mbit
|[[RDRAM]]
|[[Oki Electric Industry|Oki]]
|style="color:#AAAAAA"| ''?''
|CMOS
|325
|<ref name="oki-rdram">{{cite web |title=MSM5718C50/MD5764802 |url=https://retrocdn.net/images/c/c3/Oki_Concurrent_RDRAM_datasheet.pdf |archive-url=https://web.archive.org/web/20190621151518/https://retrocdn.net/images/c/c3/Oki_Concurrent_RDRAM_datasheet.pdf |archive-date=2019-06-21 |url-status=live |publisher=[[Oki Electric Industry|Oki Semiconductor]] |date=February 1999 |access-date=21 June 2019}}</ref>
|-
|[[Nintendo 64 technical specifications|N64 RDRAM]]
|36 Mbit
|RDRAM
|[[NEC]]
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref>{{cite magazine|title=Ultra 64 Tech Specs|magazine=[[Next Generation (magazine)|Next Generation]]|issue=14 |publisher=[[Imagine Media]] |date=February 1996|page=40}}</ref>
|-
|style="color:#AAAAAA"| ''?''
|1024 Mbit
|SDR
|[[Mitsubishi Electric|Mitsubishi]]
|[[180 nanometer|150&nbsp;nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="stol">{{cite web|url=http://maltiel-consulting.com/Semiconductor_technology_memory.html|title=Memory|website=STOL (Semiconductor Technology Online)|access-date=25 June 2019}}</ref>
|-
|1997
|style="color:#AAAAAA"| ''?''
|1024 Mbit
|SDR
|[[Hyundai Electronics|Hyundai]]
|style="color:#AAAAAA"| ''?''
|[[Silicon on insulator|SOI]]
|style="color:#AAAAAA"| ''?''
|<ref name="hynix90s">{{cite web |title=History: 1990s |url=http://www.az5miao.com/history1990.html |access-date=4 April 2022 |website=az5miao}}</ref>
|-
|1998
|MD5764802
|64 Mbit
|RDRAM
|Oki
|style="color:#AAAAAA"| ''?''
|CMOS
|325
|<ref name="oki-rdram"/>
|-
|{{sort|1998|Mar&nbsp;1998}}
|Direct RDRAM
|72 Mbit
|RDRAM
|[[Rambus]]
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref>{{cite web |title=Direct RDRAM |url=https://retrocdn.net/images/6/68/Direct_RDRAM_datasheet.pdf |archive-url=https://web.archive.org/web/20190621151523/https://retrocdn.net/images/6/68/Direct_RDRAM_datasheet.pdf |archive-date=2019-06-21 |url-status=live |publisher=[[Rambus]] |date=12 March 1998 |access-date=21 June 2019}}</ref>
|-
|{{sort|1998|Jun&nbsp;1998}}
|style="color:#AAAAAA"| ''?''
|64 Mbit
|[[DDR SDRAM|DDR]]
|Samsung
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="samsung98">{{cite news |title=Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-comes-out-with-super-fast-16m-ddr-sgrams/ |access-date=23 June 2019 |work=[[Samsung Electronics]] |publisher=[[Samsung]] |date=17 September 1998}}</ref><ref name="samsung99">{{cite news |title=Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-develops-first-128mb-sdram-with-ddr-sdr-manufacturing-option/ |access-date=23 June 2019 |work=[[Samsung Electronics]] |publisher=[[Samsung]] |date=10 February 1999}}</ref><ref name="phys">{{cite news |title=Samsung Demonstrates World's First DDR 3 Memory Prototype |url=https://phys.org/news/2005-02-samsung-world-ddr-memory-prototype.html |access-date=23 June 2019 |work=[[Phys.org]] |date=17 February 2005 |language=en-us}}</ref>
|-
| rowspan="2" |1998
| rowspan="2" style="color:#AAAAAA"| ''?''
|64 Mbit
|DDR
|Hyundai
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="hynix90s"/>
|-
|128 Mbit
|SDR
|Samsung
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="samsung-history">{{cite web |title=History |url=https://www.samsung.com/us/aboutsamsung/company/history/ |website=[[Samsung Electronics]] |publisher=[[Samsung]] |access-date=19 June 2019}}</ref><ref name="samsung99"/>
|-
| rowspan="2" |1999
| rowspan="2" style="color:#AAAAAA"| ''?''
|128 Mbit
|DDR
|Samsung
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="samsung99"/>
|-
|1024 Mbit
|DDR
|Samsung
|[[130 nanometer|140 nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="stol"/>
|-
|2000
|[[PlayStation 2 technical specifications|GS eDRAM]]
|32 Mbit
|[[eDRAM]]
|[[Sony]], [[Toshiba]]
|[[180 nm]]
|CMOS
|279
|<ref name="sony2003">{{cite news |title=EMOTION ENGINE AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION BECOME ONE CHIP |url=https://www.sie.com/content/dam/corporate/en/corporate/release/pdf/030421be.pdf |archive-url=https://web.archive.org/web/20170227150247/https://www.sie.com/content/dam/corporate/en/corporate/release/pdf/030421be.pdf |archive-date=2017-02-27 |url-status=live |access-date=26 June 2019 |publisher=[[Sony]] |date=April 21, 2003}}</ref>
|-
| rowspan="2" |2001
| rowspan="2" style="color:#AAAAAA"| ''?''
|288 Mbit
|RDRAM
|Hynix
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="hynix2000s">{{cite web |title=History: 2000s |url=http://www.az5miao.com/history2000.html |access-date=4 April 2022 |website=az5miao}}</ref>
|-
|style="color:#AAAAAA"| ''?''
|[[DDR2 SDRAM|DDR2]]
|Samsung
|[[100 nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="phys"/><ref name="stol"/>
|-
|2002
|style="color:#AAAAAA"| ''?''
|256 Mbit
|SDR
|Hynix
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="hynix2000s"/>
|-
| rowspan="5" |2003
|[[PlayStation 2 technical specifications|EE+GS eDRAM]]
|32 Mbit
|eDRAM
|Sony, Toshiba
|[[90 nm]]
|CMOS
|{{0}}86
|<ref name="sony2003"/>
|-
| rowspan="4" style="color:#AAAAAA"| ''?''
|72 Mbit
|[[DDR3]]
|Samsung
|90&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref>{{cite news |title=Samsung Develops the Industry's Fastest DDR3 SRAM for High Performance EDP and Network Applications |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-develops-the-industrys-fastest-ddr3-sram-for-high-performance-edp-and-network-applications/ |access-date=25 June 2019 |work=[[Samsung Semiconductor]] |publisher=[[Samsung]] |date=29 January 2003}}</ref>
|-
| rowspan="2" |512 Mbit
| rowspan="2" |DDR2
|Hynix
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="hynix2000s"/>
|-
|[[Elpida Memory|Elpida]]
|[[110 nanometer|110 nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref>{{cite news |title=Elpida ships 2GB DDR2 modules |url=https://www.theinquirer.net/inquirer/news/1044210/elpida-ships-2gb-ddr2-modules |archive-url=https://web.archive.org/web/20190710115030/https://www.theinquirer.net/inquirer/news/1044210/elpida-ships-2gb-ddr2-modules |url-status=unfit |archive-date=July 10, 2019 |access-date=25 June 2019 |work=[[The Inquirer]] |date=4 November 2003}}</ref>
|-
|1024 Mbit
|DDR2
|Hynix
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="hynix2000s"/>
|-
|2004
|style="color:#AAAAAA"| ''?''
|2048 Mbit
|DDR2
|Samsung
|80&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="samsung2004">{{cite news |title=Samsung Shows Industry's First 2-Gigabit DDR2 SDRAM |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-shows-industrys-first-2-gigabit-ddr2-sdram/ |access-date=25 June 2019 |work=[[Samsung Semiconductor]] |publisher=[[Samsung]] |date=20 September 2004}}</ref>
|-
| rowspan="3" |2005
|[[PlayStation 2 technical specifications|EE+GS eDRAM]]
|32 Mbit
|eDRAM
|Sony, Toshiba
|[[65 nm]]
|CMOS
|{{0}}86
|<ref name="impress">{{cite web|url=https://pc.watch.impress.co.jp/docs/2003/0421/sony1.htm|title=ソニー、65nm対応の半導体設備を導入。3年間で2,000億円の投資|website=pc.watch.impress.co.jp|url-status=live|archive-url=https://web.archive.org/web/20160813020249/http://pc.watch.impress.co.jp/docs/2003/0421/sony1.htm|archive-date=2016-08-13}}</ref>
|-
|[[Xenos (graphics chip)|Xenos eDRAM]]
|80 Mbit
|eDRAM
|NEC
|90&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref>ATI engineers by way of Beyond 3D's Dave Baumann</ref>
|-
|style="color:#AAAAAA"| ''?''
|512 Mbit
|DDR3
|Samsung
|80&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="phys"/><ref name="samsung2000s">{{cite web |title=Our Proud Heritage from 2000 to 2009 |url=https://www.samsung.com/semiconductor/about-us/history-03/ |website=[[Samsung Semiconductor]] |publisher=[[Samsung]] |access-date=25 June 2019}}</ref>
|-
|2006
|style="color:#AAAAAA"| ''?''
|1024 Mbit
|DDR2
|Hynix
|60&nbsp;nm
|rowspan="2" | CMOS
|rowspan="2" style="color:#AAAAAA"| ''?''
|rowspan="2" | <ref name="hynix2000s"/>
|-
|2008
|style="color:#AAAAAA"| ''?''
|style="color:#AAAAAA"| ''?''
|[[LPDDR2]]
|Hynix
|style="color:#AAAAAA"| ''?''
|-
|{{sort|2008|Apr&nbsp;2008}}
|style="color:#AAAAAA"| ''?''
|8192 Mbit
|DDR3
|Samsung
|50&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|rowspan="2" | <ref>{{cite news |title=Samsung 50nm 2GB DDR3 chips are industry's smallest |url=https://www.slashgear.com/samsung-50nm-2gb-ddr3-chips-are-industrys-smallest-2917676/ |access-date=25 June 2019 |work=SlashGear |date=29 September 2008}}</ref>
|-
|2008
|style="color:#AAAAAA"| ''?''
|16384 Mbit
|DDR3
|Samsung
|50&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|-
| rowspan="2" |2009
| rowspan="2" style="color:#AAAAAA"| ''?''
|style="color:#AAAAAA"| ''?''
|DDR3
|Hynix
|[[45 nanometer|44 nm]]
|rowspan="2" | CMOS
|rowspan="2" style="color:#AAAAAA"| ''?''
|rowspan="2" | <ref name="hynix2000s"/>
|-
|2048 Mbit
|DDR3
|Hynix
|[[40 nanometer|40 nm]]
|-
| rowspan="2" |2011
| rowspan="2" style="color:#AAAAAA"| ''?''
|16384 Mbit
|DDR3
|Hynix
|40&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="hynix2010s">{{cite web |title=History: 2010s |url=http://www.az5miao.com/history2010.html |website=az5miao |access-date=4 April 2022}}</ref>
|-
|2048 Mbit
|[[DDR4]]
|Hynix
|[[32 nanometer|30&nbsp;nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="hynix2010s"/>
|-
|2013
|style="color:#AAAAAA"| ''?''
|style="color:#AAAAAA"| ''?''
|[[LPDDR4]]
|Samsung
|[[20 nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="hynix2010s"/>
|-
|2014
|style="color:#AAAAAA"| ''?''
|8192 Mbit
|LPDDR4
|Samsung
|20&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref>{{cite web |title=Our Proud Heritage from 2010 to Now |url=https://www.samsung.com/semiconductor/about-us/history-04/ |website=[[Samsung Semiconductor]] |publisher=[[Samsung]] |access-date=25 June 2019}}</ref>
|-
|2015
|style="color:#AAAAAA"| ''?''
|12 Gbit
|LPDDR4
|Samsung
|20&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="samsung-history"/>
|-
| rowspan="2" |2018
| rowspan="2" style="color:#AAAAAA"| ''?''
|8192 Mbit
|[[LPDDR#LP-DDR5|LPDDR5]]
|Samsung
|[[10 nm process|10 nm]]
|[[FinFET]]
|style="color:#AAAAAA"| ''?''
|<ref>{{cite news |title=Samsung Electronics Announces Industry's First 8Gb LPDDR5 DRAM for 5G and AI-powered Mobile Applications |url=https://news.samsung.com/global/samsung-electronics-announces-industrys-first-8gb-lpddr5-dram-for-5g-and-ai-powered-mobile-applications |access-date=8 July 2019 |publisher=[[Samsung]] |date=July 17, 2018}}</ref>
|-
|128 Gbit
|DDR4
|Samsung
|10&nbsp;nm
|FinFET
|style="color:#AAAAAA"| ''?''
|<ref>{{cite news |date=6 September 2018 |title=Samsung Unleashes a Roomy DDR4 256GB RAM |work=[[Tom's Hardware]] |url=https://www.tomshardware.co.uk/samsung-256gb-ddr4-ram,news-59123.html |url-status=dead |access-date=4 April 2022 |archive-url=https://web.archive.org/web/20190621205106if_/https://www.tomshardware.co.uk/samsung-256gb-ddr4-ram,news-59123.html |archive-date=June 21, 2019}}</ref>
|}

=== SGRAM ===
{| class="wikitable sortable" style="text-align:center"
|+ [[Synchronous graphics random-access memory]] (SGRAM)
|-
! Date of introduction
! Chip name
! Capacity ([[bit]]s){{binpre}}
! SDRAM type
! Manufacturer(s)
! data-sort-type="number" |[[Semiconductor device fabrication|Process]]
! [[MOSFET]]
! data-sort-type="number" | Area
! {{Abbr|Ref|Reference(s)}}
|-
|{{sort|1994|November 1994}}
|HM5283206
|8 Mbit
|[[SGRAM]] ([[SDR SDRAM|SDR]])
|[[Hitachi]]
|[[350 nm]]
|[[CMOS]]
|58&nbsp;mm<sup>2</sup>
|<ref name="HM5283206">{{cite book |title=HM5283206 Datasheet |url=https://www.datasheetarchive.com/pdf/download.php?id=d740571591400628c124d16f943c9f96145441&type=M&term=HM5283206 |publisher=[[Hitachi]] |date=11 November 1994 |access-date=10 July 2019}}</ref><ref>{{cite web |title=Hitachi HM5283206FP10 8Mbit SGRAM |url=http://smithsonianchips.si.edu/ice/cd/9702_529.pdf |archive-url=https://web.archive.org/web/20030716101100/http://smithsonianchips.si.edu/ice/cd/9702_529.pdf |archive-date=2003-07-16 |url-status=live |website=[[Smithsonian Institution]] |access-date=10 July 2019}}</ref>
|-
|{{sort|1994|December 1994}}
|μPD481850
|8 Mbit
|SGRAM (SDR)
|[[NEC]]
|{{?}}
|CMOS
|280&nbsp;mm<sup>2</sup>
|<ref name="D481850">{{cite book |title=μPD481850 Datasheet |url=https://www.datasheetarchive.com/pdf/download.php?id=96dd7345eb44f58adee424725f8fa65f48c794&type=O |publisher=[[NEC]] |date=6 December 1994 |access-date=10 July 2019}}</ref><ref name="nec1995">{{cite book |title=NEC Application Specific Memory |date=Fall 1995 |publisher=[[NEC]] |page=[https://archive.org/details/bitsavers_necdataBoonSpecificMemory_23148799/page/n365 359] |url=https://archive.org/details/bitsavers_necdataBoonSpecificMemory_23148799 |access-date=21 June 2019}}</ref>
|-
|1997
|μPD4811650
|16 Mbit
|SGRAM (SDR)
|NEC
|350&nbsp;nm
|CMOS
|280&nbsp;mm<sup>2</sup>
|<ref>{{cite book |title=UPD4811650 Datasheet |url=https://www.datasheetarchive.com/pdf/download.php?id=74d301b62a3253e6f3e4ff722cad1e9cb1ac90&type=P |publisher=[[NEC]] |date=December 1997 |access-date=10 July 2019}}</ref><ref>{{cite journal |last1=Takeuchi |first1=Kei |title=16M-BIT SYNCHRONOUS GRAPHICS RAM: μPD4811650 |journal=NEC Device Technology International |date=1998 |issue=48 |url=https://www.datasheetarchive.com/pdf/download.php?id=5fde91b774d1f298423c9d3ae6982f843a4df7&type=P |access-date=10 July 2019}}</ref>
|-
|{{sort|1998|September 1998}}
|{{?}}
|16 Mbit
|SGRAM ([[GDDR]])
|[[Samsung Electronics|Samsung]]
|{{?}}
|CMOS
|{{?}}
|<ref name="samsung98"/>
|-
|1999
|KM4132G112
|32 Mbit
|SGRAM (SDR)
|Samsung
|{{?}}
|CMOS
|280&nbsp;mm<sup>2</sup>
|<ref>{{cite news |title=Samsung Announces the World's First 222 MHz 32Mbit SGRAM for 3D Graphics and Networking Applications |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-announces-the-worlds-first-222-mhz-32mbit-sgram-for-3d-graphics-and-networking-application/ |access-date=10 July 2019 |work=[[Samsung Semiconductor]] |publisher=[[Samsung]] |date=12 July 1999}}</ref>
|-
|2002
|{{?}}
|128 Mbit
|SGRAM ([[GDDR2]])
|Samsung
|{{?}}
|CMOS
|{{?}}
|<ref name="samsung2003">{{cite news |title=Samsung Electronics Announces JEDEC-Compliant 256Mb GDDR2 for 3D Graphics |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-announces-jedec-compliant-256mb-gddr2-for-3d-graphics/ |access-date=26 June 2019 |work=[[Samsung Electronics]] |publisher=[[Samsung]] |date=28 August 2003}}</ref>
|-
|rowspan="2" | 2003
|rowspan="2" | {{?}}
|rowspan="2" | 256 Mbit
|SGRAM (GDDR2)
|rowspan="2" | Samsung
|rowspan="2" | {{?}}
|rowspan="2" | CMOS
|rowspan="2" | {{?}}
|rowspan="2" | <ref name="samsung2003"/>
|-
|SGRAM ([[GDDR3]])
|-
|{{sort|2005|March 2005}}
|K4D553238F
|256 Mbit
|SGRAM (GDDR)
|Samsung
|{{?}}
|CMOS
|77&nbsp;mm<sup>2</sup>
|<ref>{{cite web |title=K4D553238F Datasheet |url=https://www.datasheetarchive.com/pdf/download.php?id=cbbd25bf58d1232267a54268161c1af804dc2f&type=P |publisher=[[Samsung Electronics]] |date=March 2005 |access-date=10 July 2019}}</ref>
|-
|{{sort|2005|October 2005}}
|{{?}}
|256 Mbit
|SGRAM ([[GDDR4]])
|Samsung
|{{?}}
|CMOS
|{{?}}
|<ref>{{cite web |title=Samsung Electronics Develops Industry's First Ultra-Fast GDDR4 Graphics DRAM |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-develops-industrys-first-ultra-fast-gddr4-graphics-dram/ |website=[[Samsung Semiconductor]] |publisher=[[Samsung]] |access-date=8 July 2019 |date=October 26, 2005}}</ref>
|-
|2005
|{{?}}
|512 Mbit
|SGRAM (GDDR4)
|[[Hynix]]
|{{?}}
|rowspan="3" | CMOS
|rowspan="3" | {{?}}
|rowspan="3" | <ref name="hynix2000s"/>
|-
|2007
|{{?}}
|1024 Mbit
|SGRAM ([[GDDR5]])
|Hynix
|[[65 nanometer|60&nbsp;nm]]
|-
|2009
|{{?}}
|2048 Mbit
|SGRAM (GDDR5)
|Hynix
|[[45 nanometer|40&nbsp;nm]]
|-
|2010
|K4W1G1646G
|1024 Mbit
|SGRAM (GDDR3)
|Samsung
|{{?}}
|CMOS
|100&nbsp;mm<sup>2</sup>
|<ref>{{cite web |title=K4W1G1646G-BC08 Datasheet |url=https://www.datasheet.directory/index.php?title=Special:PdfViewer&url=https%3A%2F%2Fdatasheet.iiic.cc%2Fdatasheets-1%2Fsamsung_semiconductor_division%2FK4W1G1646G-BC08.pdf |archive-url=https://web.archive.org/web/20220124234650/https://datasheet.iiic.cc/datasheets-1/samsung_semiconductor_division/K4W1G1646G-BC08.pdf |archive-date=2022-01-24 |url-status=live |publisher=[[Samsung Electronics]] |date=November 2010 |access-date=10 July 2019}}</ref>
|-
|2012
|{{?}}
|4096 Mbit
|SGRAM (GDDR3)
| [[SK Hynix]]
| {{?}}
| CMOS
| {{?}}
| <ref name="hynix2010s"/>
|-
|{{sort|2016|March 2016}}
|MT58K256M32JA
|8 Gbit
|SGRAM ([[GDDR5X]])
|[[Micron Technology|Micron]]
|20&nbsp;nm
|CMOS
|140&nbsp;mm<sup>2</sup>
|<ref>{{cite news |last1=Shilov |first1=Anton |title=Micron Begins to Sample GDDR5X Memory, Unveils Specs of Chips |url=https://www.anandtech.com/show/10193/micron-begins-to-sample-gddr5x-memory |archive-url=https://web.archive.org/web/20160330094652/http://www.anandtech.com/show/10193/micron-begins-to-sample-gddr5x-memory |url-status=dead |archive-date=March 30, 2016 |access-date=16 July 2019 |work=[[AnandTech]] |date=March 29, 2016}}</ref>
|-
|{{sort|2018|January 2018}}
|K4ZAF325BM
|16 Gbit
|SGRAM ([[GDDR6]])
|Samsung
|[[10 nm process|10 nm]]
|[[FinFET]]
|225&nbsp;mm<sup>2</sup>
|<ref>{{cite news |title=Samsung Electronics Starts Producing Industry's First 16-Gigabit GDDR6 for Advanced Graphics Systems |url=https://news.samsung.com/global/samsung-electronics-starts-producing-industrys-first-16-gigabit-gddr6-for-advanced-graphics-systems |access-date=15 July 2019 |publisher=[[Samsung]] |date=January 18, 2018}}</ref><ref name='tr_gddr6'>{{cite news|last1=Killian|first1=Zak|title=Samsung fires up its foundries for mass production of GDDR6 memory|url=https://techreport.com/news/33129/samsung-fires-up-its-foundries-for-mass-production-of-gddr6-memory|access-date=18 January 2018|publisher=Tech Report|date=18 January 2018}}</ref><ref>{{cite news |title=Samsung Begins Producing The Fastest GDDR6 Memory In The World |url=https://wccftech.com/samsung-gddr6-16gb-18gbps-mass-production-official/ |access-date=16 July 2019 |work=Wccftech |date=18 January 2018}}</ref>
|} <section end="SDRAM timeline"/>

=== HBM ===
{| class="wikitable sortable" style="text-align:center"
|+ [[High Bandwidth Memory]] (HBM)
|-
! Date of introduction
! Chip name
! Capacity ([[bit]]s){{binpre}}
! SDRAM type
! Manufacturer(s)
! data-sort-type="number" |[[Semiconductor device fabrication|Process]]
! [[MOSFET]]
! data-sort-type="number" | Area
! {{Abbr|Ref|Reference(s)}}
|-
|2013
|{{?}}
|{{?}}
|[[High Bandwidth Memory|HBM]]
|[[SK Hynix]]
|{{?}}
|CMOS
|{{?}}
|<ref name="hynix2010s" />
|-
|{{sort|2016|June 2016}}
|{{?}}
|32 Gbit
|[[HBM2]]
|Samsung
|[[20 nm]]
|CMOS
|{{?}}
|<ref name="Shilov2017">{{cite news |last1=Shilov |first1=Anton |date=July 19, 2017 |title=Samsung Increases Production Volumes of 8 GB HBM2 Chips Due to Growing Demand |url=https://www.anandtech.com/show/11643/samsung-increases-8gb-hbm2-production-volume |archive-url=https://web.archive.org/web/20170720000946/http://anandtech.com/show/11643/samsung-increases-8gb-hbm2-production-volume |url-status=dead |archive-date=July 20, 2017 |access-date=29 June 2019 |work=[[AnandTech]]}}</ref><ref>{{cite web |title=HBM |url=https://samsungsemiconductor-us.com/hbm/ |access-date=16 July 2019 |website=[[Samsung Semiconductor]] |publisher=[[Samsung]]}}</ref>
|-
|2017
|{{?}}
|64 Gbit
|HBM2
|Samsung
|20&nbsp;nm
|CMOS
|{{?}}
|<ref name="Shilov2017" />
|}
== See also ==
* [[GDDR]] (graphics DDR) and its subtypes [[GDDR2]], [[GDDR3]], [[GDDR4]], [[GDDR5]], [[GDDR6]] and [[GDDR7]]
* [[List of device bandwidths]]
* [[Serial presence detect]] – EEPROM with timing data on SDRAM modules
* [http://taututorial.yolasite.com/ SDRAM Tutorial] – Flash website built by Tel-Aviv University students
* A concise but thorough review of SDRAM architecture/terminology and command timing dependencies in [http://drum.lib.umd.edu/bitstream/1903/11269/1/Gross_umd_0117N_11844.pdf High-Performance DRAM System Design Constraints and Considerations], a master thesis from the University of Maryland.

== References ==
{{Reflist}}

== External links ==
* [https://web.archive.org/web/20121016082506/http://www.anandtech.com/show/3851 Everything you always wanted to know about SDRAM (memory), but were afraid to ask], August 2010, [[AnandTech]]
* [http://www.hardwaresecrets.com/understanding-ram-timings/ Understanding RAM Timings], May 2011, Hardware Secrets
* [https://web.archive.org/web/20030803094457/http://developer.intel.com/technology/memory/pc133sdram/spec/sdram133.pdf PC SDRAM Specification, Rev 1.7]
* [https://web.archive.org/web/20030429115837/http://developer.intel.com/technology/memory/pc133sdram/spec/PC133sodm1_0c1.pdf 133&nbsp;MHz PC133 SDRAM SO-DIMM Specification]
* [https://web.archive.org/web/20030803113813/http://developer.intel.com/technology/memory/pc133sdram/spec/Spdsd12b.pdf PC SDRAM Serial Presence Detect (SPD) Specification, Rev 1.2B]

{{DRAM}}

{{DEFAULTSORT:Sdram (Synchronous Dynamic Random Access Memory)}}
[[Category:Synchronous dynamic random-access memory| ]]
[[Category:South Korean inventions]]