View source for Silicon on insulator

{{short description|Technology in semiconductor manufacturing}}
{{Hatnote|For silicon on insulator optical devices, see [[Silicon photonics]].}}
In [[semiconductor manufacturing]], '''silicon on insulator''' ('''SOI''') technology is fabrication of [[silicon]] semiconductor devices in a layered silicon–insulator–silicon [[substrate (materials science)|substrate]], to reduce [[parasitic capacitance]] within the device, thereby improving performance.<ref name="celler">{{cite journal |last1=Celler |first1=G. K. |last2=Cristoloveanu |first2=S. |title=Frontiers of silicon-on-insulator |journal=[[Journal of Applied Physics]] |volume=93 |issue=9 |page=4955 |year=2003 |doi=10.1063/1.1558223 |bibcode=2003JAP....93.4955C }}</ref> SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an [[electrical insulator]], typically [[silicon dioxide]] or [[sapphire]] (these types of devices are called [[silicon on sapphire]], or SOS). The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short-channel effects in other microelectronics devices.<ref>{{cite book |title=SOI design: analog, memory and digital techniques |first1=Andrew |last1=Marshall |first2=Sreedhar |last2=Natarajan |year=2002 |publisher=Kluwer |isbn=0-7923-7640-4}}</ref> The insulating layer and topmost silicon layer also vary widely with application.<ref>{{cite book |title=Silicon-on-Insulator Technology: Materials to VLSI |first=Jean-Pierre |last=Colinge |publisher=Springer |year=1991 |isbn=978-0-7923-9150-0}}</ref>

==Industry need==
SOI technology is one of several manufacturing strategies to allow the continued miniaturization of [[microelectronic]] devices, colloquially referred to as "extending [[Moore's law]]" (or "more moore", abbreviated "MM"). Reported benefits of SOI relative to conventional silicon ([[bulk CMOS]]) processing include:<ref>
{{cite web |first=Horacio  |last=Mendez |title=Silicon-on-insulator — SOI technology and ecosystem — Emerging SOI applications |date=April 2009 |publisher=SOI Industry Consortium |url=http://www.soiconsortium.org/pdf/Consortium_9april09_final.pdf }}</ref>
*Lower parasitic capacitance due to isolation from the [[bulk silicon]], which improves power consumption at matched performance
*Resistance to [[latchup]] due to complete isolation of the n- and p-well structures
*Higher performance at equivalent [[IC power-supply pin|VDD]]. Can work at low VDDs<ref>{{cite web |first=Narayan M. |last=Kodeti |title=Silicon On Insulator (SOI) Implementation |date=October 2010 |work=White Paper |publisher=Infotech |url=http://www.infotech-enterprises.com/fileadmin/infotech-enterprises.com/assets/downloads/White_Papers/Infotech_SOI_Paper_Oct_2010.pdf|archive-url=https://web.archive.org/web/20130418043957/http://www.infotech-enterprises.com/fileadmin/infotech-enterprises.com/assets/downloads/White_Papers/Infotech_SOI_Paper_Oct_2010.pdf |archive-date=2013-04-18 }}</ref>
*Reduced temperature dependency due to no doping
*Better yield due to high density, better wafer utilization
*Reduced antenna issues
*No body or well taps are needed
*Lower leakage currents due to isolation thus higher power efficiency
*Inherently [[radiation hardening#Physical|radiation hardened]] (resistant to soft errors), reducing the need for redundancy

From a manufacturing perspective, SOI substrates are compatible with most conventional fabrication processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel [[metrology]] requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The threshold voltage of the transistor depends on the history of operation and applied voltage to it, thus making modeling harder. The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10&ndash;15% increase to total manufacturing costs.<ref>{{cite web|url=https://www.cnet.com/news/ibm-touts-chipmaking-technology/|title=IBM touts chipmaking technology|date=29 March 2001|website=cnet.com|access-date=22 April 2018}}</ref>{{additional citation needed|date=June 2018}} FD-SOI (fully depleted silicon on insulator) has been seen as a potential low cost alternative to FinFETs.<ref>{{cite web | url=https://www.eetimes.com/samsung-gf-ramp-fd-soi/ | title=Samsung, GF Ramp FD-SOI | date=27 April 2018 }}</ref>

==SOI transistors==
{{MOS|section|date=August 2023}}
An SOI MOSFET is a [[metal–oxide–semiconductor field-effect transistor]] (MOSFET) device in which a [[semiconductor]] layer such as silicon or [[germanium]] is formed on an insulator layer which may be a buried oxide (BOX) layer formed in a semiconductor substrate.<ref>{{cite patent |first= |last= |title=SOI wafers with 30-100 Ang. Buried OX created by wafer bonding using 30-100 Ang. thin oxide as bonding layer |country=US |number=6835633 |url=}}</ref><ref>{{cite patent |first= |last= |title=Ultra-thin body super-steep retrograde well (SSRW) FET devices |country=US |number=7002214 |url=}}</ref><ref>{{cite journal |author=Yang-Kyu Choi |last2=Asano |first2=K. |last3=Lindert |first3=N. |last4=Subramanian |first4=V. |author5=Tsu-Jae King |last6=Bokor |first6=J. |author7=Chenming Hu |title=Ultrathin-body SOI MOSFET for deep-sub-tenth micron era |journal=IEEE Electron Device Letters |volume=21 |issue=5 |pages=254–5 |date=May 2000 |doi=10.1109/IEDM.1999.824298 |s2cid=43561939 |url=http://www-device.eecs.berkeley.edu/~viveks/Papers/254EDL21.pdf}}</ref> SOI MOSFET devices are adapted for use by the computer industry.{{Citation needed|date=October 2008}} The buried oxide layer can be used in [[static random-access memory|SRAM]] designs.<ref>{{cite patent |first= |last= |title=Vertical MOSFET SRAM cell |country=US |number=7138685 |url=}} describes SOI buried oxide (BOX) structures and methods for implementing enhanced SOI BOX structures</ref> There are two types of SOI devices: PDSOI (partially depleted SOI) and FDSOI (fully depleted SOI) MOSFETs. For an n-type PDSOI MOSFET the sandwiched n-type film between the gate oxide (GOX) and buried oxide (BOX) is large, so the depletion region can't cover the whole n region. So to some extent PDSOI behaves like [[bulk MOSFET]]. Obviously there are some advantages over the bulk MOSFETs. The film is very thin in FDSOI devices so that the depletion region covers the whole channel region. In FDSOI the front gate (GOX) supports fewer depletion charges than the bulk so an increase in inversion charges occurs resulting in higher switching speeds. The limitation of the depletion charge by the BOX induces a suppression of the depletion capacitance and therefore a substantial reduction of the subthreshold swing allowing FD SOI MOSFETs to work at lower gate bias resulting in lower power operation. The [[Subthreshold slope|subthreshold swing]] can reach the minimum theoretical value for MOSFET at 300K, which is 60mV/decade. This ideal value was first demonstrated using numerical simulation.<ref>{{cite thesis |first=F. |last=Balestra |title=Characterization and Simulation of SOI MOSFETs with Back Potential Control |date=1985 |type=PhD |publisher=INP-Grenoble |url=}}</ref><ref>{{cite book |first=F. |last=Balestra |chapter=1.5 Challenges to Ultralow-Power Semiconductor Device Operation |title=Future Trends in Microelectronics—Journey into the unknown |editor-first=S. |editor-last=Lury |editor2-first=J. |editor2-last=Xu |editor3-first=A. |editor3-last=Zaslavsky  |publisher=Wiley |date=2016 |doi=10.1002/9781119069225.ch1-5  |isbn=978-1-119-06922-5 |chapter-url={{GBurl|FPnoDAAAQBAJ|p=69}} |pages=69–81}}</ref> Other drawbacks in bulk MOSFETs, like threshold voltage roll off, etc. are reduced in FDSOI since the source and drain electric fields can't interfere due to the BOX. The main problem in PDSOI is the "[[floating body effect]] (FBE)" since the film is not connected to any of the supplies.{{Citation needed|date=June 2018}}

==Manufacture of SOI wafers==
[[File:SIMOX processing schematic.svg|thumb|300px|SIMOX process]]
[[File:Smart Cut SOI Wafer Manufacturing Schema.svg|thumb|300px|Smart cut process]]
{{chem|SiO|2}}-based SOI wafers can be produced by several methods:
*''[[SIMOX]]'' - separation by implantation of oxygen &ndash; uses an oxygen [[ion implantation|ion beam implantation]] process followed by high temperature annealing to create a buried {{chem|SiO|2}} layer.<ref>{{cite patent |inventor=Atsushi Ogura |title=Method of fabricating SOI substrate |country=US  |number=5888297 |url= |gdate=1999-03-30}}</ref><ref>{{cite patent |inventor=Hiroshi Fujioka |title=Method of manufacturing semiconductor on insulator |country=US |number=5061642 |url= |gdate=1991-10-29}}</ref>
*[[Wafer bonding]]<ref>{{cite book |first1=Q.-Y. |last1=Tong |first2=U. |last2=Gösele |title=SemiConductor Wafer Bonding: Science and Technology |publisher=Wiley |date=1998 |isbn=978-0-471-57481-1 |pages= |url=}}</ref><ref>{{cite patent |inventor-first=George |inventor-last=Bajor |invent2=et al. |title=Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor |country=US |number=4771016 |url= |gdate=1988-09-13}}</ref> &ndash; the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer.
**One prominent example of a wafer bonding process is the ''[[smart cut]]'' method developed by the French firm [[Soitec]] which uses ion implantation followed by controlled exfoliation to determine the thickness of the uppermost silicon layer.
**''NanoCleave'' is a technology developed by Silicon Genesis Corporation that separates the silicon via stress at the interface of silicon and [[silicon-germanium]] alloy.<ref>{{cite web|url=http://www.sigen.com/|title=SIGEN.COM|website=www.sigen.com|access-date=22 April 2018}}</ref>
**''ELTRAN'' is a technology developed by Canon which is based on porous silicon and water cut.<ref>{{cite web |last1=Yonehara |first1=T |last2=Sakaguchi |first2=K.|url=http://www.jsapi.jsap.or.jp/Pdf/Number04/CuttingEdge2.pdf |title=ELTRAN® Novel SOI Wafer Technology |work=Cutting Edge 2 |publisher=Canon}}</ref>
*Seed methods<ref>{{cite patent |country=US |number=5417180}}</ref> - wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.

An exhaustive review of these various manufacturing processes may be found in reference<ref name="celler"/>

== Use in the microelectronics industry ==
[[IBM]] began to use SOI in the high-end [[RS64#RS64-IV|RS64-IV]] "Istar" PowerPC-AS microprocessor in 2000. Other examples of microprocessors built on SOI technology include [[AMD]]'s 130&nbsp;nm, 90&nbsp;nm, 65&nbsp;nm, 45&nbsp;nm and 32&nbsp;nm single, dual, quad, six and eight core processors since 2001.<ref>{{cite web |last=Vries |first=Hans de |date= |title=Chip Architect: Intel and Motorola/AMD's 130 nm processes to be revealed. |url=http://chip-architect.com/news/2000_11_07_process_130_nm.html |access-date=22 April 2018 |website=chip-architect.com}}</ref> [[Freescale]] adopted SOI in their [[PowerPC]] 7455 CPU in late 2001, currently{{when|date=April 2018}} Freescale is shipping SOI products in 180&nbsp;nm, 130&nbsp;nm, 90&nbsp;nm and 45&nbsp;nm lines.<ref>{{cite web |author= |date= |title=NXP Semiconductors - Automotive, Security, IoT |url=http://www.freescale.com/webapp/sps/site/overview.jsp?nodeId=0121000303#soi |access-date=22 April 2018 |website=www.freescale.com}}</ref> The 90&nbsp;nm [[PowerPC]]- and [[Power ISA]]-based processors used in the [[Xbox 360]], [[PlayStation 3]], and [[Wii]] use SOI technology as well. Competitive offerings from [[Intel]] however continue{{when|date=April 2018}} to use conventional [[bulk CMOS]] technology for each process node, instead focusing on other venues such as [[HKMG]] and [[tri-gate transistor]]s to improve transistor performance. In January 2005, Intel researchers reported on an experimental single-chip silicon rib waveguide Raman laser built using SOI.<ref name="Intel 20052">{{cite journal |last1=Rong |first1=Haisheng |last2=Liu |first2=Ansheng |last3=Jones |first3=Richard |last4=Cohen |first4=Oded |last5=Hak |first5=Dani |last6=Nicolaescu |first6=Remus |last7=Fang |first7=Alexander |last8=Paniccia |first8=Mario |date=January 2005 |title=An all-silicon Raman laser |url=http://www.ece.ucsb.edu/uoeg/publications/papers/Rong05nature.pdf |journal=Nature |volume=433 |issue=7042 |pages=292–4 |doi=10.1038/nature03723|pmid=15931210 |s2cid=4423069 }}</ref>

As for the traditional foundries, in July 2006 [[TSMC]] claimed no customer wanted SOI,<ref>{{cite web |author= |date= |title=TSMC has no customer demand for SOI technology |publisher=Fabtech: The online information source for semiconductor professionals |url=http://www.fabtech.org/content/view/1698/74/ |archive-url=https://web.archive.org/web/20070928162940/http://www.fabtech.org/content/view/1698/74/ |archive-date=28 September 2007 |access-date=22 April 2018 }}</ref> but [[Chartered Semiconductor]] devoted a whole fab to SOI.<ref>[http://www.charteredsemi.com/media/corp/2006n/20060420_IBM_SOI.asp Chartered expands foundry market access to IBM's 90nm SOI technology]</ref>

==Use in high-performance radio frequency (RF) applications==
In 1990, [[Peregrine Semiconductor]] began development of an SOI process technology utilizing a standard 0.5&nbsp;μm CMOS node and an enhanced sapphire substrate. Its patented [[silicon on sapphire]] (SOS) process is widely used in high-performance RF applications. The intrinsic benefits of the insulating sapphire substrate allow for high isolation, high linearity and electro-static discharge (ESD) tolerance. Multiple other companies have also applied SOI technology to successful RF applications in smartphones and cellular radios.<ref>{{cite news |title=Handset RFFEs: ''MMPAs, Envelope Tracking, Antenna Tuning, FEMs, and MIMO'' |first=Joe |last=Madden |url=http://mobile-experts.net/manuals/mexp-rffe-12%20toc.pdf |archive-url=https://web.archive.org/web/20160304044306/http://mobile-experts.net/manuals/mexp-rffe-12%20toc.pdf |archive-date=4 March 2016 |publisher= Mobile Experts |access-date=2 May 2012 }}</ref>{{additional citation needed|date=June 2018}}

==Use in photonics==
SOI wafers are widely used in [[silicon photonics]].<ref>{{cite book|url=https://books.google.com/books?id=6lsVVvFCBeAC&q=SOI+Wafers+in+Photonics&pg=PA111|title=Silicon Photonics: An Introduction|first1=Graham T.|last1=Reed|first2=Andrew P.|last2=Knights|date=5 March 2004|publisher=Wiley|access-date=22 April 2018|via=Google Books|isbn=978-0-470-87034-1}}</ref> The crystalline silicon layer on insulator can be used to fabricate optical waveguides and other optical devices, either passive or active (e.g. through suitable implantations). The buried insulator enables propagation of infrared light in the silicon layer on the basis of total internal reflection. The top surface of the waveguides can be either left uncovered and exposed to air (e.g. for sensing applications), or covered with a cladding, typically made of silica<ref>{{cite web |last1=Rigny |first1=Arnaud |title=Silicon-on-Insulator Substrates: The Basis of Silicon Photonics |url=https://www.photonics.com/Articles/Silicon-on-Insulator_Substrates_The_Basis_of/a63021 |website=Photonics.com |access-date=7 May 2023}}</ref>

== Disadvantages ==
The major disadvantage of SOI technology when compared to conventional semiconductor industry is increased cost of manufacturing.<ref name=":0">{{Cite web|last=McLellan|first=Paul|title=Silicon on Insulator (SOI)|url=https://semiwiki.com/semiconductor-services/1470-silicon-on-insulator-soi/|access-date=2021-03-07|website=Semiwiki|language=en-US}}</ref> As of 2012 only IBM and AMD used SOI as basis for high-performance processors and the other manufacturers (Intel, TSMC, Global Foundries etc.) used conventional silicon wafers to build their [[CMOS]] chips.<ref name=":0" />

== SOI market ==
As of 2020 the market utilizing the SOI process was projected to grow up by ~15% for the next 5 years according to Market Research Future group.<ref>{{Cite press release|last=Future|first=Market Research|date=2021-02-17|title=Silicon on Insulator (SoI) Market is Anticipated to Surpass USD 2.40 Billion By 2026 {{!}} APAC Region to Remain Forerunner in Global Silicon on Insulator Industry|url=http://www.globenewswire.com/news-release/2021/02/17/2176707/0/en/Silicon-on-Insulator-SoI-Market-is-Anticipated-to-Surpass-USD-2-40-Billion-By-2026-APAC-Region-to-Remain-Forerunner-in-Global-Silicon-on-Insulator-Industry.html|access-date=2021-03-07|website=GlobeNewswire News Room}}</ref>

==See also==
* [[Intel TeraHertz]] - similar technology from Intel
* [[Strain engineering]]
* [[Wafer (electronics)]]
* [[Wafer bonding]]

==References==
{{Reflist|30em}}

==External links==
*[http://soiconsortium.org/ SOI Industry Consortium] - a site with extensive information and education for SOI technology
*[https://web.archive.org/web/20100525073147/http://www.chipestimate.com/soi/ SOI IP portal] - A search engine for SOI IP
*[http://www.amdboard.com/soispecial.html AMDboard] - a site with extensive information regarding SOI technology
*[http://www.advancedsubstratenews.com/ Advanced Substrate News] - a newsletter about the SOI industry, produced by Soitec
*[http://www.migas.inpg.fr/2004/ MIGAS '04] - The 7th session of MIGAS International Summer School on Advanced Microelectronics, devoted to SOI technology and devices
*[http://www.migas.inpg.fr/2009/ MIGAS '09] - 12th session of the International Summer School on Advanced Microelectronics: "Silicon on Insulator (SOI) Nanodevices"

[[Category:Semiconductor structures]]
[[Category:Semiconductor technology]]
[[Category:Microtechnology]]
[[Category:MOSFETs]]
[[Category:Nanoelectronics]]
[[Category:Semiconductor device fabrication]]
[[Category:Silicon]]