View source for Serial presence detect

{{Short description|Standardized way to automatically access information about a memory module}}
{{Use dmy dates|date=March 2020}}
In [[computing]], '''serial presence detect''' ('''SPD''') is a standardized way to automatically access information about a [[memory module]].  Earlier 72-pin [[SIMM]]s included five pins that provided five bits of ''parallel presence detect'' (PPD) data, but the 168-pin [[DIMM]] standard changed to a serial presence detect to encode more information.<ref>{{Citation |url=http://findarticles.com/p/articles/mi_m0EKF/is_n2153_v43/ai_19102210/ |title=Serial Presence Detection poised for limelight |author1=Thomas P. Koenig |author2=Nathan John |journal=Electronic News |date=1997-02-03 |volume=43 |issue=2153}}</ref>

When an ordinary modern computer is turned on, it starts by doing a [[power-on self-test]] (POST).  Since about the mid-1990s, this process includes automatically configuring the hardware currently present.  SPD is a memory hardware feature that makes it possible for the computer to know what memory is present, and what [[memory timings]] to use to access the memory.

Some computers adapt to hardware changes completely automatically.  In most cases, there is a special optional procedure for accessing [[BIOS]] parameters, to view and potentially make changes in settings.  It may be possible to control how the computer uses the memory SPD data—to choose settings, selectively modify memory timings, or possibly to completely override the SPD data (see [[overclocking]]).

==Stored information==
For a memory module to support SPD, the [[JEDEC]] standards require that certain parameters be in the lower 128 bytes of an [[EEPROM]] located on the memory module.  These bytes contain timing parameters, manufacturer, serial number and other useful information about the module.  Devices utilizing the memory automatically determine key parameters of the module by reading this information.  For example, the SPD data on an [[SDRAM]] module might provide information about the [[CAS latency]] so the system can set this correctly without user intervention.

The SPD EEPROM firmware is accessed using [[SMBus]], a variant of the [[I2C|I<sup>2</sup>C]] protocol.  This reduces the number of communication pins on the module to just two: a clock signal and a data signal.  The EEPROM shares ground pins with the RAM, has its own power pin, and has three additional pins (SA0–2) to identify the slot, which are used to assign the EEPROM a unique address in the range 0x50–0x57.  Not only can the communication lines be shared among 8 memory modules, the same SMBus is commonly used on motherboards for system health monitoring tasks such as reading power supply voltages, [[Central processing unit|CPU]] temperatures, and fan speeds.

SPD EEPROMs also respond to I<sup>2</sup>C addresses 0x30–0x37 if they have not been write protected, and an extension (TSE series) uses addresses 0x18–0x1F to access an optional on-chip temperature sensor. All those values are [[I2C#7-bit addressing|seven-bit I<sup>2</sup>C addresses]] formed by a Device Type Identifier Code prefix (DTIC) with SA0-2: to read (1100) from slot 3, one uses <code>'''110 0'''011 =&nbsp;0x33</code>. With a final R/W bit it forms the 8-bit Device Select Code.<ref>[http://www.jedec.org/sites/default/files/docs/4_01_04R21.pdf JEDEC Standard 21-C section 4.1.4] "Definition of the TSE2002av Serial Presence Detect (SPD) EEPROM with Temperature Sensor (TS) for Memory Module Applications"</ref> Note that the semantics of slot-id is different for write-protection operations: for them they can be not passed by the SA pins at all.<ref>{{cite web |title=TN-04-42: Memory Module Serial Presence-Detect Write Protection |url=https://www.micron.com/-/media/client/global/documents/products/technical-note/dram-modules/tn_04_42.pdf |website=Micron}}</ref>

Before SPD, memory chips were spotted with parallel presence detect (PPD). PPD used a separate pin for each bit of information, which meant that only the speed and density of the memory module could be stored because of the limited space for pins.

===SDR SDRAM===
[[File:SPD SDRAM.jpg|thumb|Memory device on an [[SDRAM]] module, containing ''SPD'' data (red circled)]]
The first SPD specification was issued by JEDEC and tightened up by Intel as part of its [[PC100]] memory specification introduced in 1998.<ref>{{Cite web|url=https://www.tomshardware.com/reviews/ram-guide,89.html|title=Ram Guide|author1=Dean Kent|date=24 October 1998|website=Tom's Hardware}}</ref><ref>{{Cite web|url=https://www.anandtech.com/show/60|title=PC100 SDRAM: An Introduction|first=Anand Lal|last=Shimpi|website=www.anandtech.com}}</ref><ref>[http://www.memorytesters.com/ramcheck/rc_ap3.htm Application note INN-8668-APN3: SDRAM SPD Data Standards], memorytesters.com</ref> Most values specified are in [[binary-coded decimal]] form.  The most significant [[nibble]] can contain values from 10 to 15, and in some cases extends higher.  In such cases, the encodings for 1, 2 and 3 are instead used to encode 16, 17 and 18.  A most significant nibble of 0 is reserved to represent "undefined".

The SPD ROM defines up to three DRAM timings, for three CAS latencies specified by set bits in byte 18.  First comes the highest CAS latency (fastest clock), then two lower CAS latencies with progressively lower clock speeds.
{|class=wikitable
|+ SPD contents for SDR SDRAM<ref name=spd_pc100>{{Citation |url=http://www.taricorp.net/wp-content/uploads/2012/04/SPDSDRAM1.2a1.pdf |title=PC SDRAM Serial Presence Detect (SPD) Specification |date=December 1997 |version=1.2A |page=28 |access-date=30 May 2014 |archive-date=31 May 2014 |archive-url=https://web.archive.org/web/20140531124526/http://www.taricorp.net/wp-content/uploads/2012/04/SPDSDRAM1.2a1.pdf |url-status=dead }}</ref>
! colspan=2 | Byte
! colspan=8 | Bit
! rowspan=2 | Notes
|-
! (dec.) !! (hex.)
! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
|  0 || 0x00 ||colspan=8| Number of bytes present || Typically 128
|-
|  1 || 0x01 ||colspan=8| log<sub>2</sub>(size of SPD EEPROM) || Typically 8 (256 bytes)
|-
|  2 || 0x02 ||colspan=8| Basic memory type (4: SPD SDRAM) ||
|-
|  3 || 0x03 ||colspan=4| Bank 2 row address bits (0–15) ||colspan=4| Bank 1 row address bits (1–15) || Bank 2 is 0 if same as bank 1
|-
|  4 || 0x04 ||colspan=4| Bank 2 column address bits (0–15) ||colspan=4| Bank 1 column address bits (1–15)  || Bank 2 is 0 if same as bank 1
|-
|  5 || 0x05 ||colspan=8| Number of RAM banks on module (1–255) || Commonly 1 or 2
|-
|  6 || 0x06 ||colspan=8| Module data width low byte || Commonly 64, or 72 for ECC DIMMs
|-
|  7 || 0x07 ||colspan=8| Module data width high byte || 0, unless width ≥ 256 bits
|-
|  8 || 0x08 ||colspan=8| Interface voltage level of this assembly (not the same as V<sub>cc</sub> supply voltage) (0–4) || Decoded by table lookup
|-
|  9 || 0x09 ||colspan=4| Nanoseconds (0–15) ||colspan=4| Tenths of nanoseconds (0.0–0.9) || Clock cycle time at highest CAS latency
|-
| 10 || 0x0a ||colspan=4| Nanoseconds (0–15) ||colspan=4| Tenths of nanoseconds (0.0–0.9) || SDRAM access time from clock (t<sub>AC</sub>)
|-
| 11 || 0x0b ||colspan=8| DIMM configuration type (0–2): non-ECC, parity, ECC || Table lookup
|-
| 12 || 0x0c || Self ||colspan=7| Refresh period (0–5): 64, 256, 128, 32, 16, 8&nbsp;kHz|| Refresh requirements
|-
| 13 || 0x0d || Bank 2 2× ||colspan=7 | Bank 1 primary SDRAM width (1–127, usually 8) || Width of bank 1 data SDRAM devices.  Bank 2 may be same width, or 2× width if bit 7 is set.
|-
| 14 || 0x0e || Bank 2 2× ||colspan=7 | Bank 1 ECC SDRAM width (0–127)|| Width of bank 1 ECC/parity SDRAM devices.  Bank 2 may be same width, or 2× width if bit 7 is set.
|-
| 15 || 0x0f ||colspan=8| Clock delay for random column reads || Typically 1
|-
| 16 || 0x10|| Page || — || — || — || 8 || 4 || 2 || 1 || Burst lengths supported (bitmap)
|-
| 17 || 0x11 ||colspan=8| Banks per SDRAM device (1–255) || Typically 2 or 4
|-
| 18 || 0x12 || — || 7 || 6 || 5 || 4 || 3 || 2 || 1 || {{overline|CAS}} latencies supported (bitmap)
|-
| 19 || 0x13 || — || 6 || 5 || 4 || 3 || 2 || 1 || 0 || {{overline|CS}} latencies supported (bitmap)
|-
| 20 || 0x14 || — || 6 || 5 || 4 || 3 || 2 || 1 || 0 || {{overline|WE}} latencies supported (bitmap)
|-
| 21 || 0x15 || — || Redundant || Diff. clock || Registered data || Buffered data || On-card PLL || Registered addr. || Buffered addr. || Memory module feature bitmap
|-
| 22 || 0x16 || — || — || Upper V<sub>cc</sub> (supply voltage) tolerance || Lower V<sub>cc</sub> (supply voltage) tolerance || Write/1&nbsp;read burst|| Precharge all || Auto-precharge || Early {{overline|RAS}} precharge || Memory chip feature support bitmap
|-
| 23 || 0x17 ||colspan=4| Nanoseconds (4–18) ||colspan=4| Tenths of nanoseconds (0–9: 0.0–0.9) || Clock cycle time at medium CAS latency
|-
| 24 || 0x18 ||colspan=4| Nanoseconds (4–18) ||colspan=4| Tenths of nanoseconds (0–9: 0.0–0.9) || Data access time from clock (t<sub>AC</sub>)
|-
| 25 || 0x19 ||colspan=6| Nanoseconds (1–63) ||colspan=2| 0.25&nbsp;ns (0–3: 0.00–0.75) || Clock cycle time at short CAS latency.
|-
| 26 || 0x1a ||colspan=6| Nanoseconds (1–63) ||colspan=2| 0.25&nbsp;ns (0–3: 0.00–0.75) || Data access time from clock (t<sub>AC</sub>)
|-
| 27 || 0x1b ||colspan=8| Nanoseconds (1–255) || Minimum row precharge time (t<sub>RP</sub>)
|-
| 28 || 0x1c ||colspan=8| Nanoseconds (1–255) || Minimum row active–row active delay (t<sub>RRD</sub>)
|-
| 29 || 0x1d ||colspan=8| Nanoseconds (1–255) || Minimum {{overline|RAS}} to {{overline|CAS}} delay (t<sub>RCD</sub>)
|-
| 30 || 0x1e ||colspan=8| Nanoseconds (1–255) || Minimum active to precharge time (t<sub>RAS</sub>)
|-
| 31 || 0x1f || 512&nbsp;MiB || 256&nbsp;MiB || 128&nbsp;MiB || 64&nbsp;MiB || 32&nbsp;MiB || 16&nbsp;MiB || 8&nbsp;MiB || 4&nbsp;MiB || Module bank density (bitmap).  Two bits set if different size banks.
|-
| 32 || 0x20 || Sign (1: −) || colspan=3| Nanoseconds (0–7) ||colspan=4| Tenths of nanoseconds (0–9: 0.0–0.9) || Address/command setup time from clock
|-
| 33 || 0x21 || Sign (1: −) || colspan=3| Nanoseconds (0–7) ||colspan=4| Tenths of nanoseconds (0–9: 0.0–0.9) || Address/command hold time after clock
|-
| 34 || 0x22 || Sign (1: −) || colspan=3| Nanoseconds (0–7) ||colspan=4| Tenths of nanoseconds (0–9: 0.0–0.9) || Data input setup time from clock
|-
| 35 || 0x23 || Sign (1: −) || colspan=3| Nanoseconds (0–7) ||colspan=4| Tenths of nanoseconds (0–9: 0.0–0.9) || Data input hold time after clock
|-
| 36–61 || 0x24–0x3d
|colspan=8 {{n/a|Reserved}}
| For future standardization
|-
| 62 || 0x3e ||colspan=4| Major revision (0–9) ||colspan=4| Minor revision (0–9) || SPD revision level; e.g., 1.2
|-
| 63 || 0x3f ||colspan=8| Checksum || Sum of bytes 0–62, ''not then negated''
|-
| 64–71 || 0x40–47 ||colspan=8| Manufacturer JEDEC id. || Stored little-endian, trailing zero-padded
|-
| 72 || 0x48 ||colspan=8| Module manufacturing location || Vendor-specific code
|-
| 73–90 || 0x49–0x5a ||colspan=8| Module part number || ASCII, space-padded
|-
| 91–92 || 0x5b–0x5c ||colspan=8| Module revision code || Vendor-specific code
|-
| 93 || 0x5d ||colspan=4| Tens of years (0–9: 0–90) ||colspan=4| Years (0–9) ||rowspan=2| Manufacturing date (YYWW)
|-
| 94 || 0x5e ||colspan=4| Tens of weeks (0–5: 0–50) ||colspan=4| Weeks (0–9)
|-
| 95–98 || 0x5f–0x62 ||colspan=8| Module serial number || Vendor-specific code
|-
| 99–125 || 0x63–0x7f ||colspan=8| Manufacturer-specific data || Could be enhanced performance profile
|-
| 126 || 0x7e ||colspan=8| 0x66{{sic}} for 66&nbsp;MHz, 0x64 for 100&nbsp;MHz || Intel frequency support
|-
| 127 || 0x7f || CLK0 || CLK1 || CLK3 || CLK3 || 90/100&nbsp;°C || CL3 || CL2 || Concurrent AP || Intel feature bitmap
|}

===DDR SDRAM===
The DDR DIMM SPD format is an extension of the SDR SDRAM format.  Mostly, parameter ranges are rescaled to accommodate higher speeds.
<!-- This table is a bit too big.  If you don't like it, please move it to the talk page. -->
{|class=wikitable
|+ SPD contents for DDR SDRAM<ref name=spd_ddr/>
! colspan=2 | Byte
! colspan=8 | Bit
! rowspan=2 | Notes
|-
! (dec.) !! (hex.)
! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
|  0 || 0x00 ||colspan=8| Number of bytes written || Typically 128
|-
|  1 || 0x01 ||colspan=8| log<sub>2</sub>(size of SPD EEPROM) || Typically 8 (256 bytes)
|-
|  2 || 0x02 ||colspan=8| Basic memory type (7 = DDR SDRAM) ||
|-
|  3 || 0x03 ||colspan=4| Bank 2 row address bits (0–15)  ||colspan=4| Bank 1 row address bits (1–15) || Bank 2 is 0 if same as bank 1.
|-
|  4 || 0x04 ||colspan=4| Bank 2 column address bits (0–15) ||colspan=4| Bank 1 column address bits (1–15)  || Bank 2 is 0 if same as bank 1.
|-
|  5 || 0x05 ||colspan=8| Number of RAM banks on module (1–255) ||Commonly 1 or 2
|-
|  6 || 0x06 ||colspan=8| Module data width low byte || Commonly 64, or 72 for ECC DIMMs
|-
|  7 || 0x07 ||colspan=8| Module data width high byte || 0, unless width ≥ 256 bits
|-
|  8 || 0x08 ||colspan=8| Interface voltage level of this assembly (not the same as V<sub>cc</sub> supply voltage) (0–5) || Decoded by table lookup
|-
|  9 || 0x09 ||colspan=4| Nanoseconds (0–15) ||colspan=4| Tenths of nanoseconds (0.0–0.9) || Clock cycle time at highest CAS latency.
|-
| 10 || 0x0a ||colspan=4| Tenths of nanoseconds (0.0–0.9) ||colspan=4| Hundredths of nanoseconds (0.00–0.09) || SDRAM access time from clock (t<sub>AC</sub>)
|-
| 11 || 0x0b ||colspan=8| DIMM configuration type (0–2): non-ECC, parity, ECC || Table lookup
|-
| 12 || 0x0c || Self ||colspan=7| Refresh period (0–5): 64, 256, 128, 32, 16, 8&nbsp;kHz|| Refresh requirements
|-
| 13 || 0x0d || Bank 2 2× ||colspan=7 | Bank 1 primary SDRAM width (1–127) || Width of bank 1 data SDRAM devices.  Bank 2 may be same width, or 2× width if bit 7 is set.
|-
| 14 || 0x0e || Bank 2 2× ||colspan=7 | Bank 1 ECC SDRAM width (0–127)|| Width of bank 1 ECC/parity SDRAM devices.  Bank 2 may be same width, or 2× width if bit 7 is set.
|-
| 15 || 0x0f ||colspan=8| Clock delay for random column reads || Typically 1
|-
| 16 || 0x10|| Page || — || — || — || 8 || 4 || 2 || 1 || Burst lengths supported (bitmap)
|-
| 17 || 0x11 ||colspan=8| Banks per SDRAM device (1–255) || Typically 4
|-
| 18 || 0x12 || — || 4 || 3.5 || 3 || 2.5 || 2 || 1.5 || 1 || {{overline|CAS}} latencies supported (bitmap)
|-
| 19 || 0x13 || — || 6 || 5 || 4 || 3 || 2 || 1 || 0 || {{overline|CS}} latencies supported (bitmap)
|-
| 20 || 0x14 || — || 6 || 5 || 4 || 3 || 2 || 1 || 0 || {{overline|WE}} latencies supported (bitmap)
|-
| 21 || 0x15 || — || x || Diff clock || FET switch external enable || FET switch on-board enable || On-card PLL || Registered || Buffered || Memory module feature bitmap
|-
| 22 || 0x16 || Fast AP || Concurrent auto precharge || Upper V<sub>cc</sub> (supply voltage) tolerance || Lower V<sub>cc</sub> (supply voltage) tolerance || — || — || — || Includes weak driver || Memory chip feature bitmap
|-
| 23 || 0x17 ||colspan=4| Nanoseconds (0–15) ||colspan=4| Tenths of nanoseconds (0.0–0.9) || Clock cycle time at medium CAS latency.
|-
| 24 || 0x18 ||colspan=4| Tenths of nanoseconds (0.0–0.9) ||colspan=4| Hundredths of nanoseconds (0.00–0.09) || Data access time from clock (t<sub>AC</sub>)
|-
| 25 || 0x19 ||colspan=4| Nanoseconds (0–15) ||colspan=4| Tenths of nanoseconds (0.0–0.9) || Clock cycle time at short CAS latency.
|-
| 26 || 0x1a ||colspan=4| Tenths of nanoseconds (0.0–0.9) ||colspan=4| Hundredths of nanoseconds (0.00–0.09) || Data access time from clock (t<sub>AC</sub>)
|-
| 27 || 0x1b ||colspan=6| Nanoseconds (1–63) ||colspan=2| 0.25&nbsp;ns (0–0.75) || Minimum row precharge time (t<sub>RP</sub>)
|-
| 28 || 0x1c ||colspan=6| Nanoseconds (1–63) ||colspan=2| 0.25&nbsp;ns (0–0.75) || Minimum row active–row active delay (t<sub>RRD</sub>)
|-
| 29 || 0x1d ||colspan=6| Nanoseconds (1–63) ||colspan=2| 0.25&nbsp;ns (0–0.75) || Minimum {{overline|RAS}} to {{overline|CAS}} delay (t<sub>RCD</sub>)
|-
| 30 || 0x1e ||colspan=8| Nanoseconds (1–255) || Minimum active to precharge time (t<sub>RAS</sub>)
|-
| 31 || 0x1f || 512&nbsp;MiB || 256&nbsp;MiB || 128&nbsp;MiB || 64&nbsp;MiB || 32&nbsp;MiB || 16&nbsp;MiB/<br />4&nbsp;GiB || 8&nbsp;MiB/<br />2&nbsp;GiB || 4&nbsp;MiB/<br />1&nbsp;GiB || Module bank density (bitmap).  Two bits set if different size banks.
|-
| 32 || 0x20 ||colspan=4| Tenths of nanoseconds (0.0–0.9) ||colspan=4| Hundredths of nanoseconds (0.00–0.09) || Address/command setup time from clock
|-
| 33 || 0x21 ||colspan=4| Tenths of nanoseconds (0.0–0.9) ||colspan=4| Hundredths of nanoseconds (0.00–0.09) || Address/command hold time after clock
|-
| 34 || 0x22 ||colspan=4| Tenths of nanoseconds (0.0–0.9) ||colspan=4| Hundredths of nanoseconds (0.00–0.09) || Data input setup time from clock
|-
| 35 || 0x23 ||colspan=4| Tenths of nanoseconds (0.0–0.9) ||colspan=4| Hundredths of nanoseconds (0.00–0.09) || Data input hold time after clock
|-
| 36–40
| 0x24–0x28 ||colspan=8 {{n/a|Reserved}}
| Superset information
|-
| 41 || 0x29 ||colspan=8| Nanoseconds (1–255) || Minimum active to active/refresh time (t<sub>RC</sub>)
|-
| 42 || 0x2a ||colspan=8| Nanoseconds (1–255) || Minimum refresh to active/refresh time (t<sub>RFC</sub>)
|-
| 43 || 0x2b ||colspan=6| Nanoseconds (1–63, or 255: no maximum) ||colspan=2| 0.25&nbsp;ns (0–0.75) || Maximum clock cycle time (t<sub>CK</sub> max.)
|-
| 44 || 0x2c ||colspan=8| Hundredths of nanoseconds (0.01–2.55) || Maximum skew, DQS to any DQ. (t<sub>DQSQ</sub> max.)
|-
| 45 || 0x2d ||colspan=4| Tenths of nanoseconds (0.0–1.2) ||colspan=4| Hundredths of nanoseconds (0.00–0.09) || Read data hold skew factor (t<sub>QHS</sub>)
|-
| 46 || 0x2e
|colspan=8 {{n/a|Reserved}}
| For future standardization
|-
| 47 || 0x2f ||colspan=6| — ||colspan=2| Height || Height of DIMM module, table lookup
|-
| 48–61 || 0x30–0x3d
|colspan=8 {{n/a|Reserved}}
| For future standardization
|-
| 62 || 0x3e ||colspan=4| Major revision (0–9) ||colspan=4| Minor revision (0–9) || SPD revision level, 0.0 or 1.0
|-
| 63 || 0x3f ||colspan=8| Checksum || Sum of bytes 0–62, ''not then negated''
|-
| 64–71 || 0x40–47 ||colspan=8| Manufacturer JEDEC id. || Stored little-endian, trailing zero-padded
|-
| 72 || 0x48 ||colspan=8| Module manufacturing location || Vendor-specific code
|-
| 73–90 || 0x49–0x5a ||colspan=8| Module part number || ASCII, space-padded
|-
| 91–92 || 0x5b–0x5c ||colspan=8| Module revision code || Vendor-specific code
|-
| 93 || 0x5d ||colspan=4| Tens of years (0–90) ||colspan=4| Years (0–9) ||rowspan=2| Manufacturing date (YYWW)
|-
| 94 || 0x5e ||colspan=4| Tens of weeks (0–50) ||colspan=4| Weeks (0–9)
|-
| 95–98 || 0x5f–0x62 ||colspan=8| Module serial number || Vendor-specific code
|-
| 99–127 || 0x63–0x7f ||colspan=8| Manufacturer-specific data || Could be enhanced performance profile
|}

===DDR2 SDRAM===
The DDR2 SPD standard makes a number of changes, but is roughly similar to the above.  One notable deletion is the confusing and little-used support for DIMMs with two ranks of different sizes.

For cycle time fields (bytes 9, 23, 25 and 49), which are encoded in [[Binary-coded decimal|BCD]], some additional encodings are defined for the tenths digit to represent some common timings exactly:
{|class=wikitable
|+ DDR2 BCD extensions
! Hex !! Binary !! Significance
|-
| A || 1010 || 0.25 ({{frac|1|4}})
|-
| B || 1011 || 0.33 ({{frac|1|3}})
|-
| C || 1100 || 0.66 ({{frac|2|3}})
|-
| D || 1101 || 0.75 ({{frac|3|4}})
|-
| E || 1110 || 0.875 ({{frac|7|8}}, Nvidia XMP extension)
|-
| F || 1111 || {{n/a|Reserved}}
|}

{|class=wikitable
|+ SPD contents for DDR2 SDRAM<ref name="spd_ddr2" />
|-
! colspan=2 | Byte
! colspan=8 | Bit
! rowspan=2 | Notes
|-
! Dec !! Hex !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
|  0 || 0x00 ||colspan=8| Number of bytes written || Typically 128
|-
|  1 || 0x01 ||colspan=8| log<sub>2</sub>(size of SPD EEPROM) || Typically 8 (256 bytes)
|-
|  2 || 0x02 ||colspan=8| Basic memory type (8 = DDR2 SDRAM) ||
|-
|  3 || 0x03 ||colspan=4 {{n/a|Reserved}} ||colspan=4| Row address bits (1–15) ||
|-
|  4 || 0x04 ||colspan=4 {{n/a|Reserved}} ||colspan=4| Column address bits (1–15)  ||
|-
|  5 || 0x05 ||colspan=3| Vertical height || Stack? || ConC? ||colspan=3| Ranks−1 (1–8) || Commonly 0 or 1, meaning 1 or 2
|-
|  6 || 0x06 ||colspan=8| Module data width || Commonly 64, or 72 for ECC DIMMs
|-
|  7 || 0x07 ||colspan=8 {{n/a|Reserved}} ||
|-
|  8 || 0x08 ||colspan=8| Interface voltage level of this assembly (not the same as V<sub>cc</sub> supply voltage) (0–5) || Decoded by table lookup.<br />Commonly 5 = SSTL 1.8&nbsp;V
|-
|  9 || 0x09 ||colspan=4| Nanoseconds (0–15) ||colspan=4| Tenths of nanoseconds (0.0–0.9) || Clock cycle time at highest CAS latency.
|-
| 10 || 0x0a ||colspan=4| Tenths of nanoseconds (0.0–0.9) ||colspan=4| Hundredths of nanoseconds (0.00–0.09) || SDRAM access time from clock (t<sub>AC</sub>)
|-
| 11 || 0x0b ||colspan=8| DIMM configuration type (0–2): non-ECC, parity, ECC || Table lookup
|-
| 12 || 0x0c || Self ||colspan=7| Refresh period (0–5): 64, 256, 128, 32, 16, 8&nbsp;kHz|| Refresh requirements
|-
| 13 || 0x0d ||colspan=8 | Primary SDRAM width (1–255) || Commonly 8 (module built from ×8 parts) or 16
|-
| 14 || 0x0e ||colspan=8 | ECC SDRAM width (0–255)|| Width of bank ECC/parity SDRAM devices.  Commonly 0 or 8.
|-
| 15 || 0x0f ||colspan=8 {{n/a|Reserved}} ||
|-
| 16 || 0x10||| — || — || — || — || 8 || 4 || — || — || Burst lengths supported (bitmap)
|-
| 17 || 0x11 ||colspan=8| Banks per SDRAM device (1–255) || Typically 4 or 8
|-
| 18 || 0x12 || 7 || 6 || 5 || 4 || 3 || 2 || — || — || {{overline|CAS}} latencies supported (bitmap)
|-
| 19 || 0x13 ||colspan=8 {{n/a|Reserved}} ||
|-
| 20 || 0x14 || — || — || Mini-UDIMM || Mini-RDIMM || Micro-DIMM || SO-DIMM || UDIMM || RDIMM || DIMM type of this assembly (bitmap)
|-
| 21 || 0x15 || — || Module is analysis probe || — || FET switch external enable || — || — || — || — || Memory module feature bitmap
|-
| 22 || 0x16 || — || — || — || — || — || — || — || Includes weak driver || Memory chip feature bitmap
|-
| 23 || 0x17 ||colspan=4| Nanoseconds (0–15) ||colspan=4| Tenths of nanoseconds (0.0–0.9) || Clock cycle time at medium CAS latency.
|-
| 24 || 0x18 ||colspan=4| Tenths of nanoseconds (0.0–0.9) ||colspan=4| Hundredths of nanoseconds (0.00–0.09) || Data access time from clock (t<sub>AC</sub>)
|-
| 25 || 0x19 ||colspan=4| Nanoseconds (0–15) ||colspan=4| Tenths of nanoseconds (0.0–0.9) || Clock cycle time at short CAS latency.
|-
| 26 || 0x1a ||colspan=4| Tenths of nanoseconds (0.0–0.9) ||colspan=4| Hundredths of nanoseconds (0.00–0.09) || Data access time from clock (t<sub>AC</sub>)
|-
| 27 || 0x1b ||colspan=6| Nanoseconds (1–63) ||colspan=2| 1/4 ns (0–0.75) || Minimum row precharge time (t<sub>RP</sub>)
|-
| 28 || 0x1c ||colspan=6| Nanoseconds (1–63) ||colspan=2| 1/4 ns (0–0.75) || Minimum row active–row active delay (t<sub>RRD</sub>)
|-
| 29 || 0x1d ||colspan=6| Nanoseconds (1–63) ||colspan=2| 1/4 ns (0–0.75) || Minimum {{overline|RAS}} to {{overline|CAS}} delay (t<sub>RCD</sub>)
|-
| 30 || 0x1e ||colspan=8| Nanoseconds (1–255) || Minimum active to precharge time (t<sub>RAS</sub>)
|-
| 31 || 0x1f || 512&nbsp;MiB || 256&nbsp;MiB || 128&nbsp;MiB || 16&nbsp;GiB || 8&nbsp;GiB || 4&nbsp;GiB || 2&nbsp;GiB || 1&nbsp;GiB || Size of each rank (bitmap).
|-
| 32 || 0x20 ||colspan=4| Tenths of nanoseconds (0.0–1.2) ||colspan=4| Hundredths of nanoseconds (0.00–0.09) || Address/command setup time from clock
|-
| 33 || 0x21 ||colspan=4| Tenths of nanoseconds (0.0–1.2) ||colspan=4| Hundredths of nanoseconds (0.00–0.09) || Address/command hold time after clock
|-
| 34 || 0x22 ||colspan=4| Tenths of nanoseconds (0.0–0.9) ||colspan=4| Hundredths of nanoseconds (0.00–0.09) || Data input setup time from strobe
|-
| 35 || 0x23 ||colspan=4| Tenths of nanoseconds (0.0–0.9) ||colspan=4| Hundredths of nanoseconds (0.00–0.09) || Data input hold time after strobe
|-
| 36 || 0x24 ||colspan=6| Nanoseconds (1–63) ||colspan=2| 0.25&nbsp;ns (0–0.75) || Minimum write recovery time (t<sub>WR</sub>)
|-
| 37 || 0x25 ||colspan=6| Nanoseconds (1–63) ||colspan=2| 0.25&nbsp;ns (0–0.75) || Internal write to read command delay (t<sub>WTR</sub>)
|-
| 38 || 0x26 ||colspan=6| Nanoseconds (1–63) ||colspan=2| 0.25&nbsp;ns (0–0.75) || Internal read to precharge command delay (t<sub>RTP</sub>)
|-
| 39 || 0x27 ||colspan=8 {{n/a|Reserved}} || Reserved for "memory analysis probe characteristics"
|-
| 40 || 0x28 || — ||colspan=3| t<sub>RC</sub> fractional ns (0–5):<br />0, 0.25, 0.33, 0.5, 0.66, 0.75 ||colspan=3| t<sub>RFC</sub> fractional ns (0–5):<br />0, 0.25, 0.33, 0.5, 0.66, 0.75 || t<sub>RFC</sub> + 256&nbsp;ns || Extension of bytes 41 and 42.
|-
| 41 || 0x29 ||colspan=8| Nanoseconds (1–255) || Minimum active to active/refresh time (t<sub>RC</sub>)
|-
| 42 || 0x2a ||colspan=8| Nanoseconds (1–255) || Minimum refresh to active/refresh time (t<sub>RFC</sub>)
|-
| 43 || 0x2b ||colspan=4| Nanoseconds (0–15) ||colspan=4| Tenths of nanoseconds (0.0–0.9) || Maximum clock cycle time (t<sub>CK</sub> max)
|-
| 44 || 0x2c ||colspan=8| Hundredths of nanoseconds (0.01–2.55) || Maximum skew, DQS to any DQ. (t<sub>DQSQ</sub> max)
|-
| 45 || 0x2d ||colspan=8| Hundredths of nanoseconds (0.01–2.55) || Read data hold skew factor (t<sub>QHS</sub>)
|-
| 46 || 0x2e ||colspan=8| Microseconds (1–255) || PLL relock time
|-
| 47–61 || 0x2f–0x3d ||colspan=8 {{n/a|Reserved}} || For future standardization.
|-
| 62 || 0x3e ||colspan=4| Major revision (0–9) ||colspan=4| Minor revision (0.0–0.9) || SPD revision level, usually 1.0
|-
| 63 || 0x3f ||colspan=8| Checksum || Sum of bytes 0–62, ''not negated''
|-
| 64–71 || 0x40–47 ||colspan=8| Manufacturer JEDEC ID || Stored little-endian, trailing zero-pad
|-
| 72 || 0x48 ||colspan=8| Module manufacturing location || Vendor-specific code
|-
| 73–90 || 0x49–0x5a ||colspan=8| Module part number || ASCII, space-padded (limited to (,-,), A–Z, a–z, 0–9, space)
|-
| 91–92 || 0x5b–0x5c ||colspan=8| Module revision code || Vendor-specific code
|-
| 93 || 0x5d ||colspan=8| Years since 2000 (0–255) ||rowspan=2| Manufacturing date (YYWW)
|-
| 94 || 0x5e ||colspan=8| Weeks (1–52)
|-
| 95–98 ||0x5f–0x62 ||colspan=8| Module serial number || Vendor-specific code
|-
| 99–127 || 0x63–0x7f ||colspan=8| Manufacturer-specific data || Could be enhanced performance profile
|}

===DDR3 SDRAM===
The DDR3 SDRAM standard significantly overhauls and simplifies the SPD contents layout.  Instead of a number of BCD-encoded nanosecond fields, some "timebase" units are specified to high precision, and various timing parameters are encoded as multiples of that base unit.<ref>{{Cite web|url=http://www.simmtester.com/page/news/showpubnews.asp?num=153|title=Understanding DDR3 Serial Presence Detect (SPD) Table|access-date=29 May 2010|archive-date=22 December 2015|archive-url=https://web.archive.org/web/20151222112142/http://www.simmtester.com/page/news/showpubnews.asp?num=153|url-status=dead}}</ref> Further, the practice of specifying different time values depending on the CAS latency has been dropped; now there are just a single set of timing parameters.

Revision 1.1 lets some parameters be expressed as a "medium time base" value plus a (signed, −128 +127) "fine time base" correction. Generally, the medium time base is 1/8 ns (125 ps), and the fine time base is 1, 2.5 or 5 ps.  For compatibility with earlier versions that lack the correction, the medium time base number is usually rounded up and the correction is negative. Values that work this way are:
{|class=wikitable
|+ DDR3 SPD two-part timing parameters
! MTB byte || FTB byte || Value
|-
| 12 || 34 || t<sub>CK</sub>min, minimum clock period
|-
| 16 || 35 || t<sub>AA</sub>min, minimum CAS latency time
|-
| 18 || 36 || t<sub>RCD</sub>min, minimum RAS# to CAS# delay
|-
| 20 || 37 || t<sub>RP</sub>min, minimum row precharge delay
|-
| 21, 23 || 38 || t<sub>RC</sub>min, minimum active to active/precharge delay
|}

{|class=wikitable
|+ SPD contents for DDR3 SDRAM<ref name=spd_ddr3_docs>[http://www.jedec.org/sites/default/files/docs/4_01_02_11R21.pdf JESD21-C Annex K: Serial Presence Detect for DDR3 SDRAM Modules], Release 4, SPD Revision 1.1</ref><ref>[http://www.softnology.biz/pdf/JEDEC_DDR3_SPD_4_01_02_11R24.pdf JESD21-C Annex K: Serial Presence Detect for DDR3 SDRAM Modules], Release 6, SPD Revision 1.3</ref>
|-
! colspan=2 | Byte
! colspan=8 | Bit
! rowspan=2 | Notes
|-
! Dec !! Hex !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
|  0 || 0x00 || Exclude serial from CRC ||colspan=3| SPD bytes total (undef/256) ||colspan=4| SPD bytes used (undef/128/176/256) ||
|-
|  1 || 0x01 ||colspan=4| SPD major revision ||colspan=4| SPD minor revision ||1.0, 1.1, 1.2 or 1.3
|-
|  2 || 0x02 ||colspan=8| Basic memory type (11 = DDR3 SDRAM) || Type of RAM chips
|-
|  3 || 0x03 ||colspan=4 {{n/a|Reserved}} ||colspan=4| Module type || Type of module; e.g., 2 = Unbuffered DIMM, 3 = SO-DIMM, 11=LRDIMM
|-
|  4 || 0x04 || {{n/a}} ||colspan=3| Bank address bits−3 ||colspan=4| log<sub>2</sub>(bits per chip)−28 || Zero means 8 banks, 256 Mibit.
|-
|  5 || 0x05 ||colspan=2 {{n/a}} ||colspan=3| Row address bits−12 ||colspan=3| Column address bits−9 ||
|-
|  6 || 0x06 ||colspan=5 {{n/a|Reserved}} || 1.25&nbsp;V || 1.35&nbsp;V || Not 1.5&nbsp;V || Modules voltages supported. 1.5&nbsp;V is default.
|-
|  7 || 0x07 ||colspan=2 {{n/a}} ||colspan=3| ranks−1 ||colspan=3| log<sub>2</sub>(I/O bits/chip)−2 || Module organization
|-
|  8 || 0x08 ||colspan=3 {{n/a}} ||colspan=2| ECC bits (001=8) ||colspan=3| log<sub>2</sub>(data bits)−3 || 0x03 for 64-bit, non-ECC DIMM.
|-
|  9 || 0x09 ||colspan=4| Dividend, picoseconds (1–15) ||colspan=4| Divisor, picoseconds (1–15) || Fine Time Base, dividend/divisor
|-
| 10 || 0x0a ||colspan=8| Dividend, nanoseconds (1–255) ||rowspan=2| Medium Time Base, dividend/divisor; commonly 1/8
|-
| 11 || 0x0b ||colspan=8| Divisor, nanoseconds (1–255)
|-
| 12 || 0x0c ||colspan=8| Minimum cycle time t<sub>CK</sub>min || In multiples of MTB
|-
| 13 || 0x0d ||colspan=8 {{n/a|Reserved}} ||
|-
| 14 || 0x0e || 11 || 10 || 9 || 8 || 7 || 6 || 5 || 4 ||rowspan=2| CAS latencies supported (bitmap)
|-
| 15 || 0x0f || {{n/a}} || 18 || 17 || 16 || 15 || 14 || 13 || 12
|-
| 16 || 0x10 ||colspan=8| Minimum CAS latency time, t<sub>AA</sub>min || In multiples of MTB; e.g., 80/8 ns.
|-
| 17 || 0x11 ||colspan=8| Minimum write recovery time, t<sub>WR</sub>min || In multiples of MTB; e.g., 120/8 ns.
|-
| 18 || 0x12 ||colspan=8| Minimum RAS to CAS delay time, t<sub>RCD</sub>min || In multiples of MTB; e.g., 100/8 ns.
|-
| 19 || 0x13 ||colspan=8| Minimum row to row active delay time, t<sub>RRD</sub>min || In multiples of MTB; e.g., 60/8 ns.
|-
| 20 || 0x14 ||colspan=8| Minimum row precharge time, t<sub>RP</sub>min || In multiples of MTB; e.g., 100/8 ns.
|-
| 21 || 0x15 ||colspan=4| t<sub>RC</sub>min, bits 11:8 ||colspan=4| t<sub>RAS</sub>min, bits 11:8 || Upper 4 bits of bytes 23 and 22
|-
| 22 || 0x16 ||colspan=8| Minimum active to time, t<sub>RAS</sub>min, bits 7:0 || In multiples of MTB; e.g., 280/8 ns.
|-
| 23 || 0x17 ||colspan=8| Minimum active to active/refresh, t<sub>RC</sub>min, bits 7:0 || In multiples of MTB; e.g., 396/8 ns.
|-
| 24 || 0x18 ||colspan=8| Minimum refresh recovery delay, t<sub>RFC</sub>min, bits 7:0 ||rowspan=2| In multiples of MTB; e.g., 1280/8 ns.
|-
| 25 || 0x19 ||colspan=8| Minimum refresh recovery delay, t<sub>RFC</sub>min, bits 15:8
|-
| 26 || 0x1a ||colspan=8| Minimum internal write to read delay, t<sub>WTR</sub>min || In multiples of MTB; e.g., 60/8 ns.
|-
| 27 || 0x1b ||colspan=8| Minimum internal read to precharge delay, t<sub>RTP</sub>min || In multiples of MTB; e.g., 60/8 ns.
|-
| 28 || 0x1c ||colspan=4 {{n/a|Reserved}} ||colspan=4| t<sub>FAW</sub>min, bits 11:8 ||rowspan=2| In multiples of MTB; e.g., 240/8 ns.
|-
| 29 || 0x1d ||colspan=8| Minimum four activate window delay t<sub>FAW</sub>min, bits 7:0
|-
| 30 || 0x1e || DLL-off ||colspan=5 {{n/a}} || RZQ/7 || RZQ/6 || SDRAM optional features support bitmap
|-
| 31 || 0x1f || PASR    ||colspan=3 {{n/a}} || ODTS || ASR || ETR 1× || ETR (95&nbsp;°C) || SDRAM thermal and refresh options
|-
| 32 || 0x20 || Present ||colspan=7| Accuracy (TBD; currently 0 = undefined) || DIMM thermal sensor present?
|-
| 33 || 0x21 || Nonstd. ||colspan=3| Die count ||colspan=2 {{n/a}} ||colspan=2| Signal load || Nonstandard SDRAM device type (e.g., stacked die)
|-
| 34 || 0x22 ||colspan=8| t<sub>CK</sub>min correction ''(new for 1.1)'' || Signed multiple of FTB, added to byte 12
|-
| 35 || 0x23 ||colspan=8| t<sub>AA</sub>min correction ''(new for 1.1)'' || Signed multiple of FTB, added to byte 16
|-
| 36 || 0x24 ||colspan=8| t<sub>RCD</sub>min correction ''(new for 1.1)'' || Signed multiple of FTB, added to byte 18
|-
| 37 || 0x25 ||colspan=8| t<sub>RP</sub>min correction ''(new for 1.1)'' || Signed multiple of FTB, added to byte 20
|-
| 38 || 0x26 ||colspan=8| t<sub>RC</sub>min correction ''(new for 1.1)'' || Signed multiple of FTB, added to byte 23
|-
| 39–40 || 0x27–0x28 ||colspan=8 {{n/a|Reserved}} || For future standardization.
|-
| 41 || 0x29 ||colspan=2| Vendor specific ||colspan=2| t<sub>MAW</sub> ||colspan=4| Maximum Activate Count (MAC) (untested/700k/600k/.../200k/reserved/∞) || For [[row hammer]] mitigation
|-
| 42–59 || 0x2a–0x3b ||colspan=8 {{n/a|Reserved}} || For future standardization.
|-
| 60 || 0x3c || colspan=3 {{n/a}} ||colspan=5 | Module height, mm (1–31, >45) || Module nominal height
|-
| 61 || 0x3d || colspan=4| Back thickness, mm (1–16) ||colspan=4 | Front thickness, mm (1–16) || Module thickness, value = ceil(mm) − 1
|-
| 62 || 0x3e || Design ||colspan=2|Revision ||colspan=5| JEDEC design number || JEDEC reference design used (11111=none)
|-
| 63–116 || 0x3f–0x74 ||colspan=8| Module-specific section || Differs between registered/unbuffered
|-
| 117 || 0x75 ||colspan=8| Module manufacturer ID, lsbyte ||rowspan=2| Assigned by JEP-106
|-
| 118 || 0x76 ||colspan=8| Module manufacturer ID, msbyte
|-
| 119 || 0x77 ||colspan=8| Module manufacturing location || Vendor-specific code
|-
| 120 || 0x78 ||colspan=4| Tens of years ||colspan=4| Years || Manufacturing year (BCD)
|-
| 121 || 0x79 ||colspan=4| Tens of weeks ||colspan=4| Weeks || Manufacturing week (BCD)
|-
| 122–125 || 0x7a–0x7d ||colspan=8| Module serial number || Vendor-specific code
|-
| 126–127 || 0x7e–0x7f ||colspan=8| SPD CRC-16 || Includes bytes 0–116 or 0–125; see byte 0 bit 7
|-
| 128–145 || 0x80–0x91 ||colspan=8| Module part number || ASCII subset, space-padded
|-
| 146–147 || 0x92–0x93 ||colspan=8| Module revision code || Vendor-defined
|-
| 148–149 || 0x94–0x95 ||colspan=8| DRAM manufacturer ID || As distinct from module manufacturer
|-
| 150–175 || 0x96–0xAF ||colspan=8| Manufacturer-specific data
|-
| 176–255 || 0xB0–0xFF ||colspan=8| Available for customer use
|}
The memory capacity of a module can be computed from bytes 4, 7 and 8.  The module width (byte 8) divided by the number of bits per chip (byte 7) gives the number of chips per rank.  That can then be multiplied by the per-chip capacity (byte 4) and the number of ranks of chips on the module (usually 1 or 2, from byte 7).

=== DDR4 SDRAM ===
The DDR4 SDRAM "Annex L" standard for SPD changes the EEPROM module used. Instead of the old AT24C02-compatible 256-byte EEPROMs, JEDEC now defines a new nonstandard EE1004 type with two pages at the SMBus level each with 256 bytes. The new memory still uses the old 0x50–0x57 addresses, but two additional address at 0x36 (SPA0) and 0x37 (SPA1) are now used to receive commands to select the currently-active page for the bus, a form of [[bank switching]].<ref>{{cite web |last1=Delvare |first1=Jean |title=[PATCH] eeprom: New ee1004 driver for DDR4 memory |url=https://lkml.org/lkml/2017/11/20/131 |website=LKML |accessdate=7 November 2019}}</ref> Internally each logical page is further divided into two physical blocks of 128 bytes each, totaling four blocks and 512 bytes.<ref name=annex_l>{{cite web |author1=JEDEC |title=Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules |url=http://www.softnology.biz/pdf/4_01_02_AnnexL-R25_SPD_for_DDR4_SDRAM_Release_3_Sep2015.pdf}}</ref> Other semantics for "special" address ranges remain the same, although write protection is now addressed by blocks and a high voltage at SA0 is now required to change its status.<ref name="TSE2004">{{cite web |author1=JEDEC |title=EE1004 and TSE2004 Device Specification (Draft) |url=http://www.softnology.biz/pdf/ee1004_tse2004.pdf |accessdate=7 November 2019}}</ref>

Annex L defines a few different layouts that can be plugged into a 512-byte (of which a maximum of 320 bytes are defined) template, depending on the type of the memory module. The bit definitions are similar to DDR3.<ref name=annex_l/>

{|class=wikitable
|+ SPD contents for DDR4 SDRAM<ref name=spd_ddr4_docs>[https://www.jedec.org/system/files/docs/4_01_02_AnnexL-5R29.pdf JESD21-C Annex L: Serial Presence Detect for DDR4 SDRAM Modules], Release 5</ref>
|-
! colspan=2 | Byte
! colspan=8 | Bit
! rowspan=2 | Notes
|-
! Dec !! Hex !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
|  0 || 0x00 ||colspan=8| SPD bytes used
|-
|  1 || 0x01 ||colspan=8| SPD revision n || Typically 0x10, 0x11, 0x12
|-
|  2 || 0x02 ||colspan=8| Basic memory type (12 = DDR4 SDRAM) || Type of RAM chips
|-
|  3 || 0x03 ||colspan=4 {{n/a|Reserved}} ||colspan=4| Module type || Type of module; e.g., 2 = Unbuffered DIMM, 3 = SO-DIMM, 11=LRDIMM
|-
|  4 || 0x04 ||colspan=2| Bank group bits ||colspan=2| Bank address bits−2 ||colspan=4| Total SDRAM capacity per die in megabits || Zero means no bank groups, 4 banks, 256 Mibit.
|-
|  5 || 0x05 ||colspan=2 {{n/a|Reserved}} ||colspan=3| Row address bits−12 ||colspan=3| Column address bits−9 ||
|-
|  6 || 0x06 || Primary SDRAM package type ||colspan=3| Die count ||colspan=2 {{n/a|Reserved}} ||colspan=2| Signal loading
|-
|  7 || 0x07 ||colspan=2 {{n/a|Reserved}} ||colspan=2| Maximum activate window (tMAW) ||colspan=4| Maximum activate count (MAC) || SDRAM optional features
|-
|  8 || 0x08 ||colspan=8 {{n/a|Reserved}} || SDRAM thermal and refresh options
|-
|  9 || 0x09 ||colspan=2| Post package repair (PPR) || Soft PPR ||colspan=5 {{n/a|Reserved}} || Other SDRAM optional features
|-
| 10 || 0x0a || SDRAM package type ||colspan=3| Die count−1 ||colspan=2| DRAM density ratio ||colspan=2| Signal loading || Secondary SDRAM package type
|-
| 11 || 0x0b ||colspan=6 {{n/a|Reserved}} || Endurant flag || Operable flag || Module nominal voltage, VDD
|-
| 12 || 0x0c || {{n/a|Reserved}} || Rank mix ||colspan=3| Package ranks per DIMM−1 ||colspan=3| SDRAM device width || Module organization
|-
| 13 || 0x0d ||colspan=3 {{n/a|Reserved}} ||colspan=2| Bus width extension||colspan=3|Primary bus width||Module memory bus width in bits
|-
| 14 || 0x0e || Thermal sensor ||colspan=7 {{n/a|Reserved}} || Module thermal sensor
|-
| 15 || 0x0f ||colspan=4 {{n/a|Reserved}} ||colspan=4|Extended base module type
|-
| 16 || 0x10 ||colspan=8 {{n/a|Reserved}}
|-
| 17 || 0x11 ||colspan=4 {{n/a|Reserved}} ||colspan=2| Medium timebase (MTB)||colspan=2| Fine timebase (FTB) || Measured in ps.
|-
| 18 || 0x12 ||colspan=8| Minimum SDRAM cycle time, t<sub>CKAVG</sub>min || In multiples of MTB; e.g., 100/8 ns.
|-
| 19 || 0x13 ||colspan=8| Maximum SDRAM cycle time, t<sub>CKAVG</sub>max || In multiples of MTB; e.g., 60/8 ns.
|-
| 20 || 0x14 || 14 || 13 || 12 || 11 || 10 || 9 || 8 || 7 || CAS latencies supported bit-mask
|-
| 21 || 0x15 || 22 || 21 || 20 || 19 || 18 || 17 || 16 || 15 || CAS latencies supported bit-mask
|-
| 22 || 0x16 || 30 || 29 || 28 || 27 || 26 || 25 || 24 || 23 || CAS latencies supported bit-mask
|-
| 23 || 0x17 ||Low CL range|| {{n/a|Reserved}} || 36 || 35 || 34 || 33 || 32 || 31 || CAS latencies supported bit-mask
|-
| 24 || 0x18 ||colspan=8| Minimum CAS latency time, t<sub>AA</sub>min || In multiples of MTB; e.g., 1280/8 ns.
|-
| 25 || 0x19 ||colspan=8| Minimum RAS to CAS delay time, t<sub>RCD</sub>min || In multiples of MTB; e.g., 60/8 ns.
|-
| 26 || 0x1a ||colspan=8| Minimum row precharge delay time, t<sub>RP</sub>min || In multiples of MTB; e.g., 60/8 ns.
|-
| 27 || 0x1b ||colspan=8| Upper nibbles for t<sub>RAS</sub>min and t<sub>RC</sub>min
|-
| 28 || 0x1c ||colspan=8| Minimum active to precharge delay time, t<sub>RAS</sub>min least significant byte || In multiples of MTB
|-
| 29 || 0x1d ||colspan=8| Minimum active to active/refresh delay time, t<sub>RC</sub>min least significant byte || In multiples of MTB
|-
| 30 || 0x1e ||colspan=8| Minimum refresh recovery delay time, t<sub>RFC1</sub>min least significant byte || In multiples of MTB
|-
| 31 || 0x1f ||colspan=8| Minimum refresh recovery delay time, t<sub>RFC1</sub>min most significant byte || In multiples of MTB
|-
| 32 || 0x20 ||colspan=8| Minimum refresh recovery delay time, t<sub>RFC2</sub>min least significant byte || In multiples of MTB
|-
| 33 || 0x21 ||colspan=8| Minimum refresh recovery delay time, t<sub>RFC2</sub>min most significant byte || In multiples of MTB
|-
| 34 || 0x22 ||colspan=8| Minimum refresh recovery delay time, t<sub>RFC4</sub>min least significant byte || In multiples of MTB
|-
| 35 || 0x23 ||colspan=8| Minimum refresh recovery delay time, t<sub>RFC4</sub>min most significant byte || In multiples of MTB
|-
| 36 || 0x24 ||colspan=4 {{n/a|Reserved}} ||colspan=4| t<sub>FAW</sub>min most significant nibble
|-
| 37 || 0x25 ||colspan=8| Minimum four activate window delay time, t<sub>FAW</sub>min least significant byte || In multiples of MTB
|-
| 38 || 0x26 ||colspan=8| Minimum activate to activate delay time, t<sub>RRD_S</sub>min, different bank group || In multiples of MTB
|-
| 39 || 0x27 ||colspan=8| Minimum activate to activate delay time, t<sub>RRD_L</sub>min, same bank group || In multiples of MTB
|-
| 40 || 0x28 ||colspan=8| Minimum CAS to CAS delay time, t<sub>CCD_L</sub>min, same bank group || In multiples of MTB
|-
| 41 || 0x29 ||colspan=8| Upper nibble for t<sub>WR</sub>min
|-
| 42 || 0x2a ||colspan=8| Minimum write recovery time, t<sub>WR</sub>min || In multiples of MTB
|-
| 43 || 0x2b ||colspan=8| Upper nibbles for t<sub>WTR</sub>min
|-
| 44 || 0x2c ||colspan=8| Minimum write to read time, t<sub>WTR_S</sub>min, different bank group || In multiples of MTB
|-
| 45 || 0x2d ||colspan=8| Minimum write to read time, t<sub>WTR_L</sub>min, same bank group || In multiples of MTB
|-
| 49–59 || 0x2e–0x3b ||colspan=8 {{n/a|Reserved}} || Base configuration section
|-
| 60–77 || 0x3c–0x4d || colspan=8| Connector to SDRAM bit mapping
|-
| 78–116 || 0x4e–0x74 ||colspan=8 {{n/a|Reserved}} || Base configuration section
|-
| 117 || 0x75 ||colspan=8| Fine offset for minimum CAS to CAS delay time, t<sub>CCD_L</sub>min, same bank || Two's complement multiplier for FTB units
|-
| 118 || 0x76 ||colspan=8| Fine offset for minimum activate to activate delay time, t<sub>RRD_L</sub>min, same bank group || Two's complement multiplier for FTB units
|-
| 119 || 0x77 ||colspan=8| Fine offset for minimum activate to activate delay time, t<sub>RRD_S</sub>min, different bank group || Two's complement multiplier for FTB units
|-
| 120 || 0x78 ||colspan=8| Fine offset for minimum active to active/refresh delay time, t<sub>RC</sub>min || Two's complement multiplier for FTB units
|-
| 121 || 0x79 ||colspan=8| Fine offset for minimum row precharge delay time, t<sub>RP</sub>min || Two's complement multiplier for FTB units
|-
| 122 || 0x7a ||colspan=8| Fine offset for minimum RAS to CAS delay time, t<sub>RCD</sub>min || Two's complement multiplier for FTB units
|-
| 123 || 0x7b ||colspan=8| Fine offset for minimum CAS latency time, t<sub>AA</sub>min || Two's complement multiplier for FTB units
|-
| 124 || 0x7c ||colspan=8| Fine offset for SDRAM maximum cycle time, t<sub>CKAVG</sub>max || Two's complement multiplier for FTB units
|-
| 125 || 0x7d ||colspan=8| Fine offset for SDRAM minimum cycle time, t<sub>CKAVG</sub>min || Two's complement multiplier for FTB units
|-
| 126 || 0x7e ||colspan=8| Cyclic rendundancy code (CRC) for base config section, least significant byte || CRC16 algorithm
|-
| 127 || 0x7f ||colspan=8| Cyclic rendundancy code (CRC) for base config section, most significant byte || CRC16 algorithm
|-
| 128–191 || 0x80–0xbf ||colspan=8| Module-specific section || Dependent upon memory module family (UDIMM, RDIMM, LRDIMM)
|-
| 192–255 || 0xc0–0xff ||colspan=8| Hybrid memory architecture specific parameters
|-
| 256–319 || 0x100–0x13f ||colspan=8| Extended function parameter block
|-
| 320–321 || 0x140–0x141 ||colspan=8| Module manufacturer || See JEP-106
|-
| 322 || 0x142 ||colspan=8| Module manufacturing location || Manufacturer-defined manufacturing location code
|-
| 323 || 0x143 ||colspan=8| Module manufacturing year || Represented in Binary Coded Decimal (BCD)
|-
| 324 || 0x144 ||colspan=8| Module manufacturing week || Represented in Binary Coded Decimal (BCD)
|-
| 325–328 || 0x145–0x148 ||colspan=8| Module serial number || Manufacturer-defined format for a unique serial number across part numbers
|-
| 329–348 || 0x149–0x15c ||colspan=8| Module part number || ASCII part number, unused digits should be set to 0x20
|-
| 349 || 0x15d ||colspan=8| Module revision code || Manufacturer-defined revision code
|-
| 350–351 || 0x15e–0x15f ||colspan=8| DRAM manufacturer ID code || See JEP-106
|-
| 352 || 0x160 ||colspan=8| DRAM stepping || Manufacturer-defined stepping or 0xFF if not used
|-
| 353–381 || 0x161–0x17d ||colspan=8| Manufacturer's specific data
|-
| 382–383 || 0x17e–0x17f ||colspan=8 {{n/a|Reserved}}
|}

=== DDR5 SDRAM ===
Preliminary table for DDR5, based on JESD400-5 specification.<ref>{{Cite web |year=2023 |title=JESD400-5B(JESD400-5B) |url=https://www.jedec.org/standards-documents/docs/jesd400-5b |access-date=31 December 2023 |website=[[jedec]]}}</ref>

DDR5 expands the SPD table to 1024-byte. SPD of DDR5 is using the [[I3C (bus)|I3C]] bus.

{|class=wikitable
|+ SPD contents for DDR5 SDRAM
|-
! colspan=2 | Byte
! colspan=8 | Bit
! rowspan=2 | Notes
|-
! Dec !! Hex !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
|  0 || 0x00 ||colspan=8| Number of bytes in SPD device ||
|-
|  1 || 0x01 ||colspan=8| SPD revision for base configuration parameters ||
|-
|  2 || 0x02 ||colspan=8| Key byte / host bus command protocol type ||
|-
|  3 || 0x03 ||colspan=8| Key byte / module type ||
|-
|  4 || 0x04 ||colspan=8| First SDRAM density and package ||
|-
|  5 || 0x05 ||colspan=8| First SDRAM addressing ||
|-
|  6 || 0x06 ||colspan=8| First SDRAM I/O width ||
|-
|  7 || 0x07 ||colspan=8| First SDRAM bank groups & banks per bank group ||
|-
|  8 || 0x08 ||colspan=8| Second SDRAM density and package ||
|-
|  9 || 0x09 ||colspan=8| Second SDRAM addressing ||
|-
| 10 || 0x0a ||colspan=8| Second SDRAM I/O width ||
|-
| 11 || 0x0b ||colspan=8| Second SDRAM bank groups & banks per bank group ||
|-
| 12 || 0x0c ||colspan=8| SDRAM optional features ||
|-
| 13 || 0x0d ||colspan=8| Thermal and refresh options || 
|-
| 14 || 0x0e ||colspan=8 {{n/a|Reserved}} ||
|-
| 15 || 0x0f ||colspan=8 {{n/a|Reserved}} ||
|-
| 16 || 0x10 ||colspan=8| SDRAM nominal voltage, VDD ||
|-
|}

==Extensions==
The JEDEC standard only specifies some of the SPD bytes.  The truly critical data fits into the first 64 bytes,<ref name=spd_ddr>[http://www.jedec.org/download/search/4_01_02_04R13.PDF JEDEC Standard 21-C section 4.1.2.4] "SPDs for DDR SDRAM"</ref><ref name=spd_ddr2>[http://www.jedec.org/download/search/4_01_02_10R13.pdf JEDEC Standard 21-C section 4.1.2.10] "Specific SPDs for DDR2 SDRAM"</ref><ref name=spd_ddr3>[http://www.jedec.org/download/search/4_01_02_11R18.pdf JEDEC Standard 21-C section 4.1.2.11] "Serial Presence Detect (SPD) for DDR3 SDRAM Modules"</ref><ref name=spd_base>[http://www.jedec.org/download/search/4_01_02_00r9.pdf JEDEC Standard 21-C section 4.1.2] "SERIAL PRESENCE DETECT STANDARD, General Standard"</ref><ref name=spd_sdr>[http://www.jedec.org/download/search/4_01_02_05R12.PDF JEDEC Standard 21-C section 4.1.2.5] "Specific PDs for Synchronous DRAM (SDRAM)"</ref> while some of the remainder is earmarked for manufacturer identification.  However, a 256-byte EEPROM is generally provided.  A number of uses have been made of the remaining space.

Memory generally comes with conservative timing recommendations in the SPD ROM, to ensure basic functionality on all systems. Enthusiasts often spend considerable time manually adjusting the memory timings for higher speed. Enabling special configurations such as Intel XMP or AMD EXPO often requires additional testing to ensure system stability<ref>{{cite web |title=What Is XMP, and Why Does It Matter for RAM? |url=https://www.howtogeek.com/what-is-xmp/ |publisher=How-To Geek |access-date=19 May 2025 |date=21 September 2023}}</ref> and may void CPU warranty if used out of the manufacturer’s published specifications.<ref>{{cite web |title=Why XMP and memory overclocking are OK even if they void your warranty |url=https://www.pcworld.com/article/394250/why-xmp-and-memory-overclocking-are-ok-even-if-they-void-your-warranty.html |publisher=PCWorld |access-date=19 May 2025 |date=16 March 2021}}</ref><ref>{{cite web |title=AMD Ryzen 7000 Burning Out: EXPO and SoC Voltages to Blame (AMD Responds) |url=https://www.tomshardware.com/news/amd-ryzen-7000-burning-out-root-cause-identified-expo-and-soc-voltages-to-blame |publisher=Tom's Hardware |access-date=19 May 2025 |date=25 April 2023}}</ref><ref>{{cite web |title=Intel® Extreme Memory Profile (Intel® XMP) |url=https://www.intel.com/content/www/us/en/gaming/extreme-memory-profile-xmp.html |publisher=Intel |access-date=19 May 2025 |quote=Altering clock frequency or voltage may damage or reduce the useful life of the processor and other system components, and may reduce system stability and performance. Product warranties may not apply if the processor is operated beyond its specifications.}}</ref>

===Enhanced Performance Profiles (EPP)===
Enhanced Performance Profiles is an extension of SPD, developed by [[Nvidia]] and [[Corsair Gaming|Corsair]], which includes additional information for higher-performance operation of [[DDR2 SDRAM]], including supply voltages and command timing information not included in the JEDEC SPD spec.  The EPP information is stored in the same EEPROM, but in bytes 99–127, which are unused by standard DDR2 SPD.<ref>{{Citation |url=http://www.nvidia.com/content/epp/epp_specifications.pdf |title=DDR2 UDIMM Enhanced Performance Profiles Design Specification |publisher=[[Nvidia]] |date=2006-05-12 |accessdate=2009-05-05}}</ref>

{|class=wikitable
|+ EPP SPD ROM usage
|-
! Bytes !! Size !! Full profiles !! Abbreviated profiles
|-
|  99–103 || 5 ||colspan=2| EPP header
|-
| 104–109 || 6 ||rowspan=2| Profile FP1 || Profile AP1
|-
| 110–115 || 6 || Profile AP2
|-
| 116–121 || 6 ||rowspan=2| Profile FP2 || Profile AP3
|-
| 122–127 || 6 || Profile AP4
|}
The parameters are particularly designed to fit the memory controller on the [[NForce 500|nForce 5]], [[NForce 600|nForce 6]] and [[NForce 700|nForce 7]] chipsets.  Nvidia encourages support for EPP in the [[BIOS]] for its high-end motherboard chipsets.  This is intended to provide "one-click [[overclocking]]" to get better performance with minimal effort.

Nvidia's name for EPP memory that has been qualified for performance and stability is "SLI-ready memory".<ref>{{Cite web| title=Technical Brief - SLI-Ready Memory with Enhanced Performance Profiles One-Click Hassle-Free Memory Performance Boost | url=http://www.nvidia.com/docs/CP/45121/sli_memory.pdf | archive-url=https://web.archive.org/web/20081207172621/http://www.nvidia.com/docs/CP/45121/sli_memory.pdf | archive-date=2008-12-07}}</ref> The term "SLI-ready-memory" has caused some confusion, as it has nothing to do with [[Scalable Link Interface|SLI video]].  One can use EPP/SLI memory with a single video card (even a non-Nvidia card), and one can run a multi-card SLI video setup without EPP/SLI memory.

An extended version, EPP 2.0, supports DDR3 memory as well.<ref>[http://www.nvidia.com/docs/IO/52280/NVIDIA_EPP2_TB.pdf Enhanced Performance Profiles 2.0] (pp.  2–3)</ref>

=== {{Anchor|XMP}}Intel Extreme Memory Profile (XMP) ===
{{Redirect-distinguish|Intel XMP|Intel MPX}}
A similar, [[Intel]]-developed JEDEC SPD extension was developed for [[DDR3 SDRAM]] DIMMs, later used in [[DDR4 SDRAM|DDR4]] and [[DDR5 SDRAM]] as well. XMP uses bytes 176–255, which are unallocated by JEDEC, to encode higher-performance memory timings.<ref>{{Cite web |title=What Is Intel Extreme Memory Profile (Intel XMP)? |url=https://www.intel.co.uk/content/www/uk/en/gaming/extreme-memory-profile-xmp.html |website=Intel |access-date=September 26, 2022}}</ref>

Later, AMD developed AMP, an equivalent technology to XMP, for use in its "Radeon Memory" line of memory modules optimized for use in AMD platforms.<ref>{{cite web |title=Memory Profile Technology - AMP up your RAM|url=https://www.amd.com/en/technologies/amp |website=AMD |date=2012 |access-date=January 8, 2018}}</ref><ref>{{cite web |last1=Martin |first1=Ryan |date=July 23, 2012 |title=AMD introduces its XMP-equivalent AMP - eTeknix |url=https://www.eteknix.com/amd-introduces-its-xmp-equivalent-amp/ |website=eTeknix |access-date=January 8, 2018}}</ref> Furthermore, motherboard developers implemented their own technologies to allow their AMD-based motherboards to read XMP profiles: MSI offers A-XMP,<ref>{{cite web |title=MSI is worlds first brand to enable A-XMP on Ryzen for best DDR4 performance, launches new models |url=https://www.msi.com/news/detail/0ec96be397dd6d3cf2fecb4a2d627c1c |website=MSI |date=March 21, 2017 |access-date=January 8, 2018}}</ref> ASUS has DOCP (Direct Over Clock Profile), and Gigabyte has EOCP (Extended Over Clock Profile).<ref>{{cite web |author=Tradesman1 |title=What does XMP, DOCP, EOCP mean - Solved - Memory |url=http://www.tomshardware.com/answers/id-3167421/xmp-docp-eocp.html#r18503260 |website=Tom's Hardware Forums |date=August 26, 2016 |access-date=January 8, 2018}}</ref>
{|class=wikitable
|+ XMP SPD ROM usage<ref name="xmp1.1">{{Cite web |title=Intel Extreme Memory Profile (XMP) Specification, Rev 1.1 |url=http://www.softnology.biz/pdf/Intel_XMP_Spec_Rev1.1.pdf |archive-url=https://web.archive.org/web/20120306230940/http://www.softnology.biz/pdf/IntelXMP_Rev1.1.pdf |website=Intel |archive-date=March 6, 2012 |date=October 2007 |access-date=May 25, 2010}}</ref>
|-
! DDR3 Bytes !! Size !! Use
|-
| 176–184 || 10 || XMP header
|-
| 185–219 || 33 || XMP profile 1 ("enthusiast" settings)
|-
| 220–254 || 36 || XMP profile 2 ("extreme" settings)
|}
<!-- Still searching for more details.  According to http://www.legitreviews.com/article/613/1/, bytes 206–209 and 241–244 are platform-specific bytes, only used in manual XMP mode -->
<!-- Note that a later [http://www.softnology.biz/pdf/IntelXMP_WP.pdf white paper for DDR3] seems to have ditched the profile 1 personality byte and moved profile 2 a bit forward. Someone will need to dump it and check it. -->

The header contains the following data.  Most importantly, it contains a "medium timebase" value MTB, as a rational number of nanoseconds (common values are 1/8, 1/12 and 1/16 ns).  Many other later timing values are expressed as an integer number of MTB units.

Also included in the header is the number of DIMMs per memory channel that the profile is designed to support; including more DIMMs may not work well.
{|class="wikitable"
|+ XMP Header bytes<ref name="xmp1.1"/>
|-
! DDR3 Byte !! Bits !! Use
|-
| 176 || 7:0 || XMP [[Magic number (programming)|magic number]] byte 1 0x0C
|-
| 177 || 7:0 || XMP magic number byte 2 0x4A
|-
|rowspan=5| 178 || 0 || Profile 1 enabled (if 0, disabled)
|-
| 1 || Profile 2 enabled
|-
| 3:2 || Profile 1 DIMMs per channel (1–4 encoded as 0–3)
|-
| 5:4 || Profile 2 DIMMs per channel
|-
| 7:6 || {{n/a|Reserved}}
|-
|rowspan=2| 179 || 3:0 || XMP minor version number (x.0 or x.1)
|-
| 7:4 || XMP major version number (0.x or 1.x)
|-
| 180 || 7:0 || Medium timebase dividend for profile 1
|-
| 181 || 7:0 || Medium timebase divisor for profile 1 (MTB = dividend/divisor ns)
|-
| 182 || 7:0 || Medium timebase dividend for profile 2 (e.g. 8)
|-
| 183 || 7:0 || Medium timebase divisor for profile 2 (e.g. 1, giving MTB = 1/8 ns)
|-
| 184 || 7:0 ||  {{n/a|Reserved}}
|}
{|class="wikitable"
|+ XMP profile bytes<ref name="xmp1.1"/>
|-
! DDR3 Byte 1 !! DDR3 Byte 2 !! Bits !! Use
|-
|rowspan=4| 185 ||rowspan=4| 220 || 0 || Module Vdd voltage twentieths (0.00 or 0.05)
|-
| 4:1 || Module Vdd voltage tenths (0.0–0.9)
|-
| 6:5 || Module Vdd voltage units (0–2)
|-
| 7 ||  {{n/a|Reserved}}
|-
| 186 || 221 || 7:0 || Minimum SDRAM clock period t<sub>CK</sub>min (MTB units)
|-
| 187 || 222 || 7:0 || Minimum CAS latency time t<sub>AA</sub>min (MTB units)
|-
| 188 || 223 || 7:0 || CAS latencies supported (bitmap, 4–11 encoded as bits 0–7)
|-
|rowspan=2| 189 ||rowspan=2| 224 || 6:0 || CAS latencies supported (bitmap, 12–18 encoded as bits 0–6)
|-
| 7 ||  {{n/a|Reserved}}
|-
| 190 || 225 || 7:0 || Minimum CAS write latency time t<sub>CWL</sub>min (MTB units)
|-
| 191 || 226 || 7:0 || Minimum row precharge delay time t<sub>RP</sub>min (MTB units)
|-
| 192 || 227 || 7:0 || Minimum RAS to CAS delay time t<sub>RCD</sub>min (MTB units)
|-
| 193 || 228 || 7:0 || Minimum write recovery time t<sub>WR</sub>min (MTB units)
|-
|rowspan=2| 194 ||rowspan=2| 229 || 3:0 || t<sub>RAS</sub>min upper [[nibble]] (bits 11:8)
|-
| 7:4 || t<sub>RC</sub>min upper nibble (bits 11:8)
|-
| 195 || 230 || 7:0 || Minimum active to precharge delay time t<sub>RAS</sub>min bits 7:0 (MTB units)
|-
| 196 || 231 || 7:0 || Minimum active to active/refresh delay time t<sub>RC</sub>min bits 7:0 (MTB units)
|-
| 197 || 232 || 7:0 || Maximum average refresh interval t<sub>REFI</sub> lsbyte (MTB units)
|-
| 198 || 233 || 7:0 || Maximum average refresh interval t<sub>REFI</sub> msbyte (MTB units)
|-
| 199 || 234 || 7:0 || Minimum refresh recovery delay time t<sub>RFC</sub>min lsbyte (MTB units)
|-
| 200 || 235 || 7:0 || Minimum refresh recovery delay time t<sub>RFC</sub>min msbyte (MTB units)
|-
| 201 || 236 || 7:0 || Minimum internal read to precharge command delay time t<sub>RTP</sub>min (MTB units)
|-
| 202 || 237 || 7:0 ||  Minimum row active to row active delay time t<sub>RRD</sub>min (MTB units)
|-
|rowspan=2| 203 ||rowspan=2| 238 || 3:0 || t<sub>FAW</sub>min upper nibble (bits 11:8)
|-
| 7:4 ||  {{n/a|Reserved}}
|-
| 204 || 239 || 7:0 || Minimum four activate window delay time t<sub>FAW</sub>min bits 7:0 (MTB units)
|-
| 205 || 240 || 7:0 || Minimum internal write to read command delay time t<sub>WTR</sub>min (MTB units)
|-
|rowspan=4| 206 ||rowspan=4| 241 || 2:0 || Write to read command turnaround time adjustment (0–7 clock cycles)
|-
| 3 || Write to read command turnaround adjustment sign (0=pull-in, 1=push-out)
|-
| 6:4 || Read to write command turnaround time adjustment (0–7 clock cycles)
|-
| 7 || Read to write command turnaround adjustment sign (0=pull-in, 1=push-out)
|-
|rowspan=3| 207 ||rowspan=3| 242 || 2:0 || Back-to-back command turnaround time adjustment (0–7 clock cycles)
|-
| 3 || Back-to-back turnaround adjustment sign (0=pull-in, 1=push-out)
|-
| 7:4 ||  {{n/a|Reserved}}
|-
| 208 || 243 || 7:0 || System CMD rate mode.  0=JTAG default, otherwise in peculiar units of MTB × t<sub>CK</sub>/ns.<br />E.g. if MTB is 1/8 ns, then this is in units of 1/8 clock cycle.
|-
| 209 || 244 || 7:0 || SDRAM auto self refresh performance.<br />Standard version 1.1 says documentation is [[Wikt:TBD|TBD]].
|-
| 210–218 || 245–253 || 7:0 ||  {{n/a|Reserved}}
|-
| 219 || 254 || 7:0 || ''Reserved'', vendor-specific personality code.
|}

All data above are for DDR3 (XMP 1.1); DDR4 specs are not yet available.

=== {{Anchor|EXPO}}AMD Extended Profiles for Overclocking (EXPO) ===
AMD's Extended Profiles for Overclocking (EXPO) is a JEDEC SPD extension developed for [[DDR5 SDRAM|DDR5]] DIMMs to apply a one-click automatic overclocking profile to system memory.<ref>{{cite web |title=AMD Extended Profiles for Overclocking |url=https://www.amd.com/en/technologies/expo |website=AMD |access-date=September 26, 2022}}</ref><ref name="JRoachDigitalTrends">{{cite web |last1=Roach |first1=Jacob |date=September 6, 2022 |title=What is AMD EXPO and should my DDR5 have it? |url=https://www.digitaltrends.com/computing/what-is-amd-expo/ |website=Digital Trends |access-date=September 26, 2022}}</ref> AMD EXPO-certified DIMMs include optimised timings that optimise the performance of its [[Zen 4]] processors.<ref>{{cite web |last1=Bonshor |first1=Gavin |date=August 30, 2022 |title=AMD EXPO Memory Technology: One Click Overclocking Profiles For Ryzen 7000 |url=https://www.anandtech.com/show/17556/amd-expo-memory-one-click-overclocking-profiles-for-ryzen-7000-feat-gskill-and-corsair |website=AnandTech |access-date=September 26, 2022}}</ref> Unlike Intel's closed standard XMP, the EXPO standard is open and royalty-free.<ref name="JRoachDigitalTrends" /> It can be used on Intel platforms.<ref name="JRoachDigitalTrends" /> At launch in September 2022, there are 15 partner RAM kits with EXPO-certification available reaching up to 6400 MT/s.<ref>{{cite web |title=AMD announces EXPO technology for DDR5 memory overclocking |url=https://videocardz.com/newz/amd-announces-expo-technology-for-ddr5-memory-overclocking |website=VideoCardz |date=August 30, 2022 |access-date=September 26, 2022}}</ref>

===Vendor-specific memory===
A common misuse is to write information to certain memory regions to bind vendor-specific memory modules to a specific system. [[Fujitsu Technology Solutions]] is known to do this. Adding different memory module to the system usually results in a refusal or other counter-measures (like pressing F1 on every boot).

<pre>
02 0E 00 01-00 00 00 EF-02 03 19 4D-BC 47 C3 46 ...........M.G.F
53 43 00 04-EF 4F 8D 1F-00 01 70 00-01 03 C1 CF SC...O....p.....
</pre>

This is the output of a 512&nbsp;MB memory module from Micron Technologies, branded for Fujitsu-Siemens Computers, note the "FSC" string.
The system BIOS rejects memory modules that don't have this information starting at offset 128h.

Some Packard Bell AMD laptops also use this method, in this case the symptoms can vary but it can lead to a flashing cursor rather than a beep pattern. Incidentally this can also be a symptom of BIOS corruption as well.<ref>{{Cite web|url=https://forums.tomshardware.com/threads/packard-bell-lj65-ram-upgrade.1651388/|title=Packard Bell LJ65 RAM upgrade|website=Tom's Hardware Forum|date=9 January 2014 }}</ref> Though upgrading a 2&nbsp;GB to a 4&nbsp;GB can also lead to issues.

==Reading and writing SPD information==
Memory module manufacturers write the SPD information to the [[EEPROM]] on the module. Motherboard [[BIOS]]es read the SPD information to configure the memory controller. There exist several programs that are able to read and modify SPD information on most, but not all motherboard chipsets.
* [http://www.nongnu.org/dmidecode/ dmidecode] program that can decode information about memory (and other things) and runs on [[Linux]], [[FreeBSD]], [[NetBSD]], [[OpenBSD]], [[BeOS]], [[Cygwin]] and [[Solaris (operating system)|Solaris]]. dmidecode does not access SPD information directly; it reports the [[SMBIOS]] data about the memory.<ref>{{Cite web|url=https://www.linux.com/news/dmidecode-whats-it-good|title=dmidecode: What's it good for?|date=29 November 2004|website=Linux.com {{pipe}} The source for Linux information}}</ref> This information may be limited or incorrect.
* On [[Linux]] systems and [[FreeBSD]], the [[user space]] program decode-dimms provided by i2c-tools decodes and prints information on any memory with SPD information in the computer.<ref>{{cite web|title=decode-dimms(1)|website=Debian Manpage |url=http://manpages.debian.org/testing/i2c-tools/decode-dimms.1.en.html|accessdate=2020-12-16}}</ref><ref>{{Cite web|title=decode-dimms|url=https://www.freebsd.org/cgi/man.cgi?query=decode-dimms|access-date=2021-01-24|website=www.freebsd.org}}</ref> It requires [[System Management Bus|SMBus]] controller support in the kernel, the EEPROM kernel driver, and also that the SPD EEPROMs are connected to the SMBus. On older Linux distributions, decode-dimms.pl was available as part of [[lm_sensors]].
* OpenBSD has included a driver ([https://man.openbsd.org/spdmem.4 spdmem(4)]) since version 4.3 to provide information about memory modules. The driver was ported from NetBSD, where it is available since release 5.0.
* [[Coreboot]] reads and uses SPD information to initialize all [[memory controller]]s in a computer with timing, size and other properties.
* [[Microsoft Windows|Windows]] systems use programs like [[HWiNFO]],<ref>{{Cite web|url=https://www.hwinfo.com/|title=HWiNFO - Professional System Information and Diagnostics|website=HWiNFO}}</ref> [[CPU-Z]] and [[Speccy]], which can read and display DRAM module information from SPD.

Chipset-independent reading and writing of SPD information is done by accessing the memory's EEPROM directly with eeprom programmer hardware and software.

A not so common use for old laptops is as generic SMBus readers, as the internal EEPROM on the module can be disabled once the BIOS has read it so the bus is essentially available for use.  The method used is to pull low the A0,A1 lines so the internal memory shuts down, allowing the external device to access the SMBus. Once this is done, a custom Linux build or DOS application can then access the external device. A common use is recovering data from LCD panel memory chips to retrofit a generic panel into a proprietary laptop.
On some chips it is also a good idea to separate write protect lines so that the onboard chips do not get wiped during reprogramming.
A related technique is rewriting the chip on webcams often included with many laptops as the bus speed is substantially higher and can even be modified so that 25x compatible chips can be read back for later cloning of the uEFI in the event of a chip failure.

This unfortunately only works on DDR3 and below, as DDR4 uses different security and can usually only be read. Its possible to use a tool like SPDTool or similar and replace the chip with one that has its WP line free so it can be altered in situ.
On some chipsets the message "Incompatible SMBus driver?" may be seen so read is also prevented.

=== RGB LED control ===
Some memory modules (especially on [[Gaming PC]]s)<ref>{{Cite web|title=VENGEANCE RGB PRO series DDR4 memory {{!}} Desktop Memory {{!}} CORSAIR|url=https://www.corsair.com/us/en/vengeance-rgb-pro-memory|access-date=2020-11-26|website=www.corsair.com}}</ref> support RGB LEDs that are controlled by proprietary SMBus commands. This allows LED color control without additional connectors and cables.  Kernel drivers from multiple manufacturers required to control the lights have been exploited to gain access ranging from full kernel memory access, to MSR and I/O port control numerous times in 2020 alone.<ref>{{cite tech report |title=Viper RGB Driver Local Privilege Escalation |id={{CVE|2019-18845}} |author=ActiveCyber |via=MITRE Corporation |url=https://www.activecyber.us/activelabs/viper-rgb-driver-local-privilege-escalation-cve-2019-18845}}</ref><ref>{{cite tech report |title=CORSAIR iCUE Driver Local Privilege Escalation (CVE-2020-8808)  |id={{CVE|2020-8808}} |author=ActiveCyber |via=MITRE Corporation |url=https://www.activecyber.us/activelabs/corsair-icue-driver-local-privilege-escalation-cve-2020-8808}}</ref><ref>{{cite tech report |title=ACTIVE-2020-003: Trident Z Lighting Control Driver Local Privilege Escalation  |id={{CVE|2020-12446}} |author=ActiveCyber |via=MITRE Corporation |url=https://www.activecyber.us/activelabs/active-2020-003-trident-z-lighting-control-driver-local-privilege-escalation}}</ref>

==On older equipment==
Some older equipment require the use of [[SIMM]]s with ''parallel'' presence detect (more commonly called simply ''presence detect'' or PD). Some of this equipment uses non-standard PD coding, [[IBM]] computers and [[Hewlett-Packard]] [[LaserJet]] and other printers in particular.

==See also==
* [[Transducer electronic data sheet]]

== References ==
{{Reflist}}



{{DEFAULTSORT:Serial Presence Detect}}
[[Category:Computer memory]]