View source for Scientific Research Institute of System Development

{{coord missing|Russia}}
'''Scientific Research Institute of System Analysis''' ([[abbreviation|abbrev.]] SRISA/NIISI RAS, {{langx|ru|НИИСИ РАН}}, {{langx|ru|Научно-исследовательский институт системных исследований Российской Академии Наук}}) - is [[Russia]]n state research and development institution in the field of complex applications, an initiative of the [[Russian Academy of Sciences]]. The mission of the institute is to resolve complex applied problems on the basis of fundamental and [[applied mathematics|applied]] [[mathematics]] in combination with the methods of practical [[computing]]. Founded by the Decree [[number|no.]] 1174 of the Presidium of the USSR Academy of Sciences on October 1, 1986.

== Research fields ==
Main lines of activities:

* research in the field of theoretical and applied problems on [[information security]],
* research in the field of automation of [[Computer programming|programming]],
* research in the field of creating computer models of the objects with complex [[geometry]] and [[topology]] for the [[Open standard|open]] [[scalable]] [[system]] of [[Parallel computing|parallel]] [[Data processing|information processing]],
* research in the field of applied [[Informatics (academic field)|informatics]].

== Development ==

=== Microprocessors ===
The SRISA has designed several MIPS compatible CPUs for general purpose calculations. These include:
* KOMDIV-32 ({{langx|ru|КОМДИВ-32}}) is a family of 32-bit [[microprocessor]]s, MIPS-I ISA
* KOMDIV-64 ({{langx|ru|КОМДИВ-64}}) is a family of 64-bit microprocessors, MIPS-IV ISA
* KOMDIV-64 ({{langx|ru|КОМДИВ-64}}) is a family of 64-bit microprocessors, MIPS-IV ISA
* "1890VM8Ya" is a 64-bit microprocessors, used in the CPU module on "TSP16/TSP21",<ref>[https://www.kpda.ru/upload/iblock/56c/serdin20190424.pdf {{lang|ru|«Модули и ЭВМ семейства «Багет».Текущее состояние и перспективы»}}] Russian General-purpose processor module based on the 1890VM8YA microprocessor in the "TSP16/TSP21"</ref> integrated computer system at Sukhoi Su-57 "fifth-generation jet fighter" and Su-35 "4++ generation jet fighter".<ref>[https://uacrussia.livejournal.com/61632.html {{lang|ru|Многоядерный Т-50: на новом российском истребителе ИМА БК заменила «Багет»}}] Russian Developers noted that "1890VM8Ya" microprocessor used in the CPU module on TSP16 Sukhoi Su-57 "fifth-generation jet fighter" and Su-35 "4++ generation jet fighter".</ref><ref>[http://niisi.tech/?page_id=127 Chip "1890VM8Ya" – FGU FSC NIISI] Russian Semiconductor Foundry Company Group provides contract manufacturing services according to technological standards from 90nm to 65 nm with a focus on the following technologies.</ref><ref>[https://www.niisi.ru/1890ВМ8Я.pdf {{lang|ru|1890ВМ8Я – фгу фнц нииси ран}}] Russian Dual-core 64-bit superscalar microprocessor with architecture KOMDIV64 with built-in system and peripheral controllers, second-level cache memory and additional functions for digital signal processing. Manufacturing technology of 65 nm CMOS. Serial production since 2016.</ref>

Dual-core 64-bit superscalar microprocessor with KOMDIV64 architecture with integrated system and peripheral controllers, second-level cache memory and additional functions for digital signal processing. Main characteristics:

·support for 32-bit instruction execution mode and addressing mode;

·the presence of a real arithmetic coprocessor that supports the formats for representing real numbers of single (32 bits) and double (64 bits) precision, as well as the format "pair of real numbers of single precision";

·the presence of a specialized vector coprocessor optimized for linear algebra and digital signal processing tasks of single and double precision with a separate register file of 64 128-bit registers, supporting single and double precision real and complex number formats;

·translation of 32-bit and 64-bit virtual addresses into 36-bit physical ones;

·64-address (128-page) virtual translation lookaside buffer (jTLB);

·separate virtual address translation buffer (micro TLB) caches for 4 addresses for instructions and data, transparent to the software model;

·separate set-associative first-level instruction caches of 32 KB (8 sections) and data of 16 KB (4 sections);

·2-level cache memory of 512 KB (4 sections);

·128-bit internal bus;

·7-stage superscalar pipeline with instruction prefetching and the ability to execute two instructions per cycle;

·reading up to four commands per clock cycle;

·dynamic branch prediction and speculative instruction execution.


·2 DDR2/DDR3 400/800 MHz dynamic memory controllers;

·2 RapidIO interface controllers;

·built-in RapidIO switch with 4 serial and one parallel channels;

·PCI controller 33/66 MHz;

·RS232 serial port controller (2 ports);

·2 Ethernet 1000/100/10 controllers;

·1 SATA 3.0 controller with 2 channels;

·1 USB 2.0 host controller with 2 channels;

·SPI controller (4 devices);

·I2C controller;

·16 one-time commands;

·interrupt controller;

·5 timers;

·EJTAG in-circuit debugging controller.

=== Operating systems ===
Since 1998 the SRISA department of [[Systems programming|System Programming]] has develop several successive [[Unix-like|UNIX-like]] [[real-time operating system]] (RTOS) that include:

* [[POSIX|POSIX 1003.1]]-compatible RTOS developed since January 1998; the network sockets, however, were borrowed from [[FreeBSD|Free BSD]]; it supported [[Internet protocol suite|TCP/IP]] protocol and [[X Window System|X Window]] suite; it runs on MIPS based CPUs mentioned above.<ref>{{Cite web|last=Godunov|first=Alexander N.|title=Отдел системного программирования|trans-title=SRISA Department of System Programming|url=https://www.niisi.ru/otd07.htm|access-date=2021-12-24|website=www.niisi.ru}}</ref>
* [[POSIX|POSIX 1003.1]] and [[ARINC 653|Arinc 653]]-compatible RTOS was first exhibited at SofTool-2008, -2009, and -2010 in Moscow.<ref>{{Cite web |date=2011-11-11 |title=Выставочный центр |url=http://www.expo.ras.ru/base/prod_data.asp?prod_id=3622 |access-date=2021-12-24 |website= |archive-url=https://web.archive.org/web/20111111102735/http://www.expo.ras.ru/base/prod_data.asp?prod_id=3622 |archive-date=11 November 2011 |url-status=dead}}</ref> It was joint project between [[ALT Linux|Alt Linux]] and SRISA teams.<ref>{{Cite web|title=Мир ПК №12 (декабрь 2010) by Sergey Pavlion - Issuu|url=https://issuu.com/sergeypavlion/docs/mirpk122010|access-date=2021-12-24|website=issuu.com|publisher=[[PC World]]|language=en}}</ref>{{Rp|page=70}}

== Notable people ==

* [[Israel Gelfand]], academician, Chief Science Officer of SRISA
* [[Vladimir Platonov]], academician, Chief Science Officer of SRISA
* [[Maksim Moshkow]], employee, creator of the largest and the oldest Russian electronic library "[[Lib.ru]]"

== External links ==
* [http://www.niisi.ru Official site of NIISI RAS]

== References ==
{{Reflist}}
{{authority control}}

[[Category:Institutes of the Russian Academy of Sciences]]
[[Category:Research institutes in the Soviet Union]]
[[Category:Computing in the Soviet Union]]
[[Category:Computer science institutes]]