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{{Short description|RISC instruction set architecture}}
{{Other uses}}
{{Use mdy dates|date=August 2016}}
{{Infobox CPU architecture
| image      = Sparc-logo.svg
| name       = SPARC
| designer   = [[Sun Microsystems]] (acquired by [[Oracle Corporation]])<ref name="cpushack"/><ref name="timeline"/>
| bits       = 64-bit (32 → 64)
| introduced = {{Start date and age|1986}} (production)<br/>{{Start date and age|1987}}<!-- If known, add |mm|dd --> (shipments)
| version    = V9 (1993) / OSA2017
| design     = [[Reduced instruction set computer|RISC]]
| type       = [[Load–store]]
| encoding   = Fixed
| branching  = [[Status register|Condition code]]
| endianness = [[Bi-endian|Bi]] (Big → Bi)
| page size  = 8 KB (4 KB → 8 KB)
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0, 4.0
| open       = Yes, and royalty free
| gpr        = 31 (G0 = 0; non-global registers use [[register window]]s)
| fpr        = 32 (usable as 32 single-precision, 32 double-precision, or 16 quad-precision)
}}
[[File:Sun UltraSPARCII.jpg|thumb|A [[Sun Microsystems|Sun]] [[UltraSPARC II]] microprocessor (1997)]]
'''SPARC''' ('''Scalable Processor ARChitecture''') is a [[reduced instruction set computer]] (RISC) [[instruction set architecture]] originally developed by [[Sun Microsystems]]. Its design was strongly influenced by the experimental [[Berkeley RISC]] system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s. After acquiring Sun, [[Oracle Corporation]] ended SPARC development in 2017.

==Description==
By the mid-1980s the computer industry's consensus was that [[RISC]] had a much better [[price/performance ratio]] than traditional [[complex instruction set computer|CISC]] architecture. [[Workstation]] vendor [[Sun Microsystems]] decided to move to RISC as fast as possible from the [[Motorola 68000 series]] of processors.<ref name="bellstreckerpdp11vaxalpha">{{Cite report |url=https://archive.computerhistory.org/resources/text/DEC/alpha/dec.alpha.bell_stecker.pdp-11_vax_and_alpha.1998.102630388.pdf |title=What Have We Learned from the PDP-11 - What We Have Learned from VAX and Alpha |last1=Bell |first1=Gordon |author-link1=Gordon Bell |last2=Strecker |first2=W.D. |access-date=2025-06-26}}</ref>

The first implementation of the original [[32-bit computing|32-bit]] architecture (SPARC V7) was used in Sun's [[Sun-4]] computer [[workstation]] and [[server (computing)|server]] systems, replacing their earlier [[Sun-3]] systems based on the Motorola 68000 series. SPARC V8 added a number of improvements that were part of the [[SuperSPARC]] series of processors released in 1992. SPARC V9, released in 1993, introduced a [[64-bit computing|64-bit]] architecture and was first released in Sun's [[UltraSPARC]] processors in 1995. Later, SPARC processors were used in [[symmetric multiprocessing]] (SMP) and [[non-uniform memory access]] ([[CC-NUMA]]) servers produced by Sun, [[Solbourne Computer|Solbourne]], and [[Fujitsu]], among others.

The design was turned over to the SPARC International trade group in 1989, and since then its architecture has been developed by its members. SPARC International is also responsible for licensing and promoting the SPARC architecture, managing SPARC trademarks (including SPARC, which it owns), and providing [[conformance testing]]. SPARC International was intended to grow the SPARC architecture to create a larger ecosystem; SPARC has been licensed to several manufacturers, including [[Atmel]], [[Bipolar Integrated Technology]], [[Cypress Semiconductor]], [[Fujitsu]], [[Panasonic|Matsushita]] and [[Texas Instruments]]. Due to SPARC International, SPARC is fully open, non-proprietary and royalty-free.

As of 2024, the latest commercial high-end SPARC processors are [[Fujitsu]]'s [[SPARC64 V#SPARC64 XII|SPARC64 XII]] (introduced in September 2017 for its SPARC M12 server) and [[Oracle Corporation|Oracle]]'s [[SPARC M8]] introduced in September 2017 for its high-end servers.

On September 1, 2017, after a round of layoffs that started in Oracle Labs in November 2016, Oracle terminated SPARC design after completing the M8. Much of the processor core development group in Austin, Texas, was dismissed, as were the teams in Santa Clara, California, and Burlington, Massachusetts.<ref>{{cite news |last=Vaughan-Nichols |first=Steven J. |date=September 5, 2017 |url=https://www.zdnet.com/article/sun-set-oracle-closes-down-last-sun-product-lines/ |title=Sun set: Oracle closes down last Sun product lines |website=[[ZDNet]] |access-date=September 11, 2017 |url-status=live |archive-date=September 10, 2017 |archive-url=https://web.archive.org/web/20170910094119/http://www.zdnet.com/article/sun-set-oracle-closes-down-last-sun-product-lines/}}</ref><ref>{{cite news |last=Nichols |first=Shaun |date=August 31, 2017 |url=https://www.theregister.co.uk/2017/08/31/oracle_stops_prolonging_inevitable_layoffs/ |title=Oracle finally decides to stop prolonging the inevitable, begins hardware layoffs |website=[[The Register]] |access-date=September 11, 2017 |url-status=live |archive-date=September 12, 2017 |archive-url=https://web.archive.org/web/20170912055124/https://www.theregister.co.uk/2017/08/31/oracle_stops_prolonging_inevitable_layoffs/}}</ref>

Fujitsu will also discontinue their SPARC production (has already shifted to producing their own [[ARM architecture family|ARM]]-based CPUs), after one "enhanced" versions of Fujitsu's older SPARC M12 server in 2020–22 (formerly planned for 2021),<!-- "As part of this effort, Fujitsu works on a cloud shift for both Mainframe and UNIX."--> end-of-sale in 2029, of UNIX servers and a year later for their [[mainframe computer|mainframe]] and end-of-support in 2034 "to promote customer modernization".<ref>{{Cite web |title=Roadmap: Fujitsu Global |url=https://www.fujitsu.com/global/products/computing/servers/unix/sparc/key-reports/roadmap/ |access-date=2022-02-15 |website=www.fujitsu.com}}</ref>

==Features==
The SPARC architecture was heavily influenced by the earlier RISC designs, including the [[Berkeley RISC]] I and II from the [[University of California, Berkeley]] and the [[IBM 801]]. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per [[clock signal|clock cycle]]. This made them similar to the [[MIPS architecture]] in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the [[branch delay slot]].

The SPARC processor usually contains as many as 160 [[processor register|general-purpose registers]]. According to the "Oracle SPARC Architecture 2015" specification an "implementation may contain from 72 to 640 general-purpose 64-bit" registers.<ref name="SPARC 2015">{{cite web |url=https://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-architecture-2015-2868130.pdf |title=Oracle SPARC Architecture 2015: One Architecture ... Multiple Innovative Implementations |version=Draft D1.0.0 |date=January 12, 2016 |quote=<!--p.16-->IMPL. DEP. #2-V8: An Oracle SPARC Architecture implementation may contain from 72 to 640 general-purpose 64-bit R registers. This corresponds to a grouping of the registers into MAXPGL + 1 sets of global R registers plus a circular stack of N_REG_WINDOWS sets of 16 registers each, known as register windows. The number of register windows present (N_REG_WINDOWS) is implementation dependent, within the range of 3 to 32 (inclusive).<!--"Variants of load/store instructions, the load/store alternate instructions, can specify an arbitrary 8-bit address space identifier for the load/store data access."--><!--Possibly a "typo" for thirty-two 64-bit registers?: "The floating-point register set consists of sixty-four 32-bit registers, which may be accessed as follows:"--> |access-date=June 13, 2016 |archive-date=April 24, 2016 |archive-url=https://web.archive.org/web/20160424051826/http://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-architecture-2015-2868130.pdf |url-status=live }}</ref> At any point, only 32 of them are immediately visible to software&nbsp;— 8 are a set of global registers (one of which, '''g0''', is hard-wired to zero, so only seven of them are usable as registers) and the other 24 are from the [[stack (abstract data type)|stack]] of registers. These 24 registers form what is called a [[register window]], and at function call/return, this window is moved up and down the register stack. Each window has eight local registers and shares eight registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for retaining local values across function calls.

The "scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (non-privileged) instruction set.  One of the architectural parameters that can scale is the number of implemented register windows; the specification allows from three to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum [[call stack]] efficiency, or to implement only three to reduce cost and complexity of the design, or to implement some number between them. Other architectures that include similar [[register file]] features include [[Intel i960]], [[IA-64]], and [[AMD 29000]].

The architecture has gone through several revisions. It gained hardware multiply and divide functionality in version 8.{{R|gcc-doc|osnews-gcc}} [[64-bit computing|64-bit]] (addressing and data) were added to the version 9 SPARC specification published in 1994.<ref name="sparc-v9-whitepaper" />

In SPARC version 8, the [[floating-point arithmetic|floating-point]] register file has 16 [[double-precision floating-point format|double-precision]] registers. Each of them can be used as two [[single-precision floating-point format|single-precision]] registers, providing a total of 32 single-precision registers. An odd–even number pair of double-precision registers can be used as a [[quadruple-precision floating-point format|quad-precision]] register, thus allowing 8 quad-precision registers. SPARC Version 9 added 16 more double-precision registers (which can also be accessed as 8 quad-precision registers), but these additional registers can not be accessed as single-precision registers. No SPARC CPU implements quad-precision operations in hardware as of 2024.<ref>{{Cite book
| title = Numerical Computation Guide – Sun Studio 10
| chapter = SPARC Behavior and Implementation
| year = 2004
| publisher = Sun Microsystems, Inc
| chapter-url = https://download.oracle.com/docs/cd/E19059-01/stud.10/819-0499/ncg_sparc.html
| access-date = September 24, 2011
| quote = There are four situations, however, when the hardware will not successfully complete a floating-point instruction: ...&nbsp;The instruction is not implemented by the hardware (such as&nbsp;... quad-precision instructions on any SPARC FPU).
| archive-date = January 25, 2022
| archive-url = https://web.archive.org/web/20220125121541/https://docs.oracle.com/cd/E19059-01/stud.10/819-0499/ncg_sparc.html
| url-status = live
}}</ref>

[[Tagged architecture|Tagged]] add and subtract instructions perform adds and subtracts on values checking that the bottom two bits of both operands are 0 and reporting overflow if they are not.  This can be useful in the implementation of the [[run-time system|run time]] for [[ML (programming language)|ML]], [[Lisp (programming language)|Lisp]], and similar languages that might use a tagged integer format.

The [[endianness]] of the [[32-bit computing|32-bit]] SPARC V8 architecture is purely big-endian. The 64-bit SPARC V9 architecture uses big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at the application instruction ([[load–store unit|load–store]]) level or at the [[paging|memory page]] level (via an MMU setting).  The latter is often used for accessing data from inherently little-endian devices, such as those on PCI buses.

==History==

v7 &rarr; v8 &rarr; v9 (64-bit) &rarr; JPS1 &rarr; JPS2 (multicore) &rarr; UA2005 ([[sun4v]]) &rarr; UA2007 &rarr; OSA2011 &rarr; OSA2015 &rarr; OSA2017

There have been three major revisions of the architecture. The first published version was the 32-bit ''SPARC version 7'' (V7) in 1986. ''SPARC version 8'' (V8), an enhanced SPARC architecture definition, was released in 1990.  The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit "extended-precision" floating-point arithmetic to 128-bit "[[quadruple-precision floating-point format|quad-precision]]" arithmetic.  SPARC V8 served as the basis for IEEE Standard 1754-1994, an [[IEEE]] standard for a 32-bit microprocessor architecture.

''SPARC version 9'' (V9), the 64-bit SPARC architecture, was released by SPARC International in 1993.  It was developed by the SPARC Architecture Committee consisting of [[Amdahl Corporation]], [[Fujitsu]], [[International Computers Limited|ICL]], [[LSI Logic]], [[Panasonic|Matsushita]], [[Philips]], [[Ross Technology]], [[Sun Microsystems]], and [[Texas Instruments]]. Newer specifications always remain compliant with the full SPARC V9 Level 1 specification.

In 2002, the SPARC ''Joint Programming Specification 1'' (JPS1) was released by Fujitsu and Sun, describing processor functions which were identically implemented in the CPUs of both companies ("Commonality"). The first CPUs conforming to JPS1 were the UltraSPARC III by Sun and the SPARC64 V by Fujitsu. Functionalities which are not covered by JPS1 are documented for each processor in "Implementation Supplements".

At the end of 2003, ''Joint Programming Specification 2'' (JPS2) was released to support multicore CPUs. The first CPUs conforming to JPS2 were the UltraSPARC IV by Sun and the SPARC64 VI by Fujitsu.

In early 2006, Sun released an extended architecture specification, ''UltraSPARC Architecture 2005'' (UA2005). This includes not only the non-privileged and most of the privileged portions of SPARC V9, but also all the architectural extensions developed through the processor generations of UltraSPARC III, IV, and IV+, as well as ''Chip Multithreading Technology'' (''CMT'') extensions starting with the [[UltraSPARC T1]] implementation:

* the [[Visual Instruction Set|VIS]] 1 and VIS 2 instruction set extensions and the associated GSR register
* multiple levels of global registers, controlled by the GL register
* Sun's 64-bit MMU architecture
* privileged instructions ALLCLEAN, OTHERW, NORMALW, and INVALW
* access to the VER register is now hyperprivileged
* the SIR instruction is now hyperprivileged

In 2007, Sun released an updated specification, ''UltraSPARC Architecture 2007'' (UA2007), to which the [[UltraSPARC T2]] implementation complied.

In December 2007, Sun also made the [[UltraSPARC T2]] processor's RTL available via the [[OpenSPARC]] project.<ref>{{cite web |title=Sun Accelerates Growth of UltraSPARC CMT Eco System |url=http://www.sun.com/pr/2007-12/sunflash.20071211.1.xml |publisher=Sun Microsystems |archive-url=https://web.archive.org/web/20080126174236/http://www.sun.com/aboutsun/pr/2007-12/sunflash.20071211.1.xml |archive-date=January 26, 2008 |url-status=dead}}</ref> It was also released under the GNU General public license v2.<ref>{{cite web|archiveurl=https://web.archive.org/web/20121017041211/http://www.oracle.com/technetwork/systems/opensparc/opensparc-faq-1444660.html|url=http://www.oracle.com/technetwork/systems/opensparc/opensparc-faq-1444660.html|title=OpenSPARC Frequently Asked Questions|publisher=Oracle|archivedate=2012-10-17|access-date=2021-03-20}}</ref> OpenSPARC T2 is 8 cores, 16 pipelines with 64 threads.

In August 2012, Oracle Corporation made available a new specification, ''Oracle SPARC Architecture 2011'' (OSA2011), which besides the overall update of the reference, adds the VIS 3 instruction set extensions and [[Logical Domains|hyperprivileged mode]] to the 2007 specification.<ref name="sparc-arch-2011" />

In October 2015, Oracle released SPARC M7, the first processor based on the new ''Oracle SPARC Architecture 2015'' (OSA2015) specification.<ref name="SPARC 2015" /><ref>{{cite web
| url = https://www.oracle.com/us/corporate/features/sparc-m7/
| title = SPARC M7 Innovation
| access-date = October 13, 2015
| last=Soat |first=John
| work = Oracle web site
| publisher = [[Oracle Corporation]]
| archive-date = September 5, 2015
| archive-url = https://web.archive.org/web/20150905065312/http://www.oracle.com/us/corporate/features/sparc-m7/
| url-status = live
}}</ref>  This revision includes VIS 4 instruction set extensions and hardware-assisted encryption and silicon secured memory (SSM).<ref>{{cite web|url=https://www.oracle.com/servers/sparc/software-in-silicon.html|title=Software in Silicon Cloud - Oracle|website=www.oracle.com|access-date=January 21, 2019|archive-date=January 21, 2019|archive-url=https://web.archive.org/web/20190121185630/https://www.oracle.com/servers/sparc/software-in-silicon.html|url-status=live}}</ref>

In September 2017, Oracle released SPARC M8, the first processor based on the new ''Oracle SPARC Architecture 2017'' (OSA2017) specification.

SPARC architecture has provided continuous application binary compatibility from the first SPARC V7 implementation in 1987 through the Sun UltraSPARC Architecture implementations.

Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for [[Standard Performance Evaluation Corporation|SPEC]] CPU95 and CPU2000 benchmarks. The 296&nbsp;MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark.

==Architecture==
SPARC is a [[load–store architecture]] (also known as a ''register–register architecture''); except for the [[load/store instructions]] used to access [[computer memory|memory]], all instructions operate on the registers, in accordance with the RISC design principles.

A SPARC processor includes an integer unit (IU) that performs integer load, store, and arithmetic operations.<ref name="sparc-v8-whitepaper" />{{rp|page=9}}<ref name="sparc-v9-whitepaper" />{{rp|pages=15{{hyp}}16}}  It may include a floating-point unit (FPU) that performs floating-point operations<ref name="sparc-v8-whitepaper" />{{rp|page=9}}<ref name="sparc-v9-whitepaper" />{{rp|pages=15{{hyp}}16}} and, for SPARC V8, may include a co-processor (CP) that performs co-processor-specific operations; the architecture does not specify what functions a co-processor would perform, other than load and store operations.<ref name="sparc-v8-whitepaper" />{{rp|page=9}}

===Registers===
The SPARC architecture has an overlapping register window scheme. At any instant, 32 general-purpose registers are visible. A Current Window Pointer (''CWP'') variable in the hardware points to the current set. The total size of the register file is not part of the architecture, allowing more registers to be added as the technology improves, up to a maximum of 32 windows in SPARC V7 and V8 as ''CWP'' is 5 bits and is part of the ''PSR'' register.

In SPARC V7 and V8 ''CWP'' will usually be decremented by the SAVE instruction (used by the SAVE instruction during the procedure call to open a new stack frame and switch the register window), or incremented by the RESTORE instruction (switching back to the call before returning from the procedure). Trap events ([[interrupt]]s, exceptions or TRAP instructions) and RETT instructions (returning from traps) also change the ''CWP''. For SPARC V9, CWP register is decremented during a RESTORE instruction, and incremented during a SAVE instruction. This is the opposite of PSR.CWP's behavior in SPARC V8. This change has no effect on nonprivileged instructions.

{| class="wikitable"
|+ Window Addressing
|-
! Register group !! Mnemonic !! Register address || Availability
|-
| global || G0...G7 || R[{{0}}0]...R[{{0}}7] || always the same ones, G0 being zero always
|-
| out || O0...O7 || R[{{0}}8]...R[15] || to be handed over to, and returned from, the called subroutine, as its "in"
|-
| local || L0...L7 || R[16]...R[23] || truly local to the current subroutine
|-
| in || I0...I7 || R[24]...R[31] || handed over from the caller, and returned to the caller, as its "out"
|}

SPARC registers are shown in the figure above.

There is also a non-windowed Y register, used by the multiply-step, integer multiply, and integer divide instructions.<ref name="sparc-v8-whitepaper" />{{rp|page=32}}

A SPARC V8 processor with an FPU includes 32 32-bit floating-point registers, each of which can hold one single-precision [[IEEE 754]] floating-point number.  An even–odd pair of floating-point registers can hold one double-precision IEEE 754 floating-point number, and a quad-aligned group of four floating-point registers can hold one quad-precision IEEE 754 floating-point number.<ref name="sparc-v8-whitepaper" />{{rp|page=10}}

A SPARC V9 processor with an FPU includes:<ref name="sparc-v9-whitepaper" />{{rp|pages=36{{hyp}}40}}

* 32 32-bit floating-point registers, each of which can hold one single-precision IEEE 754 floating-point number;
* 32 64-bit floating-point registers, each of which can hold one double-precision IEEE 754 floating-point number;
* 16 128-bit floating-point registers, each of which can hold one quad-precision IEEE 754 floating-point number.

The registers are organized as a set of 64 32-bit registers, with the first 32 being used as the 32-bit floating-point registers, even–odd pairs of all 64 registers being used as the 64-bit floating-point registers, and quad-aligned groups of four floating-point registers being used as the 128-bit floating-point registers.

Floating-point registers are not windowed; they are all global registers.<ref name="sparc-v9-whitepaper" />{{rp|pages=36{{hyp}}40}}

===Instruction formats===
All SPARC instructions occupy a full 32-bit word and start on a word boundary. Four formats are used, distinguished by the first two bits. All arithmetic and logical instructions have 2 source operands and 1 destination operand.<ref name=ncsu>{{cite web |url=https://arcb.csc.ncsu.edu/~mueller/codeopt/codeopt00/notes/sparc.html |title= SPARC Fundamental Instructions}}</ref> RD is the "destination register", where the output of the operation is deposited. The majority of SPARC instructions have at least this register, so it is placed near the "front" of the instruction format. RS1 and RS2 are the "source registers", which may or may not be present, or replaced by a constant.

{| class="wikitable" style="text-align:center;"
|+ SPARC instruction formats
|-
! rowspan=2  | Type
! colspan=32 | Bit
|-
! 31 !! 30 !! 29 !! 28 !! 27 !! 26 !! 25 !! 24 !! 23 !! 22 !! 21 !! 20 !! 19 !! 18 !! 17 !! 16 !! 15 !! 14 !! 13 !! 12 !! 11 !! 10 !! 9 !! 8 !! 7 !! 6 !! 5 !! 4 !! 3  !! 2 !! 1 !! 0
|-
| SETHI format ||colspan="2"|00||colspan="5"| RD || colspan="3"|100 ||colspan="22"|Immediate constant 22 bits
|-
| I Branch format ||colspan="2"|00||A||colspan="4"|icc||colspan="3"|010||colspan="22"|Displacement constant 22 bits
|-
| F Branch format ||colspan="2"|00||A||colspan="4"|fcc||colspan="3"|110 ||colspan="22"|Displacement constant 22 bits
|-
| C Branch format ||colspan="2"|00||A||colspan="4"|ccc||colspan="3"|111 ||colspan="22"|Displacement constant 22 bits
|-
| CALL disp ||colspan="2"|01||colspan="30"|PC-relative displacement
|-
| Arithmetic register ||colspan="2"|10||colspan="5"| RD || colspan="6"|opcode ||colspan="5"| RS1 || 0 || colspan="8"|0 ||colspan="5"| RS2
|-
| Arithmetic immediate ||colspan="2"|10||colspan="5"| RD || colspan="6"|opcode ||colspan="5"| RS1 || 1 || colspan="13"| Immediate constant 13 bits
|-
| FPU operation ||colspan="2"|10||colspan="5"| FD || colspan="6"|110100/110101 ||colspan="5"| FS1 || colspan="9"| opf ||colspan="5"| FS2
|-
| CP operation ||colspan="2"|10||colspan="5"| RD || colspan="6"|110110/110111 ||colspan="5"| RS1 || colspan="9"| opc ||colspan="5"| RS2
|-
| JMPL register ||colspan="2"|10||colspan="5"| RD || colspan="6"|111000 ||colspan="5"| RS1 || 0 || colspan="8"|0 ||colspan="5"| RS2
|-
| JMPL immediate ||colspan="2"|10||colspan="5"| RD || colspan="6"|111000 ||colspan="5"| RS1 || 1 || colspan="13"| Immediate constant 13 bits
|-
| LD/ST register ||colspan="2"|11||colspan="5"| RD || colspan="6"|opcode ||colspan="5"| RS1 || 0 || colspan="8"|0 ||colspan="5"| RS2
|-
| LD/ST immediate ||colspan="2"|11||colspan="5"| RD || colspan="6"|opcode ||colspan="5"| RS1 || 1 || colspan="13"| Immediate constant 13 bits
|}

===Instructions===
====Loads and stores====
Load and store instructions have a three-operand format, in that they have two operands representing values for the address and one operand for the register to read or write to. The address is created by adding the two address operands to produce an address. The second address operand may be a constant or a register. Loads take the value at the address and place it in the register specified by the third operand, whereas stores take the value in the register specified by the first operand and place it at the address. To make this more obvious, the [[assembler language]] indicates address operands using square brackets with a plus sign separating the operands, instead of using a comma-separated list. Examples:<ref name=ncsu/>

 ld [%L1+%L2],%L3  !load the 32-bit value at address %L1+%L2 and put the value into %L3
 ld [%L1+8],%L2    !load the value at %L1+8 into %L2
 ld [%L1],%L2      !as above, but no offset, which is the same as +%G0
 st %L1,[%I2]      !store the value in %L1 into the location stored in %I2
 st %G0,[%I1+8]    !clear the memory at %I1+8

Due to the widespread use of non-32-bit data, such as 16-bit or 8-bit integral data or 8-bit bytes in strings, there are instructions that load and store 16-bit half-words and 8-bit bytes, as well as instructions that load 32-bit words. During a load, those instructions will read only the byte or half-word at the indicated location and then either fill the rest of the target register with zeros (unsigned load) or with the value of the uppermost bit of the byte or half-word (signed load). During a store, those instructions discard the upper bits in the register and store only the lower bits. There are also instructions for loading double-precision values used for [[floating-point arithmetic]], reading or writing eight bytes from the indicated register and the "next" one, so if the destination of a load is L1, L1 and L2 will be set. The complete list of load and store instructions for the general-purpose registers in 32-bit SPARC is {{code|LD}}, {{code|ST}}, {{code|LDUB}} (unsigned byte), {{code|LDSB}} (signed byte), {{code|LDUH}} (unsigned half-word), {{code|LDSH}} (signed half-word), {{code|LDD}} (load double), {{code|STB}} (store byte), {{code|STH}} (store half-word), {{code|STD}} (store double).<ref name=ncsu/>

In SPARC V9, registers are 64-bit, and the {{code|LD}} instruction, renamed {{code|LDUW}}, clears the upper 32 bits in the register and loads the 32-bit value into the lower 32 bits, and the {{code|ST}} instruction, renamed {{code|STW}}, discards the upper 32 bits of the register and stores only the lower 32 bits.  The new {{code|LDSW}} instruction sets the upper bits in the register to the value of the uppermost bit of the word and loads the 32-bit value into the lower bits. The new {{code|LDX}} instruction loads a 64-bit value into the register, and the {{code|STX}} instruction stores all 64 bits of the register.

The {{code|LDF}}, {{code|LDDF}}, and {{code|LDQF}} instructions load a single-precision, double-precision, or quad-precision value from memory into a floating-point register; the {{code|STF}}, {{code|STDF}}, and {{code|STQF}} instructions store a single-precision, double-precision, or quad-precision floating-point register into memory.

The [[memory barrier]] instruction, MEMBAR, serves two interrelated purposes: it articulates order constraints among memory references and facilitates explicit control over the completion of memory references. For example, all effects of the stores that appear prior to the MEMBAR instruction must be made visible to all processors before any loads following the MEMBAR can be executed.<ref>{{Cite web |url=https://www.fujitsu.com/hk/imagesgig5/sparc64ixfx-extensions.pdf#page=103 |title=SPARC64 IXfx Extensions Fujitsu Limited Ver 12, 2 Dec. 2013 |pages=103–104 |accessdate=2023-12-17}}</ref>

====ALU operations====
Arithmetic and logical instructions also use a three-operand format, with the first two being the operands and the last being the location to store the result. The middle operand can be a register or a 13-bit signed integer constant; the other operands are registers. Any of the register operands may point to G0; pointing the result to G0 discards the results, which can be used for tests. Examples include:<ref name=ncsu/>

 add %L1,%L2,%L3   !add the values in %L1 and %L2 and put the result in %L3
 add %L1,1,%L1     !increment %L1
 add %G0,%G0,%L4   !clear any value in %L4

The list of mathematical instructions is {{code|ADD}}, {{code|SUB}}, {{code|AND}}, {{code|OR}}, {{code|XOR}}, and negated versions {{code|ANDN}}, {{code|ORN}}, and {{code|XNOR}}. One quirk of the SPARC design is that most arithmetic instructions come in pairs, with one version setting the NZVC condition code bits in the [[status register]], and the other not setting them, with the default being ''not'' to set the codes. This is so that the compiler has a way to move instructions around when trying to fill delay slots. If one wants the condition codes to be set, this is indicated by adding {{code|cc}} to the instruction:<ref name=ncsu/>

 subcc %L1,10,%G0  !compare %L1 to 10 and ignore the result, but set the flags

add and sub also have another modifier, X, which indicates whether the operation should set the carry bit:

 addx %L1,100,%L1  !add 100 to the value in %L1 and track carry

SPARC V7 does not have multiplication or division instructions, but it does have {{code|MULSCC}}, which does one step of a multiplication testing one bit and conditionally adding the multiplicand to the product. This was because {{code|MULSCC}} can complete over one clock cycle in keeping with the RISC philosophy.  SPARC V8 added {{code|UMUL}} (unsigned multiply), {{code|SMUL}} (signed multiply), {{code|UDIV}} (unsigned divide), and {{code|SDIV}} (signed divide) instructions, with both versions that do not update the condition codes and versions that do.  {{code|MULSCC}} and the multiply instructions use the Y register to hold the upper 32 bits of the product; the divide instructions use it to hold the upper 32 bits of the dividend.  The {{code|RDY}} instruction reads the value of the Y register into a general-purpose register; the {{code|WRY}} instruction writes the value of a general-purpose register to the Y register.<ref name="sparc-v8-whitepaper" />{{rp|page=32}}  SPARC V9 added {{code|MULX}}, which multiplies two 64-bit values and produces a 64-bit result, {{code|SDIVX}}, which divides a 64-bit signed dividend by a 64-bit signed divisor and produces a 64-bit signed quotient, and {{code|UDIVX}}, which divides a 64-bit unsigned dividend by a 64-bit unsigned divisor and produces a 64-bit signed quotient; none of those instructions use the Y register.<ref name="sparc-v9-whitepaper" />{{rp|page=199}}

====Branching====
Conditional branches test condition codes in a [[status register]], as seen in many instruction sets such the [[IBM System/360 architecture]] and successors and the [[x86]] architecture. This means that a test and branch is normally performed with two instructions; the first is an ALU instruction that sets the condition codes, followed by a branch instruction that examines one of those flags. The SPARC does not have specialized test instructions; tests are performed using normal ALU instructions with the destination set to %G0. For instance, to test if a register holds the value 10 and then branch to code that handles it, one would:

 subcc %L1,10,%G0 !subtract 10 from %L1, setting the zero flag if %L1 is 10
 be WASEQUAL      !if the zero flag is set, branch to the address marked WASEQUAL

In a conditional branch instruction, the '''icc''' or '''fcc''' field specifies the condition being tested. The 22-bit displacement field is the address, relative to the current PC, of the target, in words, so that conditional branches can go forward or backward up to 8 megabytes. The ''ANNUL'' (A) bit is used to get rid of some delay slots. If it is 0 in a conditional branch, the delay slot is executed as usual. If it is 1, the delay slot is only executed if the branch is taken. If it is not taken, the instruction following the conditional branch is skipped.

There are a wide variety of conditional branches: {{code|BA}} (branch always, essentially a jmp), {{code|BN}} (branch never), {{code|BE}} (equals), {{code|BNE}} (not equals), {{code|BL}} (less than), {{code|BLE}} (less or equal), {{code|BLEU}} (less or equal, unsigned), {{code|BG}} (greater), {{code|BGE}} (greater or equal), {{code|BGU}} (greater unsigned), {{code|BPOS}} (positive), {{code|BNEG}} (negative), {{code|BCC}} (carry clear), {{code|BCS}} (carry set), {{code|BVC}} (overflow clear), {{code|BVS}} (overflow set).<ref name="sparc-v8-whitepaper" />{{rp|119{{hyp}}120}}

The FPU and CP have sets of condition codes separate from the integer condition codes and from each other; two additional sets of branch instructions were defined to test those condition codes. Adding an F to the front of the branch instruction in the list above performs the test against the FPU's condition codes,<ref name="sparc-v8-whitepaper" />{{rp|121{{hyp}}122}} while, in SPARC V8, adding a C tests the flags in the otherwise undefined CP.<ref name="sparc-v8-whitepaper" />{{rp|123{{hyp}}124}}

The {{code|CALL}} (jump to subroutine) instruction uses a 30-bit [[program counter]]-relative ''word'' offset. As the target address is specifying the start of a word, not a byte, 30-bits is all that is needed to reach any address in the 4 gigabyte address space.<ref name=ncsu/> The CALL instruction deposits the return address in register R15, also known as output register O7.

The {{code|JMPL}} (jump and link) instruction is a three-operand instruction, with two operands representing values for the target address and one operand for a register in which to deposit the return address. The address is created by adding the two address operands to produce a 32-bit address. The second address operand may be a constant or a register.

====Large constants====
As the instruction opcode takes up some bits of the 32-bit instruction word, there is no way to load a 32-bit constant using a single instruction. This is significant because addresses are manipulated through registers and they are 32-bits. To ease this, the special-purpose {{code|SETHI}} instruction copies its 22-bit immediate operand into the high-order 22 bits of any specified register, and sets each of the low-order 10 bits to 0. In general use, SETHI is followed by an or instruction with only the lower 10 bits of the value set. To ease this, the assembler includes the {{code|%hi(X)}} and {{code|%lo(X)}} macros. For example:<ref name=ncsu/>

 sethi %hi(0x89ABCDEF),%L1       !sets the upper 22 bits of L1
 or    %L1,%lo(0x89ABCDEF),%L1   !sets the lower 10 bits of L1 by ORing

The hi and lo macros are performed at assembly time, not runtime, so it has no performance hit yet makes it clearer that L1 is set to a single value, not two unrelated ones. To make this even easier, the assembler also includes a "synthetic instruction", {{code|set}}, that performs these two operations in a single line:

 set   0x89ABCDEF,% L1

This outputs the two instructions above if the value is larger than 13 bits, otherwise it will emit a single {{code|ld}} with the value.<ref name=ncsu/>

===Synthetic instructions===
As noted earlier, the SPARC assembler uses "synthetic instructions" to ease common coding tasks. Additional examples include (among others):<ref name=ncsu/>

{| class="wikitable"
|+ SPARC synthetic instructions
|-
! mnemonic
! actual output
! purpose
|-
| {{code|nop|asm}} || {{code|sethi 0,%g0|asm}} || do nothing
|-
| {{code|clr %reg|asm}} || {{code|or %g0,%g0,%reg|asm}} || set a register to zero
|-
| {{code|clr [address]|asm}} || {{code|st %g0,[address]|asm}} || set a memory address to zero
|-
| {{code|clrh [address]|asm}} || {{code|sth %g0,[address]|asm}} || set the half-word at memory address to zero
|-
| {{code|clrb [address]|asm}} || {{code|stb %g0,[address]|asm}} || set the byte at memory address to zero
|-
| {{code|cmp %reg1,%reg2|asm}} || {{code|subcc %reg1,%reg2,%g0|asm}} || compare two registers, set codes, discard results
|-
| {{code|cmp %reg,const|asm}} || {{code|subcc %reg,const,%g0|asm}} || compare register with constant 
|-
| {{code|mov %reg1,%reg2|asm}} || {{code|or %g0,%reg1,%reg2|asm}} || copy value from one register to another 
|-
| {{code|mov const,%reg|asm}} || {{code|or %g0,const,%reg|asm}} || copy constant value into a register
|-
| {{code|inc %reg|asm}} || {{code|add %reg,1,%reg|asm}} || increment a register 
|-
| {{code|inccc %reg|asm}} || {{code|addcc %reg,1,%reg|asm}} || increment a register, set conditions
|-
| {{code|dec %reg|asm}} || {{code|sub %reg,1,%reg|asm}} || decrement a register 
|-
| {{code|deccc %reg|asm}} || {{code|subcc %reg,1,%reg|asm}} || decrement a register, set conditions
|-
| {{code|not %reg|asm}} || {{code|xnor %reg,%g0,%reg|asm}} || flip the bits in a register
|-
| {{code|neg %reg|asm}} || {{code|sub %g0,%reg,%reg|asm}} || two's complement a register
|-
| {{code|tst %reg|asm}} || {{code|orcc %reg,%g0,%g0|asm}} || test whether the value in a register is > 0, 0, or < 0
|}

==SPARC architecture licensees==
[[Intel]] was the [[80386]]'s only producer, which made it very expensive and caused the industry to be wary of [[sole source]]d CPUs. When Sun announced SPARC in 1987, the company stated that it would be available from multiple sources. Fujitsu was the first SPARC vendor, and Cypress Semiconductor was the second licensee; {{as of|1989|02|lc=y}} their SPARC CPUs were available, as was Texas Instruments's FPU.<ref name="byte198902">{{Cite magazine |last1=Marshall |first1=Trevor |last2=Tazelaar |first2=Jane Morrill |date=February 1989 |title=Worth the RISC |url=https://archive.org/details/eu_BYTE-1989-02_OCR/page/n299/mode/2up?view=theater |access-date=2024-10-08 |magazine=[[Byte (magazine)|BYTE]] |publisher=[[McGraw-Hill]] |pages=245–249}}</ref> The following organizations have licensed the SPARC architecture<!--Not SPARC implementations-->:

{{div col}}
* [[Afara Websystems]]
* [[Bipolar Integrated Technology]] (BIT){{r|byte198902}}
* [[Cypress Semiconductor]]{{r|byte198902}}
* [[European Space Research and Technology Center]] (ESTEC)
* [[Fujitsu]]{{r|byte198902}} (and its Fujitsu Microelectronics subsidiary)
* [[Gaisler Research]]
* [[HAL Computer Systems]]
* [[Hyundai Group|Hyundai]]
* [[LSI Logic]]{{r|byte198902}}
* [[Harris Corporation|Matra Harris Semiconductors]] (MHS)
* [[Panasonic|Matsushita Electrical Industrial Co.]]
* [[Meiko Scientific]]
* [[Metaflow Technologies]]
* [[Philips Electronics]]
* Prisma
* [[Ross Technology]]
* [[Solbourne Computer]]
* Systems & Processes Engineering Corporation (SPEC)
* TEMIC
* [[Texas Instruments]]{{r|byte198902}}
* [[Weitek]]
{{div col end}}

==Implementations==
{{sticky header}}
{{mw-datatable}}
{{sort-under}}
{| class="wikitable sortable mw-datatable sort-under mw-collapsible sticky-header" style="font-size: 85%;"
|- style="vertical-align: top;"
!                            Name (codename)
!                            Model
! abbr="Frequency"         | Frequency (MHz)
! abbr="Architecture"      | Arch. version
!                            Year
! abbr="Threads"           | Total threads<ref group="note" name=threads>Threads per core × number of cores</ref>
! abbr="Process"           | Process (nm)
! abbr="Transistors"       | Transistors (millions)
! abbr="Size"              | Die size (mm<sup>2</sup>)
!                            IO pins
! abbr="Power"             | Power (W)
! abbr="Voltage"           | Voltage (V)
! abbr="Data cache"        | L1 Dcache (KB)
! abbr="Instruction cache" | L1 Icache (KB)
! abbr="L2 Cache"          | L2 cache (KB)
! abbr="L3 Cache"          | L3 cache (KB)
|-
![[MB86900|SPARC MB86900]]
|[[Fujitsu]]<ref name="cpushack">{{cite web |title=Fujitsu to take ARM into the realm of Super |url=https://www.cpushack.com/2016/06/21/fujitsu-to-take-arm-into-the-realm-of-super/ |website=The CPU Shack Museum |date=June 21, 2016 |access-date=30 June 2019 |archive-date=June 30, 2019 |archive-url=https://web.archive.org/web/20190630094926/http://www.cpushack.com/2016/06/21/fujitsu-to-take-arm-into-the-realm-of-super/ |url-status=live }}</ref><ref name="cpu-collection">{{cite web |title=Fujitsu SPARC |url=http://www.cpu-collection.de/?tn=0&l0=cl&l1=SPARC&l2=Fujitsu |website=cpu-collection.de |access-date=30 June 2019 |archive-date=August 6, 2016 |archive-url=https://web.archive.org/web/20160806032335/http://www.cpu-collection.de/?tn=0&l0=cl&l1=SPARC&l2=Fujitsu |url-status=live }}</ref><ref name="timeline">{{cite web |title=Timeline |url=https://sparc.org/timeline/ |website=SPARC International |access-date=30 June 2019 |archive-date=April 24, 2019 |archive-url=https://web.archive.org/web/20190424043743/http://sparc.org/timeline/ |url-status=live }}</ref>
|14.28&ndash;33||V7||1986||1×1=1||1300||0.11||{{n/a}}||256||{{n/a}}||{{n/a}}||colspan="2"|0&ndash;128 (unified)||{{CNone|none}}||{{CNone|none}}
|-
!SPARC
|Various<ref group="note">Various SPARC V7 implementations were produced by Fujitsu, [[LSI Logic]], Weitek, Texas Instruments, Cypress and Temic. A SPARC V7 processor generally consisted of several discrete chips, usually comprising an integer unit (IU), a [[floating-point unit]] (FPU), a [[memory management unit]] (MMU) and cache memory. Conversely, the Atmel (now Microchip Technology) TSC695 is a single-chip SPARC V7 implementation.</ref>
|14.28&ndash;40||V7||1989–1992||1×1=1||800&ndash;1300||~0.1&ndash;1.8||{{n/a}}||160&ndash;256||{{n/a}}||{{n/a}}||colspan="2"|0&ndash;128 (unified)||{{CNone|none}}||{{CNone|none}}
|-
!MN10501 (KAP)
|[[Solbourne Computer]],
Matsushita<ref>{{Cite web|url=https://www.floodgap.com/retrobits/solace/|title=Floodgap Retrobits presents the Solbourne Solace: a shrine to the forgotten SPARC|website=www.floodgap.com|access-date=2020-01-14|archive-date=December 1, 2020|archive-url=https://web.archive.org/web/20201201003135/http://www.floodgap.com/retrobits/solace/|url-status=live}}</ref>
|33–36
|V8
|1990–1991
|1x1=1
|{{n/a}}
|1.0<ref>{{Cite conference|last1=Sager|first1=D.|last2=Hinton|first2=G.|last3=Upton|first3=M.|last4=Chappell|first4=T.|last5=Fletcher|first5=T.D.|last6=Samaan|first6=S.|last7=Murray|first7=R.|book-title=2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) |title=A 0.18 μm CMOS IA32 microprocessor with a 4 GHZ integer execution unit |date=2001|location=San Francisco, CA, USA|publisher=IEEE|pages=324–325|doi=10.1109/ISSCC.2001.912658|isbn=978-0-7803-6608-4}}</ref>
|{{n/a}}
|{{n/a}}
|{{n/a}}
|{{n/a}}
|8
|8
|0–256
|{{CNone|none}}
|-
![[microSPARC]] I (Tsunami)
|TI TMS390S10
|40&ndash;50||V8||1992||1×1=1||800||0.8||225?||288||2.5||5||2||4||{{CNone|none}}||{{CNone|none}}
|-
![[SuperSPARC]] I (Viking)
|TI TMX390Z50 / Sun STP1020
|33&ndash;60||V8||1992||1×1=1||800||3.1||{{n/a}}||293||14.3||5||16||20||0–2048||{{CNone|none}}
|-
![[SPARClite]]
|Fujitsu MB8683x
|66&ndash;108||V8E||1992||1×1=1||{{n/a}}||{{n/a}}||{{n/a}}||144, 176||{{n/a}}||2.5/3.3–5.0&nbsp;V, 2.5–3.3&nbsp;V||1, 2, 8, 16||1, 2, 8, 16||{{CNone|none}}||{{CNone|none}}
|-
![[hyperSPARC]] (Colorado 1)
|Ross RT620A
|40&ndash;90||V8||1993||1×1=1||500||1.5||{{n/a}}||{{n/a}}||{{n/a}}||5?||0||8||128–256||{{CNone|none}}
|-
!microSPARC II (Swift)
|Fujitsu MB86904 / Sun STP1012
|60&ndash;125||V8||1994||1×1=1||500||2.3||233||321||5||3.3||8||16||{{CNone|none}}||{{CNone|none}}
|-
!hyperSPARC (Colorado 2)
|Ross RT620B
|90&ndash;125||V8||1994||1×1=1||400||1.5||{{n/a}}||{{n/a}}||{{n/a}}||3.3||0||8||128–256||{{CNone|none}}
|-
!SuperSPARC II (Voyager)
|Sun STP1021
|75&ndash;90||V8||1994||1×1=1||800||3.1||299||{{n/a}}||16||{{n/a}}||16||20||1024–2048||{{CNone|none}}
|-
!hyperSPARC (Colorado 3)
|Ross RT620C
|125&ndash;166||V8||1995||1×1=1||350||1.5||{{n/a}}||{{n/a}}||{{n/a}}||3.3||0||8||512–1024||{{CNone|none}}
|-
![[TurboSPARC]]
|Fujitsu MB86907
|160&ndash;180||V8||1996||1×1=1||350||3.0||132||416||7||3.5||16||16||512||{{CNone|none}}
|-
![[UltraSPARC]] (Spitfire)
|Sun STP1030
|143&ndash;167||V9||1995||1×1=1||470||3.8||315||521||30<ref group="note">@167&nbsp;MHz</ref>||3.3||16||16||512–1024||{{CNone|none}}
|-
!UltraSPARC (Hornet)
|Sun STP1030
|200||V9||1995||1×1=1||420||5.2||265||521||{{n/a}}||3.3||16||16||512–1024||{{CNone|none}}
|-
!hyperSPARC (Colorado 4)
|Ross RT620D
|180&ndash;200||V8||1996||1×1=1||350||1.7||{{n/a}}||{{n/a}}||{{n/a}}||3.3||16||16||512||{{CNone|none}}
|-
![[HAL SPARC64|SPARC64]]
|Fujitsu (HAL)
|101&ndash;118||V9||1995||1×1=1||400||{{n/a}}||Multichip||286||50||3.8||128||128||{{n/a}}||{{n/a}}
|-
![[HAL SPARC64#SPARC64 II|SPARC64 II]]
|Fujitsu (HAL)
|141&ndash;161||V9||1996||1×1=1||350||{{n/a}}||Multichip||286||64||3.3||128||128||{{n/a}}||{{n/a}}
|-
![[HAL SPARC64#SPARC64 GP|SPARC64 III]]
|Fujitsu (HAL) MBCS70301
|250&ndash;330||V9||1998||1×1=1||240||17.6||240||{{n/a}}||{{n/a}}||2.5||64||64||8192||{{n/a}}
|-
![[UltraSPARC II]]s (Blackbird)
|Sun STP1031
|250&ndash;400||V9||1997||1×1=1||350||5.4||149||521||25<ref group="note">@250&nbsp;MHz</ref>||2.5||16||16||1024 or 4096||{{CNone|none}}
|-
!UltraSPARC IIs (Sapphire-Black)
|Sun STP1032 / STP1034
|360&ndash;480||V9||1999||1×1=1||250||5.4||126||521||21<ref group="note">@400&nbsp;MHz</ref>||1.9||16||16||1024&ndash;8192||{{CNone|none}}
|-
![[UltraSPARC IIi]] (Sabre)
|Sun SME1040
|270&ndash;360||V9||1997||1×1=1||350||5.4||156||587||21||1.9||16||16||256&ndash;2048||{{CNone|none}}
|-
!UltraSPARC IIi (Sapphire-Red)
|Sun SME1430
|333&ndash;480||V9||1998||1×1=1||250||5.4||{{n/a}}||587||21<ref group="note">@440&nbsp;MHz</ref>||1.9||16||16||2048||{{CNone|none}}
|-
![[UltraSPARC IIe]] (Hummingbird)
|Sun SME1701
|400&ndash;500||V9||1999||1×1=1||180 Al||{{n/a}}||{{n/a}}||370||13<ref group="note">max. @500&nbsp;MHz</ref>||1.5–1.7||16||16||256||{{CNone|none}}
|-
!UltraSPARC IIi (IIe+) (Phantom)
|Sun SME1532
|550&ndash;650||V9||2000||1×1=1||180 Cu||{{n/a}}||{{n/a}}||370||17.6||1.7||16||16||512||{{CNone|none}}
|-
![[HAL SPARC64#SPARC64 GP|SPARC64 GP]]
|Fujitsu SFCB81147
|400&ndash;563||V9||2000||1×1=1||180||30.2||217||{{n/a}}||{{n/a}}||1.8||128||128||8192||{{n/a}}
|-
![[HAL SPARC64#SPARC64 GP|SPARC64 GP]]
| --
|600&ndash;810||V9||{{n/a}}||1×1=1||150||30.2||{{n/a}}||{{n/a}}||{{n/a}}||1.5||128||128||8192||{{n/a}}
|-
!SPARC64&nbsp;IV
|Fujitsu MBCS80523
|450&ndash;810||V9||2000||1×1=1||130||{{n/a}}||{{n/a}}||{{n/a}}||{{n/a}}||{{n/a}}||128||128||2048||{{n/a}}
|-
![[UltraSPARC III]] (Cheetah)
|Sun SME1050
|600||JPS1||2001||1×1=1||180 Al||29||330||1368||53||1.6||64||32||8192||{{CNone|none}}
|-
!UltraSPARC III (Cheetah)
|Sun SME1052
|750&ndash;900||JPS1||2001||1×1=1||130 Al||29||{{n/a}}||1368||{{n/a}}||1.6||64||32||8192||{{CNone|none}}
|-
!UltraSPARC III&nbsp;Cu (Cheetah+)
|Sun SME1056
|900&ndash;1200||JPS1||2001||1×1=1||130 Cu||29||232||1368||50<ref group="note">@1200&nbsp;MHz</ref>||1.6||64||32||8192||{{CNone|none}}
|-
![[UltraSPARC IIIi]] (Jalapeño)
|Sun SME1603
|1064&ndash;1593||JPS1||2003||1×1=1||130||87.5||206||959||52||1.3||64||32||1024||{{CNone|none}}
|-
![[SPARC64 V]] (Zeus)
|Fujitsu
||1100&ndash;1350||JPS1||2003||1×1=1||130||190||289||269||40||1.2||128||128||2048||{{n/a}}
|-
![[SPARC64 V#SPARC64 V+|SPARC64 V+]] (Olympus-B)
|Fujitsu
||1650&ndash;2160||JPS1||2004||1×1=1||90||400||297||279||65||1||128||128||4096||{{n/a}}
|-
![[UltraSPARC IV]] (Jaguar)
|Sun SME1167
|1050&ndash;1350||JPS2||2004||1×2=2||130||66||356||1368||108||1.35||64||32||16384||{{CNone|none}}
|-
![[UltraSPARC IV+]] (Panther)
|Sun SME1167A
|1500&ndash;2100||JPS2||2005||1×2=2||90||295||336||1368||90||1.1||64||64||2048||32768
|-
![[UltraSPARC T1]] (Niagara)
|Sun SME1905
|1000&ndash;1400||UA2005||2005||4×8=32||90||300||340||1933||72||1.3||8||16||3072||{{CNone|none}}
|-
![[SPARC64 VI]] (Olympus-C)
| Fujitsu
|2150&ndash;2400||JPS2||2007||2×2=4||90||540||422||{{n/a}}||120&ndash;150||1.1||128×2||128×2||4096&ndash;6144||{{CNone|none}}
|-
![[UltraSPARC T2]] (Niagara 2)
|Sun SME1908A
|1000&ndash;1600||UA2007||2007||8×8=64||65||503||342||1831||95||1.1&ndash;1.5||8||16||4096||{{CNone|none}}
|-
!UltraSPARC T2 Plus (Victoria Falls)
|Sun SME1910A
|1200&ndash;1600||UA2007|| 2008 ||8×8=64||65||503||342||1831||{{n/a}}||{{n/a}}||8||16||4096||{{CNone|none}}
|-
![[SPARC64 VII]] (Jupiter)<ref name="fujitsu-fx1-promo" />
|Fujitsu
|2400&ndash;2880||JPS2||2008||2×4=8||65||600||445||{{n/a}}||150||{{n/a}}||64×4||64×4||6144||{{CNone|none}}
|-
!UltraSPARC "RK" ([[Rock (processor)|Rock]])<ref name="sun-rock-whitepaper" />
|Sun SME1832
|2300||{{dunno}}||canceled<ref name="nytimes-rock-canceled" />||2×16=32||65||{{dunno}}||396||2326||{{dunno}}||{{dunno}}||32||32||2048||{{dunno}}
|-
![[SPARC64 VIIIfx]] (Venus)<ref name="heise-fujitsu-s64vii" /><ref name="inquirer-fujitsu-fastest" />
|Fujitsu
|2000||JPS1 / HPC-ACE||2009||1×8=8||45||760||513||1271||58||{{dunno}}||32×8||32×8||6144||{{CNone|none}}
|-
![[LEON|LEON2FT]]
|Atmel AT697F
|100||V8||2009||1×1=1||180||{{n/a}}||{{n/a}}||196||1||1.8/3.3||16||32||{{n/a}}||{{n/a}}|none
|-
![[SPARC T3]] (Rainbow Falls)
|Oracle/Sun
|1650||UA2007|| 2010 ||8×16=128||40<ref name="oracle-t3-whitepaper" />||{{dunno}} ||371||{{dunno}}||139||{{dunno}}||8||16||6144||{{CNone|none}}
|-
![[FeiTeng|Galaxy FT-1500]]
|[[National University of Defense Technology|NUDT]] (China)
|1800||UA2007|| 2013 ||8×16=128||40||{{dunno}} ||{{dunno}} ||{{dunno}}||65||{{dunno}}||16×16||16×16||512×16||4096
|-
![[SPARC64 VII+]] (Jupiter-E <small>''or''</small> M3)<ref name="register-t4-next-year" /><ref name="fujitsu-m-whitepaper" />
|Fujitsu
|2667–3000||JPS2|| 2010 ||2×4=8||65||{{n/a}}||{{n/a}}||{{n/a}}||160||{{n/a}}||64×4||64×4||12288||{{CNone|none}}
|-
![[LEON|LEON3FT]]
|[[Cobham plc|Cobham Gaisler]] GR712RC
|100||V8E|| 2011 ||1×2=2||180||{{n/a}}||{{n/a}}||{{n/a}}||1.5<ref group="note">excluding I/O buses</ref>||1.8/3.3||4x4Kb||4x4Kb||{{CNone|none}}||{{CNone|none}}
|-
![[MCST-R1000|R1000]]
|[[Moscow Center of SPARC Technologies|MCST]] (Russia)
|1000||{{dunno}}|| 2011 ||1×4=4||90||180||128||{{n/a}}||15||1, 1.8, 2.5||32||16||2048||{{CNone|none}}
|-
![[SPARC T4]] (Yosemite Falls)<ref name="register-oracle-t4" />
|Oracle
|2850–3000||OSA2011|| 2011 ||8×8=64||40||855||403||{{dunno}}||240||{{dunno}}||16×8||16×8||128×8||4096
|-
![[SPARC64 VI#SPARC64 IXfx|SPARC64 IXfx]]<ref name="fujitsu-s64ixfx" /><ref name="fujitsu-fx10-launch" /><ref>{{cite web|url=https://www.fujitsu.com/downloads/TC/sc11/sparc64-ixfx-sc11.pdf|title=Ixfx Download|publisher=fujitsu.com|access-date=May 17, 2015|archive-date=May 18, 2015|archive-url=https://web.archive.org/web/20150518120540/http://www.fujitsu.com/downloads/TC/sc11/sparc64-ixfx-sc11.pdf|url-status=live}}</ref>
|Fujitsu
|1850||JPS1 / HPC-ACE||2012||1x16=16||40||1870||484||1442||110||{{dunno}}||32×16||32×16||12288||{{CNone|none}}
|-
![[SPARC64 X]] (Athena)<ref>{{cite web|url=https://www.fujitsu.com/global/Images/HC25.27.910-SPARC64.pdf|title=Images of SPARC64|publisher=fujitsu.com|access-date=August 29, 2017|archive-date=April 22, 2016|archive-url=https://web.archive.org/web/20160422083227/https://www.fujitsu.com/global/Images/HC25.27.910-SPARC64.pdf|url-status=live}}</ref>
|Fujitsu
|2800||OSA2011 / HPC-ACE||2012||2×16=32||28||2950||587.5||1500||270||{{dunno}}||64×16||64×16||24576||{{CNone|none}}
|-
![[SPARC T5]]
|Oracle
|3600||OSA2011|| 2013 ||8×16=128||28||1500||478||{{dunno}}||{{dunno}}||{{dunno}}||16×16||16×16||128×16||8192
|-
!SPARC M5<ref>{{cite web|url=https://www.oracle.com/us/products/servers-storage/servers/sparc/oracle-sparc/m5-32/m5-processor-ds-1922646.pdf|title=Oracle Products|publisher=oracle.com|access-date=August 29, 2017|archive-date=March 8, 2017|archive-url=https://web.archive.org/web/20170308224648/http://www.oracle.com/us/products/servers-storage/servers/sparc/oracle-sparc/m5-32/m5-processor-ds-1922646.pdf|url-status=live}}</ref>
|Oracle
|3600||OSA2011|| 2013 ||8×6=48||28||3900||511||{{dunno}}||{{dunno}}||{{dunno}}||16×6||16×6||128×6||49152
|-
!SPARC M6<ref>{{cite web|url=https://www.oracle.com/us/products/servers-storage/servers/sparc/oracle-sparc/m6-32/sparc-m6-processor-ds-2015586.pdf|title=Oracle SPARC products|publisher=oracle.com|access-date=August 29, 2017|archive-date=September 26, 2018|archive-url=https://web.archive.org/web/20180926012640/http://www.oracle.com/us/products/servers-storage/servers/sparc/oracle-sparc/m6-32/sparc-m6-processor-ds-2015586.pdf|url-status=live}}</ref>
|Oracle
|3600||OSA2011|| 2013 ||8×12=96||28||4270||643||{{dunno}}||{{dunno}}||{{dunno}}||16×12||16×12||128×12||49152
|-
![[SPARC64 X+]] (Athena+)<ref>{{cite web|url=https://www.fujitsu.com/global/Images/HotChips24_Fujitsu_presentation.pdf|title=Fujitsu Presentation pdf|publisher=fujitsu.com|access-date=August 29, 2017|archive-date=April 22, 2016|archive-url=https://web.archive.org/web/20160422083242/https://www.fujitsu.com/global/Images/HotChips24_Fujitsu_presentation.pdf|url-status=live}}</ref>
|Fujitsu
|3200–3700||OSA2011 / HPC-ACE||2014||2×16=32||28||2990||600||1500||392||{{dunno}}||64×16||64×16||24M||{{CNone|none}}
|-
![[SPARC64 VI#SPARC64 XIfx|SPARC64 XIfx]]<ref>{{cite web|url=https://www.fujitsu.com/global/Images/20140811hotchips26.pdf|title=Fujitsu Global Images|publisher=fujitsu.com|access-date=August 29, 2017|url-status=dead|archive-url=https://web.archive.org/web/20150518120521/http://www.fujitsu.com/global/Images/20140811hotchips26.pdf|archive-date=May 18, 2015|df=mdy-all}}</ref>
|Fujitsu
|2200||OSA2011 / HPC-ACE2||2014||1×(32+2)=34||20||3750||{{dunno}}||1001||{{dunno}}||{{dunno}}||64×34||64×34||12M×2||{{CNone|none}}
|-
![[SPARC M7]]<ref>{{cite web|url=https://swisdev.oracle.com/_files/M7_Preso.pdf|title=M7: Next Generation SPARC. Hotchips 26|publisher=swisdev.oracle.com|access-date=August 12, 2014|archive-date=October 31, 2014|archive-url=https://web.archive.org/web/20141031195402/https://swisdev.oracle.com/_files/M7_Preso.pdf|url-status=live}}</ref><ref>{{cite web|url=https://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-t7-m7-server-architecture-2702877.pdf|title=Oracle's SPARC T7 and SPARC M7 Server Architecture|publisher=oracle.com|access-date=October 10, 2015|archive-date=November 6, 2015|archive-url=https://web.archive.org/web/20151106053601/http://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-t7-m7-server-architecture-2702877.pdf|url-status=live}}</ref>
|Oracle
|4133||OSA2015||2015||8×32=256||20||>10,000||{{dunno}}||{{dunno}}||{{dunno}}||{{dunno}}||16×32||16×32||256×24||65536
|-
!SPARC S7<ref>{{cite web|url=https://old.hotchips.org/wp-content/uploads/hc_archives/hc27/HC27.24-Monday-Epub/HC27.24.30-HP-Cloud-Comm-Epub/HC27.24.330-sonoma.Vinalk-oracle-v3.pdf |archive-url=https://ghostarchive.org/archive/20221009/https://old.hotchips.org/wp-content/uploads/hc_archives/hc27/HC27.24-Monday-Epub/HC27.24.30-HP-Cloud-Comm-Epub/HC27.24.330-sonoma.Vinalk-oracle-v3.pdf |archive-date=2022-10-09 |url-status=live|title=Hot Chips – August 23–25, 2015 – Conf. Day1 – Oracle's Sonoma Processor: Advanced low-cost SPARC processor for enterprise workloads|first1=Basant|last1=Vinaik|first2=Rahoul|last2=Puri|date=August 24, 2015|publisher=hotchips.org|access-date=January 25, 2022}}</ref><ref>{{cite web|url=https://www.theregister.co.uk/2015/08/24/oracle_sonoma_processor_sparc/?page=1|title=Blueprints revealed: Oracle crams Sparc M7 and InfiniBand into cheaper 'Sonoma' chips|publisher=theregister.co.uk|access-date=August 29, 2017|archive-date=August 29, 2017|archive-url=https://web.archive.org/web/20170829121821/http://www.theregister.co.uk/2015/08/24/oracle_sonoma_processor_sparc/?page=1|url-status=live}}</ref>
|Oracle
|4270||OSA2015||2016||8×8=64||20||{{dunno}}||{{dunno}}||{{dunno}}||{{dunno}}||{{dunno}}||16×8||16×8||256×2+256×4||16384
|-
!SPARC64 XII<ref>{{cite web|url=https://www.fujitsu.com/jp/documents/products/computing/servers/unix/sparc/events/2017/coolchips20/CoolChips20-rev8.pdf|title=Documents at Fujitsu|publisher=fujitsu.com|access-date=August 29, 2017|archive-date=August 29, 2017|archive-url=https://web.archive.org/web/20170829121542/http://www.fujitsu.com/jp/documents/products/computing/servers/unix/sparc/events/2017/coolchips20/CoolChips20-rev8.pdf|url-status=live}}</ref>
|Fujitsu
|4250||OSA2011 / HPC-ACE||2017||8×12=96||20||5500||795||1860||{{dunno}}||{{dunno}}||64×12||64×12||512×12||32768
|-
![[SPARC M8]]<ref>{{cite web|url=https://www.oracle.com/corporate/pressrelease/oracle-sparc-m8-091817.html|title=Oracle's New SPARC Systems Deliver 2-7x Better Performance, Security Capabilities, and Efficiency than Intel-based Systems|publisher=oracle.com|access-date=September 18, 2017|archive-date=September 18, 2017|archive-url=https://web.archive.org/web/20170918151550/https://www.oracle.com/corporate/pressrelease/oracle-sparc-m8-091817.html|url-status=live}}</ref><ref>{{cite web|url=https://www.oracle.com/us/products/servers-storage/sparc-m8-processor-ds-3864282.pdf|title=SPARC M8 Processor|publisher=oracle.com|access-date=September 18, 2017|archive-date=February 28, 2019|archive-url=https://web.archive.org/web/20190228101811/http://www.oracle.com/us/products/servers-storage/sparc-m8-processor-ds-3864282.pdf|url-status=live}}</ref>
|Oracle
|5000||OSA2017||2017||8×32=256||20||{{dunno}}||{{dunno}}||{{dunno}}||{{dunno}}||{{dunno}}||32×32||16×32||128×32+256×8||65536
|-
![[LEON|LEON4]]
|[[Cobham plc|Cobham Gaisler]] GR740
|250<ref group="note">nominal; specification from 100 to 424&nbsp;MHz depending on attached RAM capabilities</ref>||V8E|| 2017 ||1×4=4||32||{{n/a}}||{{n/a}}||{{n/a}}||{{n/a}}||1.2/2.5/3.3||4x4||4x4||2048||{{CNone|none}}
|-
![[MCST-R2000|R2000]]
|[[Moscow Center of SPARC Technologies|MCST]] (Russia)
|2000|| {{dunno}} || 2018 ||1×8=8||28||500|| {{dunno}} ||{{n/a}}||{{dunno}}||{{dunno}}||{{dunno}}||{{dunno}}||{{dunno}}||{{CNone|none}}
|-
![[LEON|LEON5]]
|[[Cobham plc|Cobham Gaisler]] 
|{{n/a}}||V8E|| 2019 ||{{dunno}}||{{dunno}}||{{n/a}}||{{n/a}}||{{n/a}}||{{n/a}}||{{n/a}}||{{dunno}}||{{dunno}}||16–8192||{{CNone|none}}
|-
!                            Name (codename)
!                            Model
! abbr="Frequency"         | Frequency (MHz)
! abbr="Architecture"      | Arch. version
!                            Year
! abbr="Threads"           | Total threads<ref group="note" name=threads/>
! abbr="Process"           | Process (nm)
! abbr="Transistors"       | Transistors (millions)
! abbr="Size"              | Die size (mm<sup>2</sup>)
!                            IO pins
! abbr="Power"             | Power (W)
! abbr="Voltage"           | Voltage (V)
! abbr="Data cache"        | L1 Dcache (KB)
! abbr="Instruction cache" | L1 Icache (KB)
! abbr="L2 Cache"          | L2 cache (KB)
! abbr="L3 Cache"          | L3 cache (KB)
|}
'''Notes''':
{{Reflist|group="note"}}

==Operating system support==
SPARC machines have generally used Sun's [[SunOS]], [[Solaris (operating system)|Solaris]], [[JavaOS]], or [[OpenSolaris]] including derivatives [[illumos]] and [[OpenIndiana]], but other [[operating system]]s have also been used, such as [[NeXTSTEP]], [[RTEMS]], [[FreeBSD]], [[OpenBSD]], [[NetBSD]], and [[Linux]].

In 1993, [[Intergraph]] announced a port of [[Windows NT]] to the SPARC architecture,<ref name="sunflash-nt" /> but it was later cancelled.

In October 2015, Oracle announced a "Linux for SPARC reference platform".<ref name="sparclinux" />

==Open source implementations==
Several fully [[open-source hardware|open source]] implementations of the SPARC architecture exist:

* [[LEON]], a 32-bit [[radiation hardening|radiation-tolerant]], SPARC V8 implementation, designed especially for space use. [[Source code]] is written in [[VHDL]], and licensed under the [[GNU General Public License|GPL]].
* [[OpenSPARC]] [[UltraSPARC T1|T1]], released in 2006, a 64-bit, 32-thread implementation conforming to the UltraSPARC Architecture 2005 and to SPARC Version 9 (Level 1). Source code is written in [[Verilog]], and licensed under many licenses.  Most OpenSPARC T1 source code is licensed under the GPL.  Source based on existent open source projects will continue to be licensed under their current licenses.  Binary programs are licensed under a binary [[software license agreement]].
* [[S1 Core|S1]], a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design. It is a single UltraSPARC V9 core capable of 4-way SMT. Like the T1, the source code is licensed under the GPL.
* [[OpenSPARC]] [[UltraSPARC T2|T2]], released in 2008, a 64-bit, 64-thread implementation conforming to the UltraSPARC Architecture 2007 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses.  Most OpenSPARC T2 source code is licensed under the GPL. Source based on existing open source projects will continue to be licensed under their current licenses.  Binary programs are licensed under a binary Software License Agreement.

A fully [[open-source software|open source]] simulator for the SPARC architecture also exists:

* [https://web.archive.org/web/20160529045508/https://sites.google.com/site/rampgold/ RAMP Gold], a 32-bit, 64-thread SPARC Version 8 implementation, designed for FPGA-based architecture simulation. RAMP Gold is written in ~36,000 lines of [[SystemVerilog]], and licensed under the [[BSD licenses]].

==Supercomputers==
For HPC loads Fujitsu builds specialized [[SPARC64 VI#HPC specialized processors .28fx.29|SPARC64 fx]] processors  with a new instruction extensions set, called HPC-ACE (High Performance Computing – Arithmetic Computational Extensions).

Fujitsu's [[K computer]] ranked {{Numero|1}} in the [[TOP500]] June 2011 and November 2011 lists. It combines 88,128 SPARC64 [[SPARC64 VI#SPARC64 VIIIfx|VIIIfx]] CPUs, each with eight cores, for a total of 705,024 cores—almost twice as many as any other system in the [[TOP500]] at that time. The K Computer was more powerful than the next five systems on the list combined, and had the highest performance-to-power ratio of any supercomputer system.<ref name="top500-2011-06" /> It also ranked {{Numero|6}} in the [[Green500]] June 2011 list, with a score of 824.56 MFLOPS/W.<ref name="green500-2011-06" />  In the November 2012 release of [[TOP500]], the K computer ranked {{Numero|3}}, using by far the most power of the top three.<ref name="top500-2012-11" />  It ranked {{Numero|85}} on the corresponding [[Green500]] release.<ref name="green500-2012-11" /> Newer HPC processors, [[SPARC64 VI#SPARC64 IXfx|IXfx]] and [[SPARC64 VI#SPARC64 XIfx|XIfx]], were included in recent [[PRIMEHPC FX10]] and FX100 supercomputers.

[[Tianhe-2]] ([[TOP500]] {{Numero|1}} as of November 2014<ref name="top500-2014-11" />) has a number of nodes with [[FeiTeng|Galaxy FT-1500]] [[OpenSPARC]]-based processors developed in China. However, those processors did not contribute to the [[LINPACK]] score.<ref name="nvidia-fastest-tianhe-1" /><ref name=cw>{{cite news|url=https://www.computerworld.com/s/article/9194799/U.S._says_China_building_entirely_indigenous_supercomputer_|title=U.S. says China building 'entirely indigenous' supercomputer|last=Thibodeau|first=Patrick|publisher=[[Computerworld]]|date=November 4, 2010|access-date=August 28, 2017|archive-date=October 11, 2012|archive-url=https://web.archive.org/web/20121011154327/http://www.computerworld.com/s/article/9194799/U.S._says_China_building_entirely_indigenous_supercomputer_|url-status=live}}</ref>

==See also==
* [[ERC32]]&nbsp;— based on SPARC V7 specification
* [[Ross Technology, Inc.]]&nbsp;— a SPARC microprocessor developer during the 1980s and 1990s
* [[Sparcle]]&nbsp;— a modified SPARC with multiprocessing support used by the MIT Alewife project
* [[LEON]]&nbsp;— a space rated SPARC V8 processor.
* [[MCST-4R|R1000]]&nbsp;— a Russian quad-core microprocessor based on SPARC V9 specification
* [[FeiTeng#Galaxy FT-1500|Galaxy FT-1500]]&nbsp;— a Chinese 16-core [[OpenSPARC]]-based processor

==References==
{{Reflist|30em|refs=
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==External links==
{{Commons category|SPARC microprocessors}}
* [https://www.sparc.org/ SPARC International, Inc.]
* {{webarchive |url=https://web.archive.org/web/20191013102714/http://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-processor-2516655.html |date=October 13, 2019 |title=Oracle SPARC Processor Documentation }} 
* [https://www.sparc.org/technical-documents/ SPARC Technical Documents]
* [http://www.oracle.com/technetwork/systems/opensparc/ OpenSPARC Architecture specification] 
* [https://sun4v.github.io/ Hypervisor/Sun4v Reference Materials]
* Fujitsu SPARC64 {{webarchive |url=https://web.archive.org/web/20190403225509/http://www.fujitsu.com/global/solutions/business-technology/tc/catalog/ |date=April 3, 2019 |title=V, VI, VII, VIIIfx, IXfx Extensions}}, [https://www.fujitsu.com/global/products/computing/servers/unix/sparc/downloads/documents/ X / X+ Specifications], [https://web.archive.org/web/20250527022245/https://www.fujitsu.com/jp/documents/products/computing/servers/unix/sparc/downloads/documents/SPARC64XII-Specification.vol20.pdf XII Specification], and [https://www.fujitsu.com/downloads/JP/jsuper/sparc64/sparc64xifx-extensionsj.pdf XIfx Extensions]
* {{webarchive |url=https://web.archive.org/web/20100114162013/http://www.sun.com/processors/documentation.html |date=January 14, 2010 |title= Sun – UltraSPARC Processors Documentation}}
* {{webarchive |url=https://web.archive.org/web/20111209011516/http://wikis.sun.com/display/FOSSdocs/Home |date=December 9, 2011 |title= Sun – FOSS Open Hardware Documentation}}
* {{webarchive |url=https://web.archive.org/web/20110227003720/http://www.opensparc.net/ |date=February 27, 2011 |title= OpenSPARC}}
* {{webarchive |url=https://web.archive.org/web/20180525101430/http://www.oracle.com/us/products/servers-storage/servers/sparc/oracle-sparc/sparc-roadmap-slide-2076743.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.oracle.com/us/products/servers-storage/servers/sparc/oracle-sparc/sparc-roadmap-slide-2076743.pdf |archive-date=2022-10-09 |url-status=live |date=May 25, 2018 |title= Oracle SPARC and Solaris Public Roadmap}}
* [https://www.fujitsu.com/global/products/computing/servers/unix/sparc/key-reports/roadmap/ Fujitsu SPARC Roadmap]
* [http://www.cpu-collection.de/?tn=1&l0=cl&l1=SPARC SPARC processor images and descriptions]
* [https://mbus.sunhelp.org ''The Rough Guide to MBus Modules''] (SuperSPARC, hyperSPARC)
* {{YouTube|juTFKbQSFYs|SPARC Version 9, lecture by David Ditzel}}
* [https://oscomp.hu/bgafc/oses4sparc64.php A quite an extensive list of operating systems supporting SPARC64 processors]

{{RISC-based processor architectures}}
{{Sun hardware}}
{{Oracle}}
{{CPU technologies}}
{{Authority control}}

{{DEFAULTSORT:Sparc}}
[[Category:Computer-related introductions in 1986]]
[[Category:SPARC microprocessor architecture| ]]
[[Category:Sun microprocessors]]
[[Category:32-bit computers]]
[[Category:64-bit computers]]