View source for Resistive random-access memory

{{short description|Novel type of computer memory}}
{{See also|Electrochemical random-access memory}}
{{Memory types}}
'''Resistive random-access memory''' ('''ReRAM''' or '''RRAM''') is a type of [[non-volatile]] (NV) [[random-access memory|random-access]] (RAM) computer memory that works by changing the resistance across a [[dielectric]] solid-state material, often referred to as a [[memristor]]. One major advantage of ReRAM over other NVRAM technologies is the ability to scale below 10&nbsp;nm.

ReRAM bears some similarities to [[Programmable metallization cell|conductive-bridging RAM]] (CBRAM) and [[phase-change memory]] (PCM) in that they change dielectric material properties. CBRAM involves one electrode providing ions that dissolve readily in an electrolyte material, while PCM involves generating sufficient Joule heating to effect amorphous-to-crystalline or crystalline-to-amorphous phase changes. By contrast, ReRAM involves generating defects in a thin oxide layer, known as oxygen vacancies (oxide bond locations where the oxygen has been removed), which can subsequently charge and drift under an electric field. The motion of oxygen ions and vacancies in the oxide would be analogous to the motion of electrons and holes in a semiconductor.

Although ReRAM was initially seen as a replacement technology for [[flash memory]], the cost and performance benefits of ReRAM have not been enough for companies to proceed with the replacement. Apparently, a broad range of materials can be used for ReRAM. However, the discovery<ref>{{cite book|last1=Lee|first1=H. Y.|last2=Chen|first2=P. S.|last3=Wu|first3=T. Y.|last4=Chen|first4=Y. S.|last5=Wang|first5=C. C.|last6=Tzeng|first6=P. J.|last7=Lin|first7=C. H.|last8=Chen|first8=F.|last9=Lien|first9=C. H.|last10=Tsai|first10=M. J.|title=2008 IEEE International Electron Devices Meeting |chapter=Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM |date=2008|pages=1–4|doi=10.1109/IEDM.2008.4796677|isbn=978-1-4244-2377-4|s2cid=26927991}}</ref> that the popular [[High-κ dielectric|high-κ]] gate dielectric [[Hafnium(IV) oxide|HfO<sub>2</sub>]] can be used as a low-voltage ReRAM has encouraged researchers to investigate more possibilities.

RRAM is the registered [[trademark]] name of [[Sharp Corporation]], a Japanese electronic components manufacturer, in some countries, including members of the [[European Union]].<ref>{{cite web|title=RRAM: Trademark 003062791|url=https://euipo.europa.eu/eSearch/#details/trademarks/003062791|website=euipo.europa.eu|publisher=EUIPO}}</ref>

An energy-efficient chip called NeuRRAM fixes an old design flaw to run large-scale AI algorithms on smaller devices, reaching the same accuracy as digital computers, at least for applications needing only a few million bits of neural state. As NeuRRAM is an analog technology, it suffers from the same analog noise problems that plague other analog semiconductors. While this is a handicap, many neural processors do not need bit-perfect state storage to do useful work.<ref>{{cite web|title=NeuRRAM|url=https://www.quantamagazine.org/a-brain-inspired-chip-can-run-ai-with-far-less-energy-20221110/|website=www.quantamagazine.org|date=10 November 2022 |publisher=Simon's Foundation}}</ref>

== History ==
In the early 2000s, ReRAMs were under development by a number of companies, some of which filed patent applications claiming various implementations of this technology.<ref>{{US patent|6531371}}</ref><ref>{{US patent|7292469}}</ref><ref>{{US patent|6867996}}</ref> ReRAM has entered commercialization on an initially limited KB-capacity scale.{{citation needed|reason=previous cite was essentially a blank page|date=November 2020}}

In February 2012, [[Rambus]] bought a ReRAM company called Unity Semiconductor for $35 million.<ref name="UnityRambus2012">{{Citation |last=Mellor |first=Chris |date=7 February 2012|title=Rambus drops $35m for Unity Semiconductor|url=http://www.channelregister.co.uk/2012/02/07/rambus_unity_semiconductor/}}</ref> [[Panasonic]] launched a ReRAM evaluation kit in May 2012, based on a [[tantalum oxide]] 1T1R (1 transistor – 1 resistor) memory cell architecture.<ref>{{cite press release |title=the new microcontrollers with on-chip non-volatile memory ReRAM |url=http://panasonic.co.jp/corp/news/official.data/data.dir/jn120515-1/jn120515-1.html |publisher=Panasonic |date=May 15, 2012 |access-date=May 16, 2012}}</ref>

In 2013, [[Crossbar (computer hardware manufacturer)|Crossbar]] introduced an ReRAM prototype as a chip about the size of a postage stamp that could store 1&nbsp;TB of data. In August 2013, the company claimed that large-scale production of their ReRAM chips was scheduled for 2015.<ref>{{cite press release |title=Next-gen storage wars: In the battle of RRAM vs 3D NAND flash, all of us are winners |url=http://www.pcworld.com/article/2046282/next-gen-storage-wars-in-the-battle-of-rram-vs-3d-nand-flash-all-of-us-are-winners.html |publisher=PC World |date=August 9, 2013 |access-date=January 28, 2014 |archive-date=February 2, 2014 |archive-url=https://web.archive.org/web/20140202144151/http://www.pcworld.com/article/2046282/next-gen-storage-wars-in-the-battle-of-rram-vs-3d-nand-flash-all-of-us-are-winners.html |url-status=dead }}</ref> The memory structure (Ag/a-Si/Si) closely resembles a silver-based CBRAM.

Also in 2013, Hewlett-Packard demonstrated a memristor-based ReRAM [[wafer (electronics)|wafer]], and predicted that 100 TB SSDs based on the technology could be available in 2018 with 1.5 PB capacities available in 2020, just in time for the stop in growth of NAND flash capacities.<ref>{{Cite web|url=https://www.theregister.com/2013/11/01/hp_memristor_2018/|title=HP 100TB Memristor drives by 2018 – if you're lucky, admits tech titan|first=Chris|last=Mellor|website=www.theregister.com}}</ref>

Different forms of ReRAM have been disclosed, based on different dielectric materials, spanning from [[perovskite]]s to [[transition metal oxides]] to [[chalcogenide]]s. [[Silicon dioxide]] was shown to exhibit resistive switching as early as May 1966,<ref>{{Cite journal | doi = 10.1088/0508-3443/18/1/306 | title = A non-filamentary switching action in thermally grown silicon dioxide films| journal = British Journal of Applied Physics| volume = 18| issue = 1| pages = 29–32| year = 1967| last1 = Lamb| first1 = D R| last2 = Rundle| first2 = P C| bibcode = 1967BJAP...18...29L}}</ref> and has recently been revisited.<ref>{{Cite journal | doi = 10.1143/JJAP.46.2172 | title = Resistance Switching Characteristics for Nonvolatile Memory Operation of Binary Metal Oxides| journal = Japanese Journal of Applied Physics| volume = 46| issue = 4B| pages = 2172| year = 2007| last1 = Park| first1 = In-Sung| last2 = Kim| first2 = Kyong-Rae| last3 = Lee| first3 = Sangsul| last4 = Ahn| first4 = Jinho| bibcode = 2007JaJAP..46.2172P| s2cid = 122024553}}</ref><ref name="hal.archives-ouvertes.fr">{{Cite journal | last1 = Mehonic | first1 = A. | last2 = Cueff | first2 = S. B. | last3 = Wojdak | first3 = M. | last4 = Hudziak | first4 = S. | last5 = Jambois | first5 = O. | last6 = Labbé | first6 = C. | last7 = Garrido | first7 = B. | last8 = Rizk | first8 = R. | last9 = Kenyon | first9 = A. J. | doi = 10.1063/1.3701581 | title = Resistive switching in silicon suboxide films | journal = Journal of Applied Physics | volume = 111 | issue = 7 | pages = 074507–074507–9 | year = 2012 |bibcode = 2012JAP...111g4507M | url = https://hal.archives-ouvertes.fr/hal-01148232/document | doi-access = free }}</ref>

In 1963 and 1964, a thin-film resistive memory array was first proposed by members of the [[University of Nebraska–Lincoln]].<ref name="Bashara 1963">
{{cite book|last1=Bashara|first1=N. M.|last2=Nielsen|first2=P. H.|title=Annual Report 1963 Conference on Electrical Insulation |chapter=Memory effects in thin film negative resistance structures |date=1963|pages=29–32|doi=10.1109/EIC.1963.7466544|isbn=978-1-5090-3119-1}}
</ref><ref name="Nielsen 1964">
{{cite journal|last1=Nielsen|first1=P. H.|last2=Bashara|first2=N. M.|title=The reversible voltage-induced initial resistance in the negative resistance sandwich structure|journal=IEEE Transactions on Electron Devices|date=1964|volume=11|issue=5|pages=243–244|doi=10.1109/T-ED.1964.15319|issn=0018-9383|bibcode=1964ITED...11..243N}}
</ref> Further work on this new thin-film resistive memory was reported by J.G. Simmons in 1967.<ref name="Simmons 1967">
{{cite journal|last1=Simmons|first1=J. G.|last2=Verderber|first2=R. R.|title=New thin-film resistive memory|journal=Radio and Electronic Engineer|date=August 1967|volume=34|issue=2|pages=81–89|doi=10.1049/ree.1967.0069|url=https://ieeexplore.ieee.org/document/5267142|archive-url=https://web.archive.org/web/20170101205307/http://ieeexplore.ieee.org/document/5267142|url-status=dead|archive-date=January 1, 2017|issn=0033-7722|url-access=subscription}}
</ref><ref name="Simmons 1968">
{{cite journal|last1=Lomax|first1=R. W.|last2=Simmons|first2=J. G.|title=A thin film, cold cathode, alpha-numeric display panel|journal=Radio and Electronic Engineer|date=1968|volume=35|issue=5|pages=265–272|doi=10.1049/ree.1968.0039|url=https://ieeexplore.ieee.org/document/5267292|archive-url=https://web.archive.org/web/20180320170551/http://ieeexplore.ieee.org/document/5267292/|url-status=dead|archive-date=March 20, 2018|issn=0033-7722|url-access=subscription}}
</ref> In 1970, members of the [[Atomic Energy Research Establishment]] and [[University of Leeds]] attempted to explain the mechanism theoretically.<ref name="Dearnaley 1970">
{{cite journal|last1=Dearnaley|first1=G.|last2=Stoneham|first2=A. M.|last3=Morgan|first3=D. V.|title=Electrical phenomena in amorphous oxide films|journal=Reports on Progress in Physics|date=1970|volume=33|issue=3|pages=1129{{endash}}1191|doi=10.1088/0034-4885/33/3/306|url=https://pdfs.semanticscholar.org/2e88/58f3b9e71602bff2e318d82cc13a361e16f5.pdf|language=en|issn=0034-4885|quote=[p. 1180] A thin-film resistive memory array based upon voltage-controlled negative resistance in SiO, was first proposed by Nielsen and Bashara (1964) and such a device has been described by Simmons and Verderber (1968).|bibcode=1970RPPh...33.1129D|s2cid=14500522|archive-url=https://web.archive.org/web/20180320170100/https://pdfs.semanticscholar.org/2e88/58f3b9e71602bff2e318d82cc13a361e16f5.pdf|archive-date=2018-03-20}}
</ref>{{rp|1180}} In May 1997, a research team from the [[University of Florida]] and [[Honeywell]] reported a manufacturing method for "magneto-resistive random access memory" by utilizing electron cyclotron resonance plasma etching.<ref name="Jung 1997">
{{cite journal|last1=Jung|first1=K. B.|last2=Lee|first2=J. W.|last3=Park|first3=Y. D.|last4=Childress|first4=J. R.|last5=Pearton|first5=S. J.|last6=Jenson|first6=M.|last7=Hurst|first7=A. T.|title=Electron cyclotron resonance plasma etching of materials for magneto-resistive random access memory applications|journal=Journal of Electronic Materials|date=1 November 1997|volume=26|issue=11|pages=1310–1313|doi=10.1007/s11664-997-0076-x|language=en|issn=0361-5235|bibcode=1997JEMat..26.1310J|s2cid=93702602}}
</ref>

[[Leon Chua]] argued that all two-terminal non-volatile memory devices including ReRAM should be considered [[memristors]].<ref name="chua11">{{citation |last=Chua |first=L. O. |date=2011 |title=Resistance switching memories are memristors |journal=Applied Physics A |volume=102 |issue=4 |pages=765–783 |doi=10.1007/s00339-011-6264-9 |bibcode=2011ApPhA.102..765C|doi-access=free }}</ref> Stan Williams of [[HP Labs]] also argued that ReRAM was a [[memristor]].<ref name="Mellor2011">{{Citation |last=Mellor |first=Chris |date=10 October 2011|title=HP and Hynix to produce the memristor goods by 2013|url=https://www.theregister.co.uk/2011/10/10/memristor_in_18_months/ |work=The Register |access-date=2012-03-07}}</ref> However, others challenged this terminology and the applicability of memristor theory to any physically realizable device is open to question.<ref name="Meuffels_2012">{{cite arXiv |last1=Meuffels |first1=P. |last2=Soni |first2=R. |date=2012 |title=Fundamental Issues and Problems in the Realization of Memristors |eprint=1207.7319 |mode=cs2|class=cond-mat.mes-hall }}</ref><ref name="DiVentra_2013">{{cite journal|last=Di Ventra|first=Massimiliano|author2=Pershin, Yuriy V. |title=On the physical properties of memristive, memcapacitive and meminductive systems|journal=Nanotechnology|date=2013|volume=24|issue=25|doi=10.1088/0957-4484/24/25/255201|arxiv = 1302.7063 |bibcode = 2013Nanot..24y5201D|pmid=23708238|pages=255201|citeseerx=10.1.1.745.8657|s2cid=14892809}}</ref><ref name="Kim_2019">{{cite journal|last1=Kim|first1=J.|last2=Pershin|first2=Y. V.|last3=Yin|first3=M.|last4=Datta|first4=T.|last5=Di Ventra|first5=M. |title=An experimental proof that resistance-switching memories are not memristors |journal=Advanced Electronic Materials |volume=6 |issue=7 |date=July 2020 |doi=10.1002/aelm.202000010|doi-access=free |arxiv=1909.07238|s2cid=202577242}}</ref> Whether redox-based resistively switching elements (ReRAM) are covered by the current memristor theory is disputed.<ref name=memristor_nanobattery>{{Cite journal | last1 = Valov | first1 = I. | last2 = Linn | first2 = E. | last3 = Tappertzhofen | first3 = S. | last4 = Schmelzer | first4 = S. | last5 = van den Hurk | first5 = J. | last6 = Lentz | first6 = F. | last7 = Waser | first7 = R. | title = Nanobatteries in redox-based resistive switches require extension of memristor theory | doi = 10.1038/ncomms2784 | journal = Nature Communications | volume = 4 | pages = 1771 | year = 2013 | pmid = 23612312| pmc = 3644102| bibcode = 2013NatCo...4.1771V | arxiv = 1303.2589 }}</ref>

Silicon oxide presents an interesting case of resistance switching.<ref>{{Cite web |title=Intrinsic AI Solutions |url=https://www.intrinsicsemi.com/ |access-date=2023-11-02 |website=Intrinsic AI Solutions |language=en-GB}}</ref> Two distinct modes of intrinsic switching have been reported - surface-based, in which conductive silicon filaments are generated at exposed edges (which may be internal&mdash;within pores&mdash;or external&mdash;on the surface of mesa structures), and bulk switching, in which oxygen vacancy filaments are generated within the bulk of the oxide. The former mode suffers from oxidation of the filaments in air, requiring hermetic sealing to enable switching. The latter requires no sealing. In 2014 researchers from Rice University announced a silicon filament-based device that used a porous [[silicon dioxide|silicon oxide]] dielectric with no external edge structure - rather, filaments were formed at internal edges within pores. Devices can be manufactured at room temperature and have a sub-2V forming voltage, high on-off ratio, low power consumption, nine-bit capacity per cell, high switching speeds and good endurance. Problems with their inoperability in air can be overcome by hermetic sealing of devices.<ref>{{cite web|url=http://www.foresight.org/nanodot/?p=6188 |title=the Foresight Institute » Blog Archive » Nanotechnology-based next generation memory nears mass production |publisher=Foresight.org |access-date=2014-08-13|date=2014-08-10 }}</ref> Bulk switching in silicon oxide, pioneered by researchers at UCL ([[University College London]]) since 2012,<ref name="hal.archives-ouvertes.fr"/> offers low electroforming voltages (2.5V), switching voltages around 1V, switching times in the nanoseconds regime, and more than 10,000,000 cycles without device failure - all in ambient conditions.<ref>{{Cite journal | last1 = Mehonic | first1 = A. | last2 = Munde | first2 = M. S. | last3 = Ng | first3 = W. H. | last4 = Buckwell | first4 = M. | last5 = Montesi | first5 = L. | last6 = Bosman | first6 = M. | last7 = Shluger | first7 = A. L. | last8 = Kenyon | first8 = A. J. |doi = 10.1016/j.mee.2017.04.033 | title = Intrinsic resistance switching in amorphous silicon oxide for high performance SiOx ReRAM devices | journal = Microelectronic Engineering | volume = 178 | pages = 98–103 | year = 2017 | doi-access = free }}</ref>

== Forming ==
[[File:I-V of filamentary RRAM.png|right|thumb|300px|'''Filament forming:''' A 50 nm × 50 nm ReRAM cell by Crossbar ({{webarchive |url=https://web.archive.org/web/20150319001250/http://www.crossbar-inc.com:80/assets/img/media/Crossbar-RRAM-Technology-Whitepaper-080413.pdf |date=19 March 2015}}) {{clarify span|shows|what are the axes and units?|date=December 2014}} the instance of filament forming when the current abruptly increases beyond a certain voltage. A transistor is often used to limit current to prevent a runaway breakdown following the filament formation.]]
The basic idea is that a [[dielectric]], which is normally insulating, can form a conduction path after application of a sufficiently high voltage.<ref name=":0">{{Cite journal|last=Lanza|first=Mario|year=2014|title=A Review on Resistive Switching in High-k Dielectrics: A Nanoscale Point of View Using Conductive Atomic Force Microscope|journal=Materials|volume=7|issue=3|pages=2155–2182|bibcode=2014Mate....7.2155L|doi=10.3390/ma7032155|pmid=28788561|pmc=5453275|doi-access=free}}</ref> The conduction path can arise from different mechanisms, including vacancy or metal defect migration. Once the conduction path is formed, it may be ''reset'' (broken, resulting in high resistance) or ''set'' (re-formed, resulting in lower resistance) by another lower voltage. Many current paths, rather than a single filament, are possibly involved.<ref>{{Cite journal | doi = 10.1063/1.2715002| title = Resistance switching of copper doped MoO[sub x] films for nonvolatile memory applications| journal = Applied Physics Letters| volume = 90| issue = 12| pages = 122104| year = 2007| last1 = Lee | first1 = D. | last2 = Seong | first2 = D. J. | last3 = Jo | first3 = I. | last4 = Xiang | first4 = F.| last5 = Dong | first5 = R.| last6 = Oh | first6 = S. | last7 = Hwang | first7 = H. | bibcode = 2007ApPhL..90l2104L}}</ref> The presence of these current paths in the dielectric can be in situ demonstrated via [[conductive atomic force microscopy]].<ref name=":0" /><ref>{{Cite journal|date=2012-11-05|title=Resistive switching in hafnium dioxide layers: Local phenomenon at grain boundaries|journal=Applied Physics Letters|volume=101|issue=19|pages=193502|doi=10.1063/1.4765342|issn=0003-6951|bibcode=2012ApPhL.101s3502L|last1=Lanza|first1=M.|last2=Bersuker|first2=G.|last3=Porti|first3=M.|last4=Miranda|first4=E.|last5=Nafría|first5=M.|last6=Aymerich|first6=X.|url=http://ddd.uab.cat/record/182947}}</ref><ref>{{Cite journal|last1=Shi|first1=Yuanyuan|last2=Ji|first2=Yanfeng|last3=Hui|first3=Fei|last4=Nafria|first4=Montserrat|last5=Porti|first5=Marc|last6=Bersuker|first6=Gennadi|last7=Lanza|first7=Mario|date=2015-04-01|title=In Situ Demonstration of the Link Between Mechanical Strength and Resistive Switching in Resistive Random-Access Memories|journal=Advanced Electronic Materials|language=en|volume=1|issue=4|pages=n/a|doi=10.1002/aelm.201400058|doi-access=free |s2cid=110305072 |issn=2199-160X}}</ref><ref>{{Cite book|title=Conductive Atomic Force Microscopy: Applications in Nanomaterials|last=Lanza|first=Mario|publisher=Wiley-VCH|year=2017|isbn=978-3-527-34091-0|location=Berlin, Germany|pages=10–30}}</ref>

The low-resistance path can be either localized (filamentary) or homogeneous. Both effects can occur either throughout the entire distance between the electrodes or only in proximity to one of the electrodes. Filamentary and homogenous conduction path switching effects can be distinguished by measuring the area dependence of the low-resistance state.<ref name="aem-journal.com">{{cite web |url=http://www.aem-journal.com |title=Advanced Engineering Materials – Wiley Online Library |publisher=Aem-journal.com |doi=10.1002/(ISSN)1527-2648 |access-date=2014-08-13 |archive-date=2013-04-30 |archive-url=https://web.archive.org/web/20130430021515/http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1527-2648 |url-status=dead }}</ref>

Under certain conditions, the forming operation may be bypassed.<ref name="Chen 2009">{{cite book|last1=Chen|first1=Yu-Sheng|last2=Wu|first2=Tai-Yuan|last3=Tzeng|first3=Pei-Jer|last4=Chen|first4=Pang-Shiu|last5=Lee|first5=H. Y.|last6=Lin|first6=Cha-Hsin|last7=Chen|first7=F.|last8=Tsai|first8=Ming-Jinn|title=2009 International Symposium on VLSI Technology, Systems, and Applications |chapter=Forming-free HfO<sub>2</sub> bipolar RRAM device with improved endurance and high speed operation |date=2009|pages=37–38|doi=10.1109/VTSA.2009.5159281|isbn=978-1-4244-2784-0|s2cid=7590725}}</ref> It is expected that under these conditions, the initial current is already quite high compared to insulating oxide layers. ReRAM cells generally do not require high voltage forming if Cu ions are already present in the dielectric, having already been driven-in by a designed photo-diffusion or annealing process; such cells may also readily return to their initial state.<ref name="Balakrishnan 2006">{{cite book|last1=Balakrishnan|first1=M.|last2=Thermadam|first2=S. C. P.|last3=Mitkova|first3=M.|last4=Kozicki|first4=M. N.|title=2006 7th Annual Non-Volatile Memory Technology Symposium |chapter=A Low Power Non-Volatile Memory Element Based on Copper in Deposited Silicon Oxide |date=2006|pages=104–110|doi=10.1109/NVMT.2006.378887|isbn=978-0-7803-9738-5|s2cid=27573769}}</ref> In the absence of such Cu initially being in the dielectric, the voltage applied directly to the electrolyte has a strong possibility of forming.<ref name="Sills 2014">{{cite book|last1=Sills|first1=S.|last2=Yasuda|first2=S.|last3=Strand|first3=J.|last4=Calderoni|first4=A.|last5=Aratani|first5=K.|last6=Johnson|first6=A.|last7=Ramaswamy|first7=N.|title=2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers |chapter=A copper ReRAM cell for Storage Class Memory applications |date=2014|pages=1–2|doi=10.1109/VLSIT.2014.6894368|isbn=978-1-4799-3332-7|s2cid=9690870}}</ref>

==Operation styles==
For random-access type memories, a 1T1R (one transistor, one resistor) architecture is preferred because the transistor isolates current to cells that are selected from cells that are not. On the other hand, a cross-point architecture is more compact and may enable vertically stacking memory layers, ideal suited for mass-storage devices. However, in the absence of any transistors, isolation must be provided by a "selector" device, such as a [[diode]], in series with the memory element or by the memory element itself. Such isolation capabilities are inferior to the use of transistors if the on/off ratio for the selector is not sufficient, limiting the ability to operate very large arrays in this architecture. Thin film based threshold switch can work as a selector for bipolar and unipolar ReRAM. Threshold switch-based selector was demonstrated for 64 Mb array.<ref>[http://journals.cambridge.org/action/displayAbstract?fromPage=online&aid=7956129&fulltextType=RA&fileId=S1946427400002724 I.V. Karpov, D. Kencke, D. Kau, S. Tang and G. Spadini, MRS Proceedings, Volume 1250, 2010]</ref> The cross-point architecture requires [[BEOL]] compatible two terminal selectors like punch-through diode for bipolar ReRAM<ref>V. S. S. Srinivasan et al., Punchthrough-Diode-Based Bipolar RRAM Selector by Si Epitaxy," Electron Device Letters, IEEE, vol.33, no.10, pp.1396,1398, Oct. 2012 doi: 10.1109/LED.2012.2209394 [https://ieeexplore.ieee.org/document/6286985/]</ref> or PIN diode for unipolar ReRAM.<ref>{{Cite book | doi=10.1109/DRC.2014.6872387| chapter=High performance sub-430°C epitaxial silicon PIN selector for 3D RRAM| title=72nd Device Research Conference| pages=241–242| year=2014| last1=Mandapati| first1=R.| last2=Shrivastava| first2=S.| last3=Das| first3=B.| last4=Sushama| last5=Ostwal| first5=V.| last6=Schulze| first6=J.| last7=Ganguly| first7=U.| isbn=978-1-4799-5406-3| s2cid=31770873}}</ref>

Polarity can be either binary or unary. Bipolar effects cause polarity to reverse when switching from low to high resistance (reset operation) compared to switching high to low (set operation). Unipolar switching leaves polarity unaffected, but uses different voltages.

== Material systems for resistive memory cells ==
Multiple inorganic and organic material systems display thermal or ionic resistive switching effects. These can be grouped into the following categories:<ref name="aem-journal.com"/>

* phase-change chalcogenides such as {{chem|Ge|2|Sb|2|Te|5}} or AgInSbTe
* binary transition metal oxides such as NiO, Ta<sub>2</sub>O<sub>5</sub>, or {{chem|TiO|2}}
* perovskites such as Sr(Zr){{chem|TiO|3}}<ref name="Waser 2007">
{{cite journal|last1=Waser|first1=Rainer|last2=Aono|first2=Masakazu|title=Nanoionics-based resistive switching memories|journal=[[Nature Materials]]|date=2007|volume=6|issue=11|pages=833–840|doi=10.1038/nmat2023|pmid=17972938|language=En|issn=1476-4660|bibcode=2007NatMa...6..833W}}
</ref> or PCMO
* solid-state electrolytes such as GeS, GeSe, {{chem|SiO|''x''}} or {{chem|Cu|2|S}}
* organic charge-transfer complexes such as CuTCNQ
* organic donor–acceptor systems such as Al AIDCN
* two dimensional (layered) insulating materials like hexagonal boron nitride<ref>{{Cite journal|last1=Pan|first1=Chengbin|last2=Ji|first2=Yanfeng|last3=Xiao|first3=Na|last4=Hui|first4=Fei|last5=Tang|first5=Kechao|last6=Guo|first6=Yuzheng|last7=Xie|first7=Xiaoming|last8=Puglisi|first8=Francesco M.|last9=Larcher|first9=Luca|date=2017-01-01|title=Coexistence of Grain-Boundaries-Assisted Bipolar and Threshold Resistive Switching in Multilayer Hexagonal Boron Nitride|journal=Advanced Functional Materials|volume=27|issue=10|language=en|pages=n/a|doi=10.1002/adfm.201604811|hdl=11380/1129421 |s2cid=100500198 |issn=1616-3028|hdl-access=free}}</ref><ref>{{Cite book|last1=Puglisi|first1=F. M.|last2=Larcher|first2=L.|last3=Pan|first3=C.|last4=Xiao|first4=N.|last5=Shi|first5=Y.|last6=Hui|first6=F.|last7=Lanza|first7=M.|title=2016 IEEE International Electron Devices Meeting (IEDM) |chapter=2D h-BN based RRAM devices |date=2016-12-01|pages=34.8.1–34.8.4|doi=10.1109/IEDM.2016.7838544|hdl=11380/1129447 |isbn=978-1-5090-3902-9|s2cid=28059875}}</ref>

== RRAM Based on Perovskite ==
ABO3-type inorganic perovskite materials such as BaTiO3, SrRuO3, SrZrO3, and SrTiO3 have attracted extensive research interest as the storage media in memristors due to their remarkable resistance switching effects and various functionalities such as ferroelectric, dielectric, and semiconducting physical characteristics.<ref>S.C. Lee, Q. Hu, Y.-J. Baek, Y.J. Choi, C.J. Kang, H.H. Lee, T.-S. Yoon, Analog and bipolar resistive switching in pn junction of n-type ZnO nanowires on p-type Si substrate, J. Appl. Phys. 114 (2013) 1–5.</ref> However, the fragile nature and high cost of the fabrication process limit the wide applications of these ABO3-type inorganic perovskite materials for memristors. Recently, ABX3-type lead trihalide perovskites have received extensive research interest for using in optoelectronic devices such as photovoltaics, photodetectors, and light-emitting diodes (LED).<ref>D.V. Talapin, J.-S. Lee, M.V. Kovalenko, E.V. Shevchenko, Prospects of colloidal nanocrystals for electronic and optoelectronic applications, Chem. Rev. 110 (2009) 389–458.</ref> In these structures, A is a monovalent organic or inorganic (MA:CH3NH3+, FA: CH(NH2)2+, Cs+, Rb+), B is a divalent metal cation (Pb2+, Sn2+), and X is a halide anion (Cl, Br, I). The A cation resides at the eight corners of the cubic unit and the B cation locates at the center of the octahedral cluster [BX6]4 to form the 3D perovskite structure. According to the different A-site cations, these structures can be classified into organic-inorganic hybrid perovskites and all-inorganic perovskites.<ref>Li, B., Hui, W., Ran, X., Xia, Y., Xia, F., Chao, L., ... & Huang, W. (2019). Metal halide perovskites for resistive switching memory devices and artificial synapses. Journal of Materials Chemistry C, 7(25), 7476-7493.</ref> Moreover, this type of perovskite can be obtained readily by solution-processable methods at a low cost.[16] Nevertheless, owing to the inclusion of organic cations, it was commonly found that the intrinsic thermal instability of methylammonium (MA) and formamidinium (FA) lead trihalide perovskites was really a bottleneck for the development of hybrid perovskite-based electronic devices.<ref>Kojima, A.; Teshima, K.; Shirai, Y.; Miyasaka, T. Organometal Halide Perovskites as Visible-light Sensitizers for Photovoltaic Cells. J. Am. Chem. Soc. 2009, 131, 6050−6051.</ref> Therefore, to resolve this issue, the organic cations must be substituted by other ions such as Cesium (Cs) cations. Interestingly, there are some reports of Cesium/Cesium hybridization solar cells that give us many new clues for the improved stability of all-inorganic perovskite-based electronic devices. More and more publications demonstrate that inorganic Cs cation-based all-inorganic perovskites could be both structurally and thermally stable above 100&nbsp;°C, while hybrid perovskites thermally degraded to lead iodide above 85&nbsp;°C.<ref>Gratzel, M. The Light and Shade of Perovskite Solar Cells. ̈ Nat. Mater. 2014, 13, 838−842.</ref> Therefore, it has been implied that all-inorganic perovskites could be excellent candidates for the fabrication of stable and highly efficient resistive switching memory devices using a low-cost process. Considering the CsPbX3 perovskites are usually prepared by solution method, point defects such as vacancies, interstitials, and antisites are possible in the crystals. These defects are essential for the defect drift-dominated resistive switching memory. Thus, these CsPbX3 perovskites have great potential for application in memory devices.<ref>Liu, D., Lin, Q., Zang, Z., Wang, M., Wangyang, P., Tang, X., ... & Hu, W. (2017). Flexible all-inorganic perovskite CsPbBr3 nonvolatile memory device. ACS Applied Materials & Interfaces, 9(7), 6171-6176.</ref> Given the fact that resistance switching in halide perovskite-based RRAM is caused by migrations of halide atoms through vacancies, the migration characteristics of a vacancy within the RRAM are one of the most important material properties of the RRAM determining the key features of it. However, despite its importance, the activation energy of halide vacancy in RRAMs has been no serious study topic at all. Obviously, a small activation barrier of halide vacancy expected in halide perovskite-based RRAMs plays a central role in allowing this RRAM to operate at low voltages and thus at low power consumption mode.<ref>Hur, J. H. (2020). First principles study of oxygen vacancy activation energy barrier in zirconia-based resistive memory. Scientific reports, 10(1), 1-8.</ref>

== Demonstrations ==
Papers at the IEDM Conference in 2007 suggested for the first time that ReRAM exhibits lower programming currents than [[Phase-change memory|PRAM]] or [[Magnetoresistive RAM|MRAM]] without sacrificing programming performance, retention or endurance.<ref>{{Cite book | doi = 10.1109/IEDM.2007.4419060| chapter = Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3 V| title = 2007 IEEE International Electron Devices Meeting| pages = 767–770| year = 2007| last1 = Tsunoda | first1 = K.| last2 = Kinoshita | first2 = K.| last3 = Noshiro | first3 = H.| last4 = Yamazaki | first4 = Y.| last5 = Iizuka | first5 = T.| last6 = Ito | first6 = Y.| last7 = Takahashi | first7 = A.| last8 = Okano | first8 = A.| last9 = Sato | first9 = Y.| last10 = Fukano | first10 = T.| last11 = Aoki | first11 = M.| last12 = Sugiyama | first12 = Y.| isbn = 978-1-4244-1507-6| s2cid = 40684267}}</ref> Some commonly cited ReRAM systems are described further below.

===Gb-scale ReRAM===
A 32 Gb 24&nbsp;nm ReRAM was published by SanDisk in 2013 without many details other than a non-transistor access device, and metal oxide RRAM composition.<ref>T. Liu et al., ISSCC 2013.</ref>

A 16 Gb 27&nbsp;nm ReRAM (actually CBRAM) was published by Micron and Sony in 2014. Instead of a 1T1R structure for one bit, two bits were split between two transistors and bottom electrodes while sharing the top portions (electrolyte, copper reservoir, and top electrode).<ref>J. Zahurak et al., IEDM 2014.</ref>

===HfO<sub>2</sub>-based ReRAM===
At IEDM 2008, the first high-performance ReRAM technology was demonstrated by [[ITRI]] using HfO<sub>2</sub> with a Ti buffer layer, showing switching times less than 10&nbsp;ns and currents less than 30μA. At IEDM 2010, ITRI again broke the speed record, showing <0.3 ns switching time, while also showing process and operation improvements to allow yield up to 100% and endurance up to 10 billion cycles.<ref>H-Y. Lee et al., IEDM 2010.</ref> [[IMEC]] presented updates of their ReRAM program at the 2012 Symposia on VLSI Technology and Circuits, including a solution with a 500 nA operating current.<ref>L. Goux ''et al.'', 2012 Symp. on VLSI Tech. Dig. of Tech. Papers, 159 (2012).</ref>

ITRI had focused on the Ti/HfO<sub>2</sub> system since its first publication in 2008. ITRI's patent 8362454 has since been sold to TSMC;<ref>{{Cite web|url=https://assignment.uspto.gov/patent/index.html#/patent/search/resultAbstract?id=8362454&type=patNum|title = United States Patent and Trademark Office}}</ref> the number of prior licensees is unknown. On the other hand, IMEC focused mainly on Hf/HfO<sub>2</sub>.<ref>Y. Y. Chen ''et al.'', IEDM 2013.</ref> Winbond had done more recent work toward advancing and commercializing the HfO<sub>2</sub>-based ReRAM.<ref>C-H. Ho ''et al.'', 2016 Symposium on VLSI Technology.</ref>

A Chinese group presented the largest 1T1R RRAM to date, a 64 Mb chip on a 130&nbsp;nm process.<ref>X. Han et al., CICC 2017.</ref> 10 million cycles were achieved, as well as an extrapolated retention of 10 yrs at 75 C.

===Panasonic===
Panasonic revealed its TaO<sub>x</sub>-based ReRAM at IEDM 2008.<ref>{{cite book|last1=Wei|first1=Z.|last2=Kanzawa|first2=Y.|last3=Arita|first3=K.|last4=Katoh|first4=Y.|last5=Kawai|first5=K.|last6=Muraoka|first6=S.|last7=Mitani|first7=S.|last8=Fujii|first8=S.|last9=Katayama|first9=K.|last10=Iijima|first10=M.|last11=Mikawa|first11=T.|last12=Ninomiya|first12=T.|last13=Miyanaga|first13=R.|last14=Kawashima|first14=Y.|last15=Tsuji|first15=K.|last16=Himeno|first16=A.|last17=Okada|first17=T.|last18=Azuma|first18=R.|last19=Shimakawa|first19=K.|last20=Sugaya|first20=H.|last21=Takagi|first21=T.|last22=Yasuhara|first22=R.|last23=Horiba|first23=K.|last24=Kumigashira|first24=H.|last25=Oshima|first25=M.|title=2008 IEEE International Electron Devices Meeting |chapter=Highly reliable TaOx ReRAM and direct evidence of redox reaction mechanism |date=2008|pages=1–4|doi=10.1109/IEDM.2008.4796676|isbn=978-1-4244-2377-4|s2cid=30862029}}</ref> A key requirement was the need for a high work function metal such as Pt or Ir to interface with the TaO<sub>x</sub> layer. The change of O content results in resistance change as well as Schottky barrier change. More recently, a Ta<sub>2</sub>O<sub>5</sub>/TaO<sub>x</sub> layer was implemented, which still requires the high work function metal to interface with Ta<sub>2</sub>O<sub>5</sub>.<ref>Y. Hayakawa ''et al.'', 2015 Symposium on VLSI Technology.</ref> This system has been associated with high endurance demonstration (trillion cycles),<ref>M-J. Lee ''et al.'', Nat. Mat. 10, 625 (2011).</ref> but products are specified at 100K cycles.<ref>[http://www.mouser.tw/new/panasonic/panasonic-mn101l-reram/ Panasonic ReRAM-based product description]</ref> Filament diameters as large as ~100&nbsp;nm have been observed.<ref>Z. Wei, IMW 2013.</ref> Panasonic released a 4Mb part with Fujitsu,<ref>{{Cite web|url=https://www.fujitsu.com/jp/group/fsl/en/resources/news/press-releases/2016/1026.html|title=Fujitsu Semiconductor Launches World's Largest Density 4 Mbit ReRAM Product for Mass Production : FUJITSU SEMICONDUCTOR|website=www.fujitsu.com}}</ref> and is developing 40&nbsp;nm embedded memory with UMC.<ref>{{Cite web|url=https://www.businesswire.com/news/home/20170206005452/en/Panasonic-and-United-Microelectronics-Corporation-Agreed-to-Develop-Mass-Production-Process-for-Next-Generation-ReRAM|title=Panasonic and United Microelectronics Corporation Agreed to Develop Mass Production Process for Next Generation ReRAM|date=February 6, 2017|website=www.businesswire.com}}</ref>

===HP memristor===
On 30 April 2008, HP announced that they had discovered the memristor, originally envisioned as a missing 4th fundamental circuit element by Chua in 1971. On 8 July they announced they would begin prototyping ReRAM using their memristors.<ref>[http://www.eetimes.com/news/design/rss/showArticle.jhtml?articleID=208803176&cid=RSSfeed_eetimes_designRSS EETimes.com – Memristors ready for prime time]</ref> HP first demonstrated its memristor using TiO<sub>x</sub>,<ref>D. B. Strukov, Nature 453, 80 (2008).</ref> but later migrated to TaO<sub>x</sub>,<ref>J. P. Strachan ''et al.'', IEEE Trans. Elec. Dev. 60, 2194 (2013).</ref> possibly due to improved stability.<ref>{{Cite web |url=http://www.jos.ac.cn/bdtxbcn/ch/reader/create_pdf.aspx?file_no=15090022&year_id=2016&quarter_id=6&falg=1 |title=Comparison of Pt/TiOx/Pt vs Pt/TaOx/TaOy/Pt |access-date=2017-02-13 |archive-url=https://web.archive.org/web/20170213170042/http://www.jos.ac.cn/bdtxbcn/ch/reader/create_pdf.aspx?file_no=15090022&year_id=2016&quarter_id=6&falg=1 |archive-date=2017-02-13 |url-status=dead }}</ref> The TaO<sub>x</sub>-based device has some material similarity to Panasonic's ReRAM, but the operation characteristics are different. The Hf/HfOx system was similarly studied.<ref>S. Kumar ''et al.'', ACS Nano 10, 11205 (2016).</ref>

===Adesto Technologies===
The [[Adesto Technologies]] CBRAM is based on filaments generated from the electrode metal rather than oxygen vacancies. The original material system was Ag/GeS<sub>2</sub><ref>J. R. Jameson ''et al.'', IEDM 2013.</ref> but eventually migrated to ZrTe/Al<sub>2</sub>O<sub>3</sub>.<ref>D. Kanter, "Adesto Targets IoT Using CBRAM, The Linley Group Microprocessor Report, Feb 2016.</ref> The tellurium filament achieved better stability as compared to silver. Adesto has targeted the ultralow power memory for Internet-of-Things (IoT) applications. Adesto has released products manufactured at Altis foundry<ref name="auto">{{Cite web|url=https://www.dialog-semiconductor.com/|title=Dialog Semiconductor: Advancing the connected world through technology &#124; Dialog|website=www.dialog-semiconductor.com}}</ref> and entered into a 45&nbsp;nm foundry agreement with [[Tower Semiconductor|TowerJazz]]/[[Panasonic]].<ref name="auto"/>

===Weebit Nano===
[[Weebit Nano]] has been working with [[CEA-Leti: Laboratoire d'électronique des technologies de l'information|CEA-Leti]], one of the largest nanotechnology research institutes in Europe to further ReRAM technology. Beginning in November, 2017, the company has demonstrated the manufacturability in 40&nbsp;nm SiOx ReRAM cells,<ref>{{Cite web|url=https://www.rram-info.com/weebit-announced-working-40nm-siox-rram-cell-samples|title=Weebit announced working 40nm SiOx RRAM cell samples &#124; RRAM-Info|website=www.rram-info.com}}</ref> followed by demonstrations of working arrays in 2018<ref>{{Cite web|url=https://www.eenewseurope.com/news/siox-reram-reaches-1mbit-milestone-0|title=SiOx ReRAM reaches 1Mbit milestone|date=July 4, 2018|website=eeNews Europe}}</ref> and discrete components in 2020.<ref>{{Cite web|url=https://www.rram-info.com/weebit-nano-packaged-its-rram-chips-first-time|title=Weebit Nano packaged its RRAM chips for the first time &#124; RRAM-Info|website=www.rram-info.com}}</ref> In July 2021, the company taped out its first embedded ReRAM modules.<ref>{{Cite web|url=https://www.rram-info.com/weebit-nano-completed-its-first-embedded-rram-module-design-and-tape-out|title=Weebit Nano completed its first embedded RRAM module design and tape-out &#124; RRAM-Info|website=www.rram-info.com}}</ref> In September 2021, Weebit, together with Leti, produced, tested and characterized a 1 Mb ReRAM array, using a 28&nbsp;nm FDSOI process on 300mm wafers.<ref>{{Cite web|url=https://www.electronicsweekly.com/news/business/weebit-nano-reram-scaled-28nm-2021-10/|title=Weebit Nano ReRAM scaled to 28nm|website=www.electronicsweekly.com|date=October 2021}}</ref>

===Crossbar===
[[Crossbar (computer hardware manufacturer)|Crossbar]] implements an Ag filament in amorphous Si along with a threshold switching system to achieve a diode+ReRAM.<ref>Y. Dong ''et al.'', Nano. Lett. 8, 386 (2008).</ref><ref>S. H. Jo ''et al.'', ASPDAC 2015.</ref> Their system includes the use of a transistor in 1T1R or 1TNR architecture. Crossbar started producing samples at [[Semiconductor Manufacturing International Corporation|SMIC]] on the 40&nbsp;nm process in 2017.<ref>[http://www.eetimes.com/document.asp?doc_id=1331173 Crossbar sampling 40nm at SMIC]</ref> The Ag filament diameter has been visualized on the scale of tens of nanometers.<ref>{{Cite web|url=https://site.ieee.org/sfbanano/files/2013/06/Lu_NVMT_2013.pdf|title=TEMs of Ag filament}}</ref>

=== IntrinSic ===
A UK based that company plans to create cells using common silicon-oxide.<ref>{{Cite web |title=Intrinsic AI Solutions |url=https://www.intrinsicsemi.com/ |access-date=2023-11-03 |website=Intrinsic AI Solutions |language=en-GB}}</ref><ref>{{Cite web |last=Mellor |first=Chris |date=2023-03-16 |title=Taking a look at the ReRAM state of play |url=https://blocksandfiles.com/2023/03/16/the-state-of-reram-play/ |access-date=2023-11-03 |website=Blocks and Files |language=en-US}}</ref>

===Programmable metallization cell===
{{Main|Programmable metallization cell}}
[[Infineon Technologies]] calls it conductive-bridging RAM(CBRAM), NEC has a variant called "Nanobridge" and Sony calls their version "electrolytic memory". New research suggests CBRAM can be [[3D printed]].<ref>[http://aip.scitation.org/doi/full/10.1063/1.4978664?dm_i=3Q4Y%2C6QBI%2CJ2QY2%2CNJEU%2C1& Fully inkjet printed flexible resistive memory] -[[American Institute of Physics|AIP]] Scitation</ref><ref>[http://www.engineering.com/DesignerEdge/DesignerEdgeArticles/ArticleID/14672/Mass-Producing-Printed-Electronics.aspx Mass Producing Printed Electronics] -Engineering.com</ref>

'''<big>Quantum dot resistive memory device</big>'''

[[Quantum dot]] based non-volatile resistive memory device with a switching speed of 10 ns and ON/OFF ratio of 10 000. The device showed excellent endurance characteristics for 100 000 switching cycles. Retention tests showed good stability and the devices are reproducible. Memory operating mechanism is proposed based on charge trapping in quantum dots with AlOx acting as barrier. This mechanism is supported by marked variation in capacitance value in ON and OFF states.<ref>{{Cite journal|last1=Kannan|first1=V|last2=Rhee J K|date=6 October 2011|title=Ultra-fast switching in solution processed quantum dot based non-volatile resistive memory|url=https://aip.scitation.org/doi/10.1063/1.3647629|journal=Applied Physics Letters|volume=99|issue=14|pages=143504|doi=10.1063/1.3647629|bibcode=2011ApPhL..99n3504K|via=AIP|url-access=subscription}}</ref>

== ReRam test boards ==
* Panasonic AM13L-STK2 : MN101LR05D 8-bit MCU with built in ReRAM for evaluation, {{nowrap|USB 2.0}} connector

== Future applications ==
Compared to PRAM, ReRAM operates at a faster timescale (switching time can be less than 10&nbsp;ns), while compared to MRAM, it has a simpler, smaller cell structure (less than 8F² MIM stack). A vertical 1D1R (one diode, one resistive switching device) integration can be used for crossbar memory structure to reduce the unit cell size to 4F² (F is the feature dimension).<ref>{{Cite journal | doi = 10.1088/0022-3727/46/14/145101 | title = Vertically integrated ZnO-Based 1D1R structure for resistive switching| journal = Journal of Physics D: Applied Physics| volume = 46| issue = 14| pages = 145101| year = 2013| last1 = Zhang| first1 = Yang| last2 = Duan| first2 = Ziqing| last3 = Li| first3 = Rui| last4 = Ku| first4 = Chieh-Jen| last5 = Reyes| first5 = Pavel I| last6 = Ashrafi| first6 = Almamun| last7 = Zhong| first7 = Jian| last8 = Lu| first8 = Yicheng| bibcode = 2013JPhD...46n5101Z| s2cid = 121110610}}</ref> Compared to flash memory and racetrack memory, a lower voltage is sufficient, and hence it can be used in low-power applications.

ITRI has shown that ReRAM is scalable below 30&nbsp;nm.<ref>{{cite book|last1=Chen|first1=Y. S.|last2=Lee|first2=H. Y.|last3=Chen|first3=P. S.|last4=Gu|first4=P. Y.|last5=Chen|first5=C. W.|last6=Lin|first6=W. P.|last7=Liu|first7=W. H.|last8=Hsu|first8=Y. Y.|last9=Sheu|first9=S. S.|last10=Chiang|first10=P. C.|last11=Chen|first11=W. S.|last12=Chen|first12=F. T.|last13=Lien|first13=C. H.|last14=Tsai|first14=M. J.|title=2009 IEEE International Electron Devices Meeting (IEDM) |chapter=Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity |date=2009|pages=1–4|doi=10.1109/IEDM.2009.5424411|isbn=978-1-4244-5639-0|s2cid=36391893}}</ref> The motion of oxygen atoms is a key phenomenon for oxide-based ReRAM;<ref>New Non-Volatile Memory Workshop 2008, Hsinchu, Taiwan.</ref> one study indicated that oxygen motion may take place in regions as small as 2&nbsp;nm.<ref>{{Cite journal | doi = 10.1038/nmat2136 | pmid = 18311143| title = Nanoscale control of an interfacial metal–insulator transition at room temperature| journal = Nature Materials| volume = 7| issue = 4| pages = 298–302| year = 2008| last1 = Cen| first1 = C.| last2 = Thiel| first2 = S.| last3 = Hammerl| first3 = G.| last4 = Schneider| first4 = C. W.| last5 = Andersen| first5 = K. E.| last6 = Hellberg| first6 = C. S.| last7 = Mannhart| first7 = J.| last8 = Levy| first8 = J.| bibcode = 2008NatMa...7..298C| url = https://opus.bibliothek.uni-augsburg.de/opus4/frontdoor/index/index/docId/61913}}</ref> It is believed that if a filament is responsible, it would not exhibit direct scaling with cell size.<ref>I. G. Baek et al., IEDM 2004.</ref> Instead, the current compliance limit (set by an outside resistor, for example) could define the current-carrying capacity of the filament.<ref>{{Cite journal | doi = 10.1149/1.2750450 | title = Bistable Resistive Switching in Al2O3 Memory Thin Films| journal = Journal of the Electrochemical Society| volume = 154| issue = 9| pages = G189| year = 2007| last1 = Lin| first1 = Chih-Yang| last2 = Wu| first2 = Chen-Yu| last3 = Wu| first3 = Chung-Yi| last4 = Hu| first4 = Chenming| last5 = Tseng| first5 = Tseung-Yuen| bibcode = 2007JElS..154G.189L}}</ref>

A significant hurdle to realizing the potential of ReRAM is the sneak path problem that occurs in larger passive arrays. In 2010, [[complementary resistive switching]] (CRS) was introduced as a possible solution to sneak-path current interference.<ref>{{Cite journal | doi = 10.1038/nmat2748 | pmid = 20400954| title = Complementary resistive switches for passive nanocrossbar memories| journal = Nature Materials| volume = 9| issue = 5| pages = 403–6| year = 2010| last1 = Linn| first1 = Eike| last2 = Rosezin| first2 = Roland| last3 = Kügeler| first3 = Carsten| last4 = Waser| first4 = Rainer| bibcode = 2010NatMa...9..403L}}</ref> In the CRS approach, the information storing states are pairs of high- and low-resistance states (HRS/LRS and LRS/HRS) so that the overall resistance is always high, allowing larger passive crossbar arrays.

A drawback to the initial CRS solution is the requirement for switching endurance caused by conventional destructive readout based on current measurements. A new approach for a nondestructive readout based on capacity measurement potentially lowers the requirements for both material endurance and power consumption.<ref>{{Cite journal | doi = 10.1088/0957-4484/22/39/395203 | pmid = 21891857| title = Capacity based nondestructive readout for complementary resistive switches| journal = Nanotechnology| volume = 22| issue = 39| pages = 395203| year = 2011| last1 = Tappertzhofen| first1 = S| last2 = Linn| first2 = E| last3 = Nielen| first3 = L| last4 = Rosezin| first4 = R| last5 = Lentz| first5 = F| last6 = Bruchhaus| first6 = R| last7 = Valov| first7 = I| last8 = Böttger| first8 = U| last9 = Waser| first9 = R| bibcode = 2011Nanot..22M5203T| s2cid = 12305490}}</ref> Bi-layer structure is used to produce the nonlinearity in LRS to avoid the sneak path problem.<ref>{{Cite journal | doi = 10.1063/1.3693392 | title = Engineering nonlinearity into memristors for passive crossbar applications| journal = Applied Physics Letters| volume = 100| issue = 11| pages = 113501| year = 2012| last1 = Joshua Yang| first1 = J.| last2 = Zhang| first2 = M.-X.| last3 = Pickett| first3 = Matthew D.| last4 = Miao| first4 = Feng| last5 = Paul Strachan| first5 = John| last6 = Li| first6 = Wen-Di| last7 = Yi| first7 = Wei| last8 = Ohlberg| first8 = Douglas A. A.| last9 = Joon Choi| first9 = Byung| last10 = Wu| first10 = Wei| last11 = Nickel| first11 = Janice H.| last12 = Medeiros-Ribeiro| first12 = Gilberto| last13 = Stanley Williams| first13 = R.| bibcode = 2012ApPhL.100k3501J| doi-access = free}}</ref> A single-layer device exhibiting a strong nonlinear conduction in LRS was reported.<ref>{{Cite journal | doi = 10.1088/0957-4484/23/45/455201 | pmid = 23064085| title = Electrically tailored resistance switching in silicon oxide| journal = Nanotechnology| volume = 23| issue = 45| pages = 455201| year = 2012| last1 = Mehonic| first1 = Adnan| last2 = Cueff| first2 = Sébastien| last3 = Wojdak| first3 = Maciej| last4 = Hudziak| first4 = Stephen| last5 = Labbé| first5 = Christophe| last6 = Rizk| first6 = Richard| last7 = Kenyon| first7 = Anthony J| bibcode = 2012Nanot..23S5201M| s2cid = 12528923}}</ref> Another bi-layer structure was introduced for bipolar ReRAM to improve the HRS and stability.<ref>{{Cite journal | doi = 10.1007/s11664-012-2045-2 | title = FeZnO-Based Resistive Switching Devices| journal = Journal of Electronic Materials| volume = 41| issue = 10| pages = 2880| year = 2012| last1 = Zhang| first1 = Yang| last2 = Duan| first2 = Ziqing| last3 = Li| first3 = Rui| last4 = Ku| first4 = Chieh-Jen| last5 = Reyes| first5 = Pavel| last6 = Ashrafi| first6 = Almamun| last7 = Lu| first7 = Yicheng| bibcode = 2012JEMat..41.2880Z| s2cid = 95921756}}</ref>

Another solution to the sneak current issue is to perform ''read'' and ''reset'' operations in parallel across an entire row of cells, while using ''set'' on selected cells.<ref>{{cite journal|last1=Yoon|first1=Hong Sik|last2=Baek|first2=In-Gyu|last3=Zhao|first3=Jinshi|last4=Sim|first4=Hyunjun|last5=Park|first5=Min Young|last6=Lee|first6=Hansin|last7=Oh|first7=Gyu-Hwan|last8=Shin|first8=Jong Chan|last9=Yeo|first9=In-Seok|last10=Chung|first10=U.-In|title=Vertical cross-point resistance change memory for ultra-high density non-volatile memory applications|journal=2009 Symposium on VLSI Technology|date=2009|pages=26–27|url=https://ieeexplore.ieee.org/document/5200621}}</ref> In this case, for a 3D-ReRAM 1TNR array, with a column of ''N'' ReRAM cells situated above a select transistor, only the intrinsic nonlinearity of the HRS is required to be sufficiently large, since the number of vertical levels ''N'' is limited (e.g., ''N''&nbsp;=&nbsp;8–32), and this has been shown possible for a low-current ReRAM system.<ref>{{cite journal|last1=Chen|first1=F. T.|last2=Chen|first2=Y. S.|last3=Wu|first3=T. Y.|last4=Ku|first4=T. K.|title=Write Scheme Allowing Reduced LRS Nonlinearity Requirement in a 3D-RRAM Array With Selector-Less 1TNR Architecture|journal=[[IEEE Electron Device Letters]]|date=2014|volume=35|issue=2|pages=223–225|doi=10.1109/LED.2013.2294809|issn=0741-3106|bibcode=2014IEDL...35..223C|s2cid=1126533}}</ref>

Modeling of 2D and 3D caches designed with ReRAM and other non-volatile random access memories such as [[Magnetoresistive random-access memory|MRAM]] and [[Phase-change memory|PCM]] can be done using DESTINY<ref>Poremba et al., "[https://www.academia.edu/9045143/DESTINY_A_Tool_for_Modeling_Emerging_3D_NVM_and_eDRAM_caches DESTINY: A Tool for Modeling Emerging 3D NVM and eDRAM caches]", DATE, 2015.</ref> tool.

==Proposed role in artificial intelligence applications==
The increasing computational demands necessary for many improvements in [[Artificial Intelligence|artificial intelligence]] have led many to speculate that ReRAM implementations could be extremely useful hardware for running [[Artificial Intelligence|artificial intelligence]] and [[Machine Learning|machine learning]] applications.<ref>{{cite journal |last1=Prezioso |first1=M. |editor1-first=Ferechteh H |editor1-last=Teherani |editor2-first=David C |editor2-last=Look |editor3-first=David J |editor3-last=Rogers |display-authors=etal |title=RRAM-based Hardware Implementation of Artificial Neural Networks: Progress Updates and Challenges Ahead |journal=SPIE Annual Review |series=Oxide-based Materials and Devices VII |date=2016 |volume=9749 |page=974918 |doi=10.1117/12.2235089 |bibcode=2016SPIE.9749E..18P |s2cid=20633281 |url=https://web.ece.ucsb.edu/~strukov/papers/2016/SPIEannreview2016.pdf |access-date=June 13, 2021}}</ref>

Researchers at School of Engineering of Stanford University have built up a RRAM that "does the AI processing within the memory itself, thereby eliminating the separation between the compute and memory units." It is twice as energy efficient as state-of-the-art.<ref>{{cite web|url=https://news.stanford.edu/2022/08/18/new-chip-ramps-ai-computing-efficiency/|title=Stanford engineers present new chip that ramps up AI computing efficiency|date=August 18, 2022}}</ref>

==References==
{{Reflist|30em}}

{{emerging technologies|topics=yes|infocom=yes}}

[[Category:Solid-state computer storage media]]
[[Category:Computer memory]]
[[Category:Non-volatile random-access memory]]
[[Category:Types of RAM]]