View source for Reduced instruction set computer

{{short description|Processor executing one instruction in minimal clock cycles}}
{{Redirect|RISC}}
{{Use dmy dates|date=August 2016}}
{{Use American English|date=August 2023}}

[[File:KL Sun UltraSparc.jpg|thumb|The [[Sun Microsystems]] UltraSPARC processor is a type of RISC [[microprocessor]].]]

In [[electronics]] and [[computer science]], a '''reduced instruction set computer''' ('''RISC''', pronounced "risk") is a [[computer architecture]] designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a [[complex instruction set computer]] (CISC), a RISC computer might require more machine code in order to accomplish a task because the individual instructions perform simpler operations. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular by implementing an [[instruction pipeline]], which may be simpler to achieve given simpler instructions.<ref>{{cite web |url=https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/pipelining/index.html |title=Pipelining |work=RISC Architecture |first1=Crystal |last1=Chen |first2=Greg |last2=Novick |first3=Kirk |last3=Shimano}}</ref>

The key operational concept of the RISC computer is that each instruction performs only one function (e.g. copy a value from memory to a register). The RISC computer usually has many (16 or 32) high-speed, general-purpose registers with a [[load–store architecture]] in which the code for the register-register instructions (for performing arithmetic and tests) is separate from the instructions that access the main memory of the computer. The design of the CPU allows RISC computers few simple [[addressing mode]]s<ref name=Flynn54 >{{cite book |title=Computer Architecture: Pipelined and Parallel Processor Design |author-link=Michael J. Flynn |first=Michael J. |last=Flynn |year=1995 |isbn=0867202041 |pages=54–56|publisher=Jones & Bartlett Learning }}</ref> and predictable instruction times that simplify design of the system as a whole.

The conceptual developments of the RISC computer architecture began with the [[IBM 801]] project in the late 1970s, but these were not immediately put into use. Designers in California picked up the 801 concepts in two seminal projects, [[Stanford MIPS]] and [[Berkeley RISC]]. These were commercialized in the 1980s as the [[MIPS architecture|MIPS]] and [[SPARC]] systems. [[IBM]] eventually produced RISC designs based on further work on the 801 concept, the [[IBM POWER architecture]], [[PowerPC]], and [[Power ISA]]. As the projects matured, many similar designs, produced in the mid-to-late 1980s and early 1990s, such as [[ARM architecture family|ARM]], [[PA-RISC]], and [[DEC Alpha|Alpha]], created central processing units that increased the commercial utility of the [[Unix]] [[workstation]] and of [[embedded processor]]s in the [[laser printer]], the [[router (computing)|router]], and similar products.

In the [[minicomputer]] market, companies that included [[Celerity Computing]], [[Pyramid Technology]], and [[Ridge Computers]] began offering systems designed according to RISC or RISC-like principles in the early 1980s.<ref name="computer-sep1985"/><ref name="aletanpaper"/><ref name="byte-nov1984"/><ref name="pbdla-histoire"/><ref name="em-sep1987-p59"/> Few of these designs began by using RISC [[microprocessor]]s.

The varieties of RISC processor design include the [[ARC (processor)|ARC]] processor, the DEC Alpha, the [[AMD Am29000]], the ARM architecture, the [[Atmel AVR]], [[Blackfin]], [[Intel i860]], [[Intel i960]], [[LoongArch]], [[Motorola 88000]], the MIPS architecture, PA-RISC, Power ISA, [[RISC-V]], [[SuperH]], and SPARC. RISC processors are used in [[supercomputer]]s, such as the [[Fugaku (supercomputer)|Fugaku]].<ref>{{Cite web|url=https://www.riken.jp/en/news_pubs/news/2020/20200623_1//|title=Japan's Fugaku gains title as world's fastest supercomputer|website=RIKEN|access-date=24 June 2020}}</ref>

==History and development==
A number of systems, going back to the 1960s, have been credited as the first RISC architecture, partly based on their use of the [[load–store]] approach.<ref name=Fisher55 >{{cite book |title=Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools |url=https://archive.org/details/embeddedcomputin00fish_183 |url-access=limited |first1=Joseph A. |last1=Fisher |first2=Paolo |last2=Faraboschi |first3=Cliff |last3=Young |year=2005 |isbn=1558607668 |page=[https://archive.org/details/embeddedcomputin00fish_183/page/n91 55]|publisher=Elsevier }}</ref> The term RISC was coined by [[David Patterson (computer scientist)|David Patterson]] of the [[Berkeley RISC]] project, although somewhat similar concepts had appeared before.<ref name="coinrisk">{{cite book |last=Reilly |first=Edwin D. |url=https://archive.org/details/milestonesincomp0000reil_m9h9 |title=Milestones in computer science and information technology |publisher=Greenwood Publishing |year=2003 |isbn=1-57356-521-0 |pages=[https://archive.org/details/milestonesincomp0000reil_m9h9/page/50 50] |url-access=registration}}</ref>

The [[CDC 6600]] designed by [[Seymour Cray]] in 1964 used a load–store architecture with only two [[addressing mode]]s (register+register, and register+immediate constant) and 74 operation codes, with the basic clock cycle being 10 times faster than the memory access time.<ref>{{cite book |first=Ralph |last=Grishman |title=Assembly Language Programming for the Control Data 6000 Series and the Cyber 70 Series |oclc=425963232 |publisher=Algorithmics Press |year=1974 |pages=12}}</ref> Partly due to the optimized load–store architecture of the CDC 6600, [[Jack Dongarra]] says that it can be considered a forerunner of modern RISC systems, although a number of other technical barriers needed to be overcome for the development of a modern RISC system.<ref>{{cite book |first=Jack J. |last=Dongarra |display-authors=etal|title=Numerical Linear Algebra on High-Performance Computers |year=1987 |isbn=0-89871-428-1 |pages=[https://archive.org/details/numericallineara00dong_316/page/n24 6] |url=https://archive.org/details/numericallineara00dong_316|url-access=limited}}</ref>

===IBM 801===


[[Michael J. Flynn]] views the first RISC system as the [[IBM 801]] design,<ref name=Flynn54 /> begun in 1975 by [[John Cocke (computer scientist)|John Cocke]] and completed in 1980. The 801 developed out of an effort to build a 24-bit high-speed processor to use as the basis for a digital [[telephone switch]]. To reach their goal of switching 1 million calls per hour (300 per second) they calculated that the CPU required performance on the order of 12 million [[instructions per second]] (MIPS),<ref name=evolution>{{Cite journal
 |last1=Cocke |first1=John
 |last2=Markstein |first2=Victoria
 |doi=10.1147/rd.341.0004
 |url=https://www.cis.upenn.edu/~milom/cis501-Fall11/papers/cocke-RISC.pdf
 |title=The evolution of RISC technology at IBM
 |journal=IBM Journal of Research and Development
 |volume=34 |issue=1
 |pages=4–11
 |date=January 1990
}}</ref> compared to their fastest mainframe machine of the time, the [[IBM System/370|370/168]], which performed at 3.5 MIPS.<ref>{{cite tech report |title= IBM System/370 System Summary |date= January 1987 |publisher=IBM |url=http://www.beagle-ears.com/lars/engineer/comphist/model360.htm}}</ref>

The design was based on a study of IBM's extensive collection of statistics gathered from their customers. This demonstrated that code in high-performance settings made extensive use of [[processor register]]s, and that they often ran out of them. This suggested that additional registers would improve performance. Additionally, they noticed that [[compiler]]s generally ignored the vast majority of the available instructions, especially orthogonal addressing modes. Instead, they selected the fastest version of any given instruction and then constructed small routines using it. This suggested that the majority of instructions could be removed without affecting the resulting code. These two conclusions worked in concert; removing instructions would allow the instruction [[opcode]]s to be shorter, freeing up bits in the instruction word which could then be used to select among a larger set of registers.<ref name=evolution/>

The telephone switch program was canceled in 1975, but by then the team had demonstrated that the same design would offer significant performance gains running just about any code. In simulations, they showed that a compiler tuned to use registers instead of operating directly on memory would run code about three times as fast as traditional designs. Somewhat surprisingly, the same code would run about 50% faster even on existing machines due to the improved register use. In practice, their experimental PL/8 compiler, a slightly cut-down version of [[PL/I]], consistently produced code that ran much faster on their existing mainframes.<ref name=evolution/>

A 32-bit version of the 801 was eventually produced in a single-chip form as the [[IBM ROMP]] in 1981, which stood for 'Research OPD [Office Products Division] Micro Processor'.<ref>{{cite book |first1=Jurij |last1=Šilc |first2=Borut |last2=Robič |first3=Theo |last3=Ungerer |title=Processor architecture: from dataflow to superscalar and beyond |year=1999 |isbn=3-540-64798-8 |pages=[https://archive.org/details/processorarchite00ilcd/page/n52 33] |publisher=Springer |url=https://archive.org/details/processorarchite00ilcd|url-access=limited}}</ref> This CPU was designed for "mini" tasks, and found use in peripheral interfaces and [[channel controller]]s on later IBM computers. It was also used as the CPU in the [[IBM RT PC]] in 1986, which turned out to be a commercial failure.<ref name=Gov239 /> Although the 801 did not see widespread use in its original form, it inspired many research projects, including ones at IBM that would eventually lead to the [[IBM POWER architecture]].<ref name=Jari40 >{{cite book |first=Jari |last=Nurmi |title=Processor design: system-on-chip computing for ASICs and FPGAs |year=2007 |isbn=978-1-4020-5529-4 |pages=[https://archive.org/details/processordesigns00nurm/page/n56 40]–43 |publisher=Springer |url=https://archive.org/details/processordesigns00nurm|url-access=limited}}</ref><ref>{{cite book |first1=Mark Donald |last1=Hill |first2=Norman Paul |last2=Jouppi |author-link2=Norman Jouppi|first3=Gurindar |last3=Sohi |title=Readings in computer architecture |year=1999 |isbn=1-55860-539-8 |pages=252–4|publisher=Gulf Professional }}</ref>

===Berkeley RISC and Stanford MIPS===
By the late 1970s, the 801 had become well-known in the industry. This coincided with new fabrication techniques that were allowing more complex chips to come to market. The [[Zilog Z80]] of 1976 had 8,000 transistors, whereas the 1979 [[Motorola 68000]] (68k) had 68,000. These newer designs generally used their newfound complexity to expand the instruction set to make it more orthogonal. Most, like the 68k, used [[microcode]] to do this, reading instructions and re-implementing them as a sequence of simpler internal instructions. In the 68k, a full {{frac|3}} of the transistors were used for this microcoding.<ref>{{cite magazine |magazine=Byte |date=May 1983 |title= Design Philosophy Behind Motorola's MC68000 |url=http://www.easy68k.com/paulrsm/doc/dpbm68k2.htm |first= Thomas |last=Starnes |page=Photo 1}}</ref>

In 1979, [[David Patterson (computer scientist)|David Patterson]] was sent on a [[sabbatical]] from the [[University of California, Berkeley]] to help DEC's west-coast team improve the VAX microcode. Patterson was struck by the complexity of the coding process and concluded it was untenable.<ref>{{cite web |website=AM SIGARCH |date=30 May 2018 |first=David |last=Patterson |title=RISCy History |url=https://www.sigarch.org/riscy-history/}}</ref> He first wrote a paper on ways to improve microcoding, but later changed his mind and decided microcode itself was the problem. With funding from the [[VLSI Project|DARPA VLSI Program]], Patterson started the [[Berkeley RISC]] effort. The program, practically unknown today, led to a huge number of advances in chip design, fabrication, and even computer graphics. Considering a variety of programs from their [[BSD Unix]] variant, the Berkeley team found, as had IBM, that most programs made no use of the large variety of instructions in the 68k.<ref name=riscii/>

Patterson's early work pointed out an important problem with the traditional "more is better" approach; even those instructions that were critical to overall performance were being delayed by their trip through the microcode. If the microcode was removed, the programs would run faster. And since the microcode ultimately took a complex instruction and broke it into steps, there was no reason the compiler could not do this instead. These studies suggested that, even with no other changes, one could make a chip with {{frac|3}} fewer transistors that would run faster.<ref name=riscii>{{cite web |url=http://euler.mat.uson.mx/~havillam/ca/CS323/0708.cs-323005.html |title=Example: Berkeley RISC II |archive-url=https://web.archive.org/web/20220613053600/http://euler.mat.uson.mx/~havillam/ca/CS323/0708.cs-323005.html |archive-date=2022-06-13 |url-status=dead}}</ref> In the original RISC-I paper they noted:<ref name=PattersonSequin/>

<blockquote>Skipping this extra level of interpretation appears to enhance performance while reducing chip size.<ref name=PattersonSequin/></blockquote>

It was also discovered that, on microcoded implementations of certain architectures, complex operations tended to be ''slower'' than a sequence of simpler operations doing the same thing. This was in part an effect of the fact that many designs were rushed, with little time to optimize or tune every instruction; only those used most often were optimized, and a sequence of those instructions could be faster than a less-tuned instruction performing an equivalent operation as that sequence. One infamous example was the [[VAX]]'s <code>INDEX</code> instruction.<ref name=PattersonDitzel>{{Cite journal |last1=Patterson |first1=D. A. |author-link1=David Patterson (scientist) |last2=Ditzel |first2=D. R. |doi=10.1145/641914.641917 |title=The case for the reduced instruction set computer |journal=ACM SIGARCH Computer Architecture News |volume=8 |issue=6 |pages=25–33 |year=1980 |citeseerx=10.1.1.68.9623 |s2cid=12034303}}</ref>

The Berkeley work also turned up a number of additional points. Among these was the fact that programs spent a significant amount of time performing [[subroutine]] calls and returns, and it seemed there was the potential to improve overall performance by speeding up these calls. This led the Berkeley design to select a method known as [[register window]]s, which can significantly improve subroutine performance, although at the cost of some complexity.<ref name=PattersonSequin/> They also noticed that the majority of mathematical instructions were simple assignments; only {{frac|3}} of them actually performed an operation like addition or subtraction. But when those operations did occur, they tended to be slow. This led to far more emphasis on the underlying arithmetic data unit, as opposed to previous designs where the majority of the chip was dedicated to control and microcode.<ref name=riscii/>

The resulting Berkeley RISC was based on gaining performance through the use of [[instruction pipelining|pipelining]] and aggressive use of register windowing.<ref name=PattersonDitzel /><ref name=PattersonSequin >{{cite conference |first1=David A. |last1=Patterson |first2=Carlo H. |last2=Sequin |title=RISC I: A Reduced Instruction Set VLSI Computer |url=http://dl.acm.org/citation.cfm?id=801895&CFID=730308602&CFTOKEN=83826969 |conference=8th annual symposium on Computer Architecture |location=Minneapolis, MN, USA |year=1981 |pages=443–457 |doi=10.1145/285930.285981|url-access=subscription }} As [https://web.archive.org/web/20170406022438/https://pdfs.semanticscholar.org/9a8a/859d1a9352e13e7fa4fc9e66f1de7066a9c9.pdf PDF]</ref> In a traditional CPU, one has a small number of registers, and a program can use any register at any time. In a CPU with register windows, there are a huge number of registers, e.g., 128, but programs can only use a small number of them, e.g., eight, at any one time. A program that limits itself to eight registers per procedure can make very fast [[procedure call]]s: The call simply moves the window "down" by eight, to the set of eight registers used by that procedure, and the return moves the window back.<ref name=Sequin1 >{{cite conference |first1=Carlo |last1= Sequin |first2=David |last2= Patterson |title=Design and Implementation of RISC I |url=http://www.eecs.berkeley.edu/Pubs/TechRpts/1982/CSD-82-106.pdf |id=CSD-82-106 |conference=Advanced Course on VLSI Architecture|location=University of Bristol|date=July 1982}}</ref> The Berkeley RISC project delivered the RISC-I processor in 1982. Consisting of only 44,420 transistors (compared with averages of about 100,000 in newer [[Complex instruction set computing|CISC]] designs of the era), RISC-I had only 32 instructions, and yet completely outperformed any other single-chip design, with estimated performance being higher than the VAX.<ref name=PattersonSequin/> They followed this up with the 40,760-transistor, 39-instruction RISC-II in 1983, which ran over three times as fast as RISC-I.<ref name=PattersonSequin />

As the RISC project began to become known in [[Silicon Valley]], a similar project began at [[Stanford University]] in 1981. This [[Stanford MIPS|MIPS]] project grew out of a graduate course by [[John L. Hennessy]], produced a functioning system in 1983, and could run simple programs by 1984.<ref name=mipsx >{{cite book |first=Paul |last=Chow |title=The MIPS-X RISC microprocessor |year=1989 |isbn=0-7923-9045-8 |pages=xix–xx|publisher=Springer }}</ref> The MIPS approach emphasized an aggressive clock cycle and the use of the pipeline, making sure it could be run as "full" as possible.<ref name=mipsx /> The MIPS system was followed by the MIPS-X, and in 1984 Hennessy and his colleagues formed [[MIPS Computer Systems]] to produce the design commercially.<ref name=mipsx /><ref name=Jari52 >{{harvnb|Nurmi|2007|pp=52–53}}</ref> The venture resulted in a new architecture that was also called [[MIPS architecture|MIPS]] and the [[R2000 microprocessor]] in 1985.<ref name=Jari52 />

The overall philosophy of the RISC concept was widely understood by the second half of the 1980s and led the designers of the [[MIPS-X]] to put it this way in 1987:

{{blockquote|The goal of any instruction format should be: 1. simple decode, 2. simple decode, and 3. simple decode. Any attempts at improved code density at the expense of CPU performance should be ridiculed at every opportunity.<ref>{{cite conference |first1=Vincent |last1=Weaver |first2=Sally |last2=McKee |title=Code Density Concerns for New Architectures |url=http://web.eece.maine.edu/~vweaver/papers/iccd09/iccd09_density.pdf |conference=ICCD 2009}}</ref>}}

Competition between RISC and conventional CISC approaches was also the subject of theoretical analysis in the early 1980s, leading, for example, to the [[iron law of processor performance]].

[[File:Yunsup Lee holding RISC V prototype chip.jpg|thumb|RISC-V prototype chip (2013)]]
Since 2010, a new [[open standard]] [[instruction set architecture]] (ISA), Berkeley [[RISC-V]], has been under development at the University of California, Berkeley, for research purposes and as a free alternative to proprietary ISAs. As of 2014, version 2 of the [[user space]] ISA is fixed.<ref>{{cite web|last1=Waterman|first1=Andrew|last2=Lee|first2=Yunsup|last3=Patterson|first3=David A.|last4=Asanovi|first4=Krste|title=The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.0|id=Technical Report EECS-2014-54|url=https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.html|publisher=University of California, Berkeley|access-date=1 March 2022}}</ref> The ISA is designed to be extensible from a barebones core sufficient for a small embedded processor to supercomputer and cloud computing use with standard and chip designer–defined extensions and coprocessors. It has been tested in silicon design with the ROCKET [[system on a chip|SoC]], which is also available as an open-source processor generator in the CHISEL language.

===Commercial breakout===
In the early 1980s, significant uncertainties surrounded the RISC concept. One concern involved the use of memory; a single instruction from a traditional processor like the Motorola 68k may be written out as perhaps a half dozen of the simpler RISC instructions. In theory, this could slow the system down as it spent more time fetching instructions from memory. But by the mid-1980s, the concepts had matured enough to be seen as commercially viable.<ref name=Gov239 >''Funding a Revolution: Government Support for Computing Research'' by Committee on Innovations in Computing and Communications 1999 {{ISBN|0-309-06278-0}} page 239</ref><ref name=mipsx />
[[File:Acorn-ARM-Evaluation-System.jpg|thumb|right|upright=1.4|Acorn ARM Evaluation System (1985)]]
Commercial RISC designs began to emerge in the mid-1980s. The [[IBM RT PC]] was introduced in January 1986, and the [[ARM architecture family#ARM1|Acorn ARM1]] was introduced as part of an evaluation system in July 1986,<ref name="acorn1986">{{ cite press release | date=7 July 1986 | access-date=29 June 2025 | title=Acorn Computers Announce The Availability Of An Evaluation System For Their Single Chip, 32-Bit Reduced Instruction Set Computer - The Arm | url=https://chrisacorns.computinghistory.org.uk/docs/Acorn/PR/Acorn_announces_the_ARM_Evaluation_kit.pdf | publisher=Acorn Computers Limited}}</ref> following on from initial fabrication in April 1985.<ref>{{cite journal | title = Speciation through entrepreneurial spin-off: The Acorn-ARM story | journal = Research Policy | date = March 2008 | first = Elizabeth | last = Garnsey | author2= Lorenzoni, Gianni|author3= Ferriani, Simone | volume = 37 | issue = 2 | url = http://www2.sa.unibo.it/~simone.ferriani/Download/Speciation%20through%20Entrepreneurial%20Spin-off.pdf | access-date = 2011-06-02 | quote = [...] the first silicon was run on April 26th 1985. | doi=10.1016/j.respol.2007.11.006 | pages=210–224| s2cid = 73520408 }}</ref> The MIPS R2000 was introduced in May 1986,<ref name="computerworld19860512_mips">{{ cite magazine | url=https://archive.org/details/computerworld2019unse/page/34/mode/1up | title=MIPS Computer Systems jumps into OEM mart with RISC-based products | magazine=Computerworld | last1=Connolly | first1=James | date=12 May 1986 | access-date=29 June 2025 | pages=34 }}</ref> followed shortly thereafter by [[Hewlett-Packard]]'s [[PA-RISC]] in some of their computers.<ref name="fotland198703">{{ cite journal | url=https://archive.org/details/Hewlett-Packard_Journal_Vol._38_No._3_1987-03_Hewlett-Packard/page/n3/mode/2up | title=Hardware Design of the First HP Precision Architecture Computers | last1=Fotland | first1=David A. | last2=Shelton | first2=John F. | last3=Bryg | first3=William R. | last4=La Fetra | first4=Ross V. | last5=Boschma | first5=Simin I. | last6=Yeh | first6=Allan S. | last7=Jacobs | first7=Edward M. | journal=Hewlett-Packard Journal | date=March 1987 | access-date=6 October 2020 | volume=38 | issue=3 | pages=6 }}</ref> In the meantime, the Berkeley effort had become so well known that it eventually became the name for the entire concept. In 1987, [[Sun Microsystems]] began shipping systems with the [[SPARC]] processor, directly based on the Berkeley RISC-II system.<ref name=Gov239 /><ref>{{cite book |first=Allen B. |last=Tucker |title=Computer science handbook |year=2004 |isbn=1-58488-360-X |pages=[https://archive.org/details/computersciencee00tuck/page/n1244 100]–6 |publisher=Taylor & Francis |url=https://archive.org/details/computersciencee00tuck|url-access=limited}}</ref> The US government Committee on Innovations in Computing and Communications credits the acceptance of the viability of the RISC concept to the success of the SPARC system.<ref name=Gov239 />

A benefit of RISC to the industry was much lower prices than the [[sole source]]d [[Intel 80386]];<ref name="inteloh20081202">{{Cite interview |last=Crawford |first=John |interviewer=Jim Jarrett |title=Intel 386 Microprocessor Design and Development Oral History Panel |last2=Hill |first2=Gene |last3=Leukhardt |first3=Jill |last4=Prak |first4=Jan Willem |last5=Slager |first5=Jim |url=https://archive.computerhistory.org/resources/access/text/2015/06/102702019-05-01-acc.pdf |access-date=2025-05-15 |publisher=Computer History Museum |place=Mountain View, California |language=en-US}}</ref> by 1989 many RISC CPUs were available, and competition lowered their price to $10 per MIPS in large quantities. The performance of IBM's RISC CPU—only available in the [[RT PC]]—was less competitive than others,{{r|byte198902}} but the success of SPARC renewed interest within IBM, which released new RISC systems by 1990 and by 1995 RISC processors were the foundation of a $15&nbsp;billion server industry.<ref name=Gov239 />

Patterson was a consultant for [[Intel]] during the 1980s. Despite dominating the microprocessor market with the CISC 80386 and its successors, the consensus that RISC was the future of the industry influenced that company's engineers, who worked to improve the performance of their processors to match RISC.{{r|inteloh20081202}} IBM chose a similar approach of improving CISC as much as possible with [[IBM mainframe]]s,{{r|bellstreckerpdp11vaxalpha}} while introducing new RISC-based computers that competed directly with its existing CISC [[midrange system]]s.<ref name="iw19900219">{{Cite magazine |date=1990-02-19 |title=IBM's Born-Again Workstation Line Will Exorcise RT Ghost, Users Say |url=https://books.google.com/books?id=gTAEAAAAMBAJ&pg=PA1 |access-date=2025-06-28 |magazine=InfoWorld |pages=1,101 |volume=12 |issue=8}}</ref> Sun's move to SPARC was based on its decision to, instead of relying on improvements to CISC, transition to RISC as fast as possible.{{r|bellstreckerpdp11vaxalpha}} The DEC engineers who designed [[DECstation]] with MIPS R2000 and not their company's own VAX did so because, they wrote, the former offered "at least a two-to-one performance advantage" for the cost.<ref name="dtj1990spring_decstation3100">{{ cite journal | url=http://www.bitsavers.org/pdf/dec/dtj/dtj_v02-02_1990.pdf | first1=Thomas C. | last1=Furlong | first2=Michael J. K. | last2=Nielsen | first3=Neil C. | last3=Wilhelm | title=Development of the DECstation 3100 | journal=Digital Technical Journal | volume=2 | issue=2 | date=Spring 1990 | publisher=Digital Equipment Corporation }}</ref><ref name="bellstreckerpdp11vaxalpha">{{Cite report |url=https://archive.computerhistory.org/resources/text/DEC/alpha/dec.alpha.bell_stecker.pdp-11_vax_and_alpha.1998.102630388.pdf |title=What Have We Learned from the PDP-11 - What We Have Learned from VAX and Alpha |last1=Bell |first1=Gordon |author-link1=Gordon Bell |last2=Strecker |first2=W.D. |access-date=2025-06-26}}</ref> By the later 1980s, new RISC designs were easily outperforming all CISC designs by a wide margin.{{r|bellstreckerpdp11vaxalpha}}

By 1992 Sun, DEC, HP, and IBM were the leading commercial RISC companies.<ref name="fisher19921109">{{Cite magazine |last=Fisher |first=Susan E. |date=1992-11-09 |title=It's show time for RISC; DEC to debut Alpha systems, as Sun, HP wait in wings |url=https://galeapps.gale.com/apps/auth?userGroupName=wikipedia&sid=bookmark-GPS&origURL=https%3A%2F%2Fgo.gale.com%2Fps%2Fi.do%3Fp%3DGPS%26u%3Dwikipedia%26id%3DGALE%25257CA12756142%26v%3D2.1%26it%3Dr%26sid%3Dbookmark-GPS%26asid%3D940f7d98&prodId=GPS |access-date=2025-09-29 |magazine=PC Week |via=Gale |volume=9 |issue=45}}</ref> Other vendors began their own RISC efforts. Among the available architectures were the [[DEC Alpha]], [[AMD Am29000]], [[Intel i860]] and [[i960]], [[Motorola 88000]], [[IBM Power microprocessors|IBM POWER]], and, slightly later, the IBM/Apple/Motorola [[PowerPC]]. Many of these have since disappeared due to them often offering no competitive advantage over others of the same era. Those that remain are often used only in niche markets or as parts of other systems; of the designs from these traditional vendors, only SPARC and the PowerPC-derived [[Power ISA]] have any significant remaining market.{{citation needed|reason=This is probably true but needs substantiating.|date=March 2023}}

The [[ARM architecture]] has been the most widely adopted RISC ISA, initially intended to deliver higher-performance desktop computing, at low cost, and in a restricted thermal package, such as in the [[Acorn Archimedes]], while featuring in the [[TOP500#TOP500|Super Computer League tables]], its initial, relatively, lower power and cooling implementation was soon adapted to embedded applications, such as laser printer raster image processing.<ref name="acornuser198808_acorn">{{ cite news | url=https://archive.org/details/AcornUser073-Aug88/page/n8/mode/1up | title=Olivetti buys RISC card | work=Acorn User | date=August 1988 | access-date=24 May 2021 | pages=7 }}</ref> Acorn, in partnership with Apple Inc, and VLSI, creating ARM Ltd, in 1990, to share R&D costs and find new markets for the ISA, who in partnership with TI, GEC, Sharp, Nokia, Oracle and Digital would develop low-power and embedded RISC designs, and target those market segments, which at the time were niche. With the rise in mobile, automotive, streaming, smart device computing, ARM became the most widely used ISA, the company estimating almost half of all CPUs shipped in history have been ARM.<ref>{{Cite web |title=Arm searches for growth beyond smartphones |url=https://www.ft.com/content/0139781c-1db5-4104-bf4f-fdc087971020 |access-date=2024-06-23 |website=www.ft.com|date=23 August 2023 |last1=Bradshaw |first1=Tim }}</ref>

==Characteristics and design philosophy==
{{More citations needed section|date=March 2012}}
{{further|Processor design}}

Confusion around the definition of RISC deriving from the formulation of the term, along with the tendency to opportunistically categorize processor architectures with relatively few instructions (or groups of instructions) as RISC architectures, led to attempts to define RISC as a design philosophy. One attempt to do so was expressed as the following:

{{quotation|A RISC processor has an instruction set that is designed for efficient execution by a pipelined processor and for code generation by an optimizing compiler.|Michael Slater, Microprocessor Report<ref name="ieeemicro199006_risc">{{ cite magazine | url=https://archive.org/details/ieee_micro_v10n3_june_90/page/n99/mode/1up | title=What is RISC? | magazine=IEEE Micro | last1=Slater | first1=Michael | date=June 1990 | access-date=20 March 2023 | pages=96–95 }}</ref>}}

===Instruction set philosophy===
A common misunderstanding of the phrase "reduced instruction set computer" is that instructions are simply eliminated, resulting in a smaller set of instructions.<ref name="esponda" >{{cite book |first1=Margarita |last1=Esponda |first2=Ra'ul |last2=Rojas |chapter=Section 2: The confusion around the RISC concept |title=The RISC Concept — A Survey of Implementations |publisher=Freie Universitat Berlin |date=September 1991 |id=B-91-12 |chapter-url=http://www.inf.fu-berlin.de/lehre/WS94/RA/RISC-9.html}}</ref>
In fact, over the years, RISC instruction sets have grown in size, and today many of them have a larger set of instructions than many CISC CPUs.<ref>{{cite web |first=Jon "Hannibal" |last=Stokes |title=RISC vs. CISC: the Post-RISC Era |website=[[Ars Technica]] |url=https://arstechnica.com/cpu/4q99/risc-cisc/rvc-5.html#Branch}}</ref><ref>
{{cite news |first=Lloyd |last=Borrett |title=RISC versus CISC |newspaper=Australian Personal Computer |date=June 1991 |url=http://www.borrett.id.au/computing/art-1991-06-02.htm}}</ref> Some RISC processors such as the PowerPC have instruction sets as large as the CISC [[IBM System/370]], for example; conversely, the DEC [[PDP-8]]—clearly a CISC CPU because many of its instructions involve multiple memory accesses—has only 8 basic instructions and a few extended instructions.<!--Clarify|reason=IS size is highly dependent on the functionality, which may grow along with number of instructions.|date=April 2019--><ref>{{cite web|url=http://homepage.cs.uiowa.edu/~jones/pdp8/faqs/#instrs|title=Doug Jones's DEC PDP-8 FAQs|work=PDP-8 Collection, The University Of Iowa Department of Computer Science|last=Jones|first=Douglas W.}}</ref>
The term "reduced" in that phrase was intended to describe the fact that the amount of work any single instruction accomplishes is reduced—at most a single data memory cycle—compared to the "complex instructions" of CISC CPUs that may require dozens of data memory cycles in order to execute a single instruction.<ref>{{cite book |first=Sivarama P. |last=Dandamudi |chapter=Ch. 3: RISC Principles |title=Guide to RISC Processors for Programmers and Engineers |url=https://archive.org/details/guidetoriscproce00dand_422 |url-access=limited |year=2005 |isbn=978-0-387-21017-9 |pages= [https://archive.org/details/guidetoriscproce00dand_422/page/n49 39]–44|quote=the main goal was not to reduce the number of instructions, but the complexity |doi=10.1007/0-387-27446-4_3 |publisher=Springer}}</ref>

The term ''[[load–store architecture]]'' is sometimes preferred.

Another way of looking at the RISC/CISC debate is to consider what is exposed to the compiler. In a CISC processor, the hardware may internally use registers and flag bit in order to implement a single complex instruction such as {{code|STRING MOVE}}, but hide those details from the compiler.
The internal operations of a RISC processor are "exposed to the compiler", leading to the [[backronym]] 'Relegate Interesting Stuff to the Compiler'.<ref>{{cite web|first=Colin|last=Walls|url=https://blogs.sw.siemens.com/embedded-software/2016/04/18/cisc-and-risc|title=CISC and RISC|date=April 18, 2016}}</ref><ref>{{cite book|first1=Joseph A.|last1=Fisher|first2=Paolo|last2=Faraboschi|first3=Cliff|last3=Young|url=https://books.google.com/books?id=R5UXl6Jo0XYC|title=Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools|date=2005|page=57|publisher=Elsevier |isbn=9781558607668}}</ref>

===Instruction format===
Most RISC architectures have fixed-length instructions and a simple encoding, which simplifies fetch, decode, and issue logic considerably. This is among the main goals of the RISC approach.<ref name=PattersonSequin/>

Some of this is possible only due to the contemporary move to 32-bit formats. For instance, in a typical program, over 30% of all the numeric constants are either 0 or 1, 95% will fit in one byte, and 99% in a 16-bit value.<ref>{{cite journal |title=Static and Dynamic Characteristics of XPL Programs |journal=IEEE Computer |date=November 1975 |pages=41–48 |first1=W. Gregg |last1=Alexander |first2=David |last2=Wortman| volume=8 | issue=11 | doi=10.1109/C-M.1975.218804 | s2cid=39685209 }}</ref> When computers were based on 8- or 16-bit words, it would be difficult to have an immediate combined with the opcode in a single memory word, although certain instructions like increment and decrement did this implicitly by using a different opcode. In contrast, a 32-bit machine has ample room to encode an immediate value, and doing so avoids the need to do a second memory read to pick up the value. This is why many RISC processors allow a 12- or 13-bit constant to be encoded directly into the instruction word.<ref name=PattersonSequin/>

Assuming a 13-bit constant area, as is the case in the MIPS and RISC designs, another 19 bits are available for the instruction encoding. This leaves ample room to indicate both the opcode and one or two registers. Register-to-register operations, mostly math and logic, require enough bits to encode the two or three registers being used. Most processors use the three-operand format {{code|A {{=}} B + C}}, in which case three register numbers are needed. If the processor has 32 registers, each one requires a 5-bit number for 15 bits total. If one of these registers is replaced by an immediate, there is still room to encode the two remaining registers and the opcode. Common instructions found in multi-word systems, like {{code|INC}} and {{code|DEC}}, which reduce the number of words that have to be read before performing the instruction, are unnecessary in RISC as they can be accomplished with a single register and the immediate value 1.<ref name=PattersonSequin/>

The original RISC-I format remains a canonical example of the concept. It uses 7 bits for the opcode and a 1-bit flag for conditional codes, the following 5 bits for the destination register, and the next five for the first operand. This leaves 14 bits, the first of which indicates whether the following 13 contain an immediate value or uses only five of them to indicate a register for the second operand.<ref name=PattersonSequin/> A more complex example is the MIPS encoding, which used only 6 bits for the opcode, followed by two 5-bit registers. The remaining 16 bits could be used in two ways, one as a 16-bit immediate value, or as a 5-bit shift value (used only in shift operations, otherwise zero) and the remaining 6 bits as an extension on the opcode. In the case of register-to-register arithmetic operations, the opcode was 0 and the last 6 bits contained the actual code; those that used an immediate value used the normal opcode field at the front.<ref>{{cite web |url=https://www.dcc.fc.up.pt/~ricroc/aulas/1920/ac/apontamentos/P04_encoding_mips_instructions.pdf |title=Encoding MIPS Instructions 
|first1=João |last1=Soares |first2=Ricardo |last2=Rocha}}</ref>

One drawback of 32-bit instructions is reduced code density, which is more adverse a characteristic in embedded computing than it is in the workstation and server markets RISC architectures were originally designed to serve. To address this problem, several architectures, such as [[SuperH]] (1992), [[ARM architecture family#Thumb|ARM thumb]] (1994),<ref>{{Cite web |last=Staff |first=Embedded |date=2003-09-24 |title=ARM Thumb Instruction Set |url=https://www.embedded.com/introduction-to-arm-thumb/ |access-date=2024-06-23 |website=Embedded.com |language=en-US}}</ref> [[MIPS architecture|MIPS16e]] (2004), [[Power ISA|Power Variable Length Encoding ISA]] (2006), [[RISC-V]], and the [[Adapteva Epiphany]], have an optional short, feature-reduced [[compressed instruction set]]. Generally, these instructions expose a smaller number of registers and fewer bits for immediate values, and often use a two-operand format to eliminate one register number from instructions. A two-operand format in a system with 16 registers requires 8 bits for register numbers, leaving another 8 for an opcode or other uses. The [[SuperH#SH-5|SH5]] also follows this pattern, albeit having evolved in the opposite direction, having added longer 32-bit instructions to an original 16-bit encoding.

===Hardware utilization===
The most characteristic aspect of RISC is executing at least one [[instruction per cycle]].<ref name="byte198902">{{Cite magazine |last1=Marshall |first1=Trevor |last2=Tazelaar |first2=Jane Morrill |date=February 1989 |title=Worth the RISC |url=https://archive.org/details/eu_BYTE-1989-02_OCR/page/n299/mode/2up?view=theater |access-date=2024-10-08 |magazine=BYTE |pages=245–249}}</ref> Single-cycle operation is described as "the rapid execution of simple functions that dominate a computer's instruction stream", thus seeking to deliver an average throughput approaching one instruction per cycle for any single instruction stream.<ref name="colwell1985">{{ cite journal | url=https://archive.org/details/tutorialsoftware0000unse_s5q2/page/116/mode/2up | title=Instruction Sets and Beyond: Computers, Complexity and Controversy | journal=Computer | publisher=The Institute of Electrical and Electronics Engineers, Inc. | date=September 1985 | access-date=25 March 2023 | last1=Colwell | first1=Robert P. | last2=Hitchcock III | first2=Charles Y. | last3=Jensen | first3=E. Douglas | last4=Sprunt | first4=H. M. Brinkley | last5=Kollar | first5=Charles P. | volume=18 | issue=9 | pages=8–19 | doi=10.1109/MC.1985.1663000 | s2cid=7306378 }}</ref>

Other features of RISC architectures include:

* Far fewer [[transistor]]s dedicated to the core logic, which originally allowed designers to increase the size of the register set and increase internal parallelism.{{citation needed | date=March 2023 | reason=This is undoubtedly consistent with the early literature, but it should still be supported by a citation.}}
* Uniform instruction format, using single word with the opcode in the same bit positions for simpler decoding
* All [[general-purpose register]]s can be used equally as source/destination in all instructions, simplifying compiler design ([[floating-point]] registers are often kept separate)
* Simple addressing modes with complex addressing performed by instruction sequences
* Few [[data type]]s in hardware (no [[byte]] [[String (computer science)|string]] or [[binary-coded decimal]] [BCD], for example)

RISC designs are also more likely to feature a [[Harvard architecture|Harvard memory model]], where the instruction stream and the data stream are conceptually separated; this means that modifying the memory where code is held might not have any effect on the instructions executed by the processor (because the CPU has a separate instruction and data [[CPU cache|cache]]), at least until a special synchronization instruction is issued; CISC processors that have separate instruction and data caches generally keep them synchronized automatically, for backwards compatibility with older processors.

Many early RISC designs also shared the characteristic of having a [[branch delay slot]], an instruction space immediately following a jump or branch. The instruction in this space is executed, whether or not the branch is taken (in other words the effect of the branch is delayed). This instruction keeps the [[Arithmetic logic unit|ALU]] of the CPU busy for the extra time normally needed to perform a branch. Nowadays the branch delay slot is considered an unfortunate side effect of a particular strategy for implementing some RISC designs, and modern RISC designs generally do away with it (such as PowerPC and more recent versions of SPARC and MIPS).{{Citation needed|date=June 2011}}

Some aspects attributed to the first RISC-''labeled'' designs around 1975 include the observations that the memory-restricted compilers of the time were often unable to take advantage of features intended to facilitate ''manual'' assembly coding, and that complex addressing modes take many cycles to perform due to the required additional memory accesses. It was argued{{by whom|date=June 2022}} that such functions would be better performed by sequences of simpler instructions if this could yield implementations small enough to leave room for many registers, reducing the number of slow memory accesses. In these simple designs, most instructions are of uniform length and similar structure, arithmetic operations are restricted to CPU registers and only separate ''load'' and ''store'' instructions access memory. These properties enable a better balancing of pipeline stages than before, making [[RISC pipeline]]s significantly more efficient and allowing higher [[clock frequencies]].

Yet another impetus of both RISC and other designs came from practical measurements on real-world programs. [[Andrew Tanenbaum]] summed up many of these, demonstrating that processors often had oversized immediates. For instance, he showed that 98% of all the constants in a program would fit in 13 [[bit]]s, yet many CPU designs dedicated 16 or 32 bits to store them. This suggests that, to reduce the number of memory accesses, a fixed length machine could store constants in unused bits of the instruction word itself, so that they would be immediately ready when the CPU needs them (much like immediate addressing in a conventional design). This required small opcodes in order to leave room for a reasonably sized constant in a 32-bit instruction word.

Since many real-world programs spend most of their time executing simple operations, some researchers decided to focus on making those operations as fast as possible. The [[clock rate]] of a CPU is limited by the time it takes to execute the slowest ''sub-operation'' of any instruction; decreasing that cycle-time often accelerates the execution of other instructions.<ref>[http://www.ddj.com/architect/184408418 "Microprocessors From the Programmer's Perspective"] by Andrew Schulman 1990</ref> The focus on "reduced instructions" led to the resulting machine being called a "reduced instruction set computer" (RISC). The goal was to make instructions so simple that they could ''easily'' be pipelined, in order to achieve a ''single clock'' throughput at ''high frequencies''. This contrasted with CISC designs whose "crucial arithmetic operations and register transfers" were considered difficult to pipeline.<ref name="sweetman1986">{{ cite conference | url=https://archive.org/details/internationalcom0000yvon/page/83/mode/1up | title=The RISC Workstation | book-title=Proceedings of the Conference Held at Computer Graphics 87, London, October 1987 | publisher=Online Publications | date=1987 | access-date=26 March 2024 | isbn=0-86353-092-3 | last1=Sweetman | first1=Dominic | pages=83–91 }}</ref>

Later, it was noted that one of the most significant characteristics of RISC processors was that external memory was only accessible by a ''load'' or ''store'' instruction. All other instructions were limited to internal registers. This simplified many aspects of processor design: allowing instructions to be fixed-length, simplifying pipelines, and isolating the logic for dealing with the delay in completing a memory access (cache miss, etc.) to only two instructions. This led to RISC designs being referred to as ''load–store'' architectures.<ref>{{cite book |first1=Kevin |last1=Dowd |title=High Performance Computing |publisher=O'Reilly |year=1993 |url=https://archive.org/details/highperformancec00dowd |isbn=1565920325 |first2=Michael K. |last2=Loukides}}</ref>

==Comparison to other architectures==
Some CPUs have been specifically designed to have a very small set of instructions&mdash;but these designs are very different from classic RISC designs, so they have been given other names such as [[minimal instruction set computer]] (MISC) or [[transport triggered architecture]] (TTA).

RISC architectures have traditionally had few successes in the desktop PC and commodity server markets, where the [[x86]]-based platforms remain the dominant processor architecture. However, this may change, as ARM-based processors are being developed for higher performance systems.<ref>{{cite web|last1=Vincent|first1=James|title=Microsoft unveils new ARM server designs, threatening Intel's dominance|url=https://www.theverge.com/2017/3/9/14867310/arm-servers-microsoft-intel-compute-conference|access-date=12 May 2017|website=The Verge|date=9 March 2017}}</ref> Manufacturers including [[Cavium]], AMD, and [[Qualcomm]] have released server processors based on the ARM architecture.<ref>{{cite news|last1=Russell|first1=John|title=Cavium Unveils ThunderX2 Plans, Reports ARM Traction is Growing|url=https://www.hpcwire.com/2016/05/31/cavium-unveils-thunderx2-plans-reports-arm-traction-growing/|access-date=8 March 2017|publisher=HPC Wire|date=31 May 2016}}</ref><ref>{{citation |url=https://www.extremetech.com/extreme/221282-amds-first-arm-based-processor-the-opteron-a1100-is-finally-here |title=AMD's first ARM-based processor, the Opteron A1100, is finally here |publisher=ExtremeTech |date=2016-01-14 |access-date=2016-08-14}}</ref> ARM further partnered with [[Cray]] in 2017 to produce an ARM-based supercomputer.<ref>{{cite news|last1=Feldman|first1=Michael|title=Cray to Deliver ARM-Powered Supercomputer to UK Consortium|url=https://www.top500.org/news/cray-to-deliver-arm-powered-supercomputer-to-uk-consortium/|access-date=12 May 2017|publisher=Top500.org|date=18 January 2017}}</ref> On the desktop, Microsoft announced that it planned to support the PC version of [[Windows 10]] on [[Qualcomm Snapdragon]]-based devices in 2017 as part of its partnership with Qualcomm. These devices will support Windows applications compiled for 32-bit x86 via an x86 processor [[emulator]] that [[binary translation|translates 32-bit x86 code to ARM64 code]].<ref name="verge-w10armsoftware">{{cite web|url=https://www.theverge.com/2016/12/7/13866936/microsoft-windows-10-arm-desktop-apps-support-qualcomm|title=Microsoft is bringing Windows desktop apps to mobile ARM processors|website=The Verge|access-date=8 December 2016|date=8 December 2016}}</ref><ref>{{cite web|url=https://learn.microsoft.com/en-us/windows/arm/apps-on-arm-x86-emulation|title=How x86 emulation works on ARM|date=2023-10-23|website=Microsoft Docs|access-date=27 October 2023}}</ref> Apple announced they will transition their [[Mac (computer)|Mac]] desktop and laptop computers from Intel processors to internally developed ARM64-based [[System on a chip|SoCs]] called [[Apple silicon]]; the first such computers, using the [[Apple M1]] processor, were released in November 2020.<ref name="ARM-Macs-available">{{cite press release|url=https://www.apple.com/newsroom/2020/11/introducing-the-next-generation-of-mac/|title=Introducing the next generation of Mac|publisher=Apple Inc.|date=November 10, 2020}}</ref> Macs with Apple silicon can run x86-64 binaries with [[Rosetta 2]], an x86-64 to ARM64 translator.<ref>{{cite press release|url=https://www.apple.com/newsroom/2020/11/macos-big-sur-is-here/|title=macOS Big Sur is here|publisher=Apple Inc.|date=November 12, 2020}}</ref>

Outside of the desktop arena, however, the ARM RISC architecture is in widespread use in smartphones, tablets and many forms of embedded devices. While early RISC designs differed significantly from contemporary CISC designs, by 2000 the highest-performing CPUs in the RISC line were almost indistinguishable from the highest-performing CPUs in the CISC line.<ref>{{cite book |first=Nicholas P. |last=Carter |title=Schaum's Outline of Computer Architecture |year=2002 |isbn=0-07-136207-X |pages=96 |publisher=McGraw Hill Professional |url=https://books.google.com/books?id=24V00tD7HeAC&pg=PT105}}</ref><ref>{{cite web |first=Douglas L. |last=Jones |title=CISC, RISC, and DSP Microprocessors |date=2000 |url=http://www.ifp.uiuc.edu/~jones/RISCvCISCvDSP.pdf |access-date=17 December 2008 |archive-date=7 September 2008 |archive-url=https://web.archive.org/web/20080907083430/http://www.ifp.uiuc.edu/~jones/RISCvCISCvDSP.pdf |url-status=dead }}</ref><ref>
{{cite web |first=Amit |last=Singh |title=A History of Apple's Operating Systems |url=http://www.kernelthread.com/publications/appleoshistory/5.html |quote=the line between RISC and CISC has been growing fuzzier over the years |archive-url=https://web.archive.org/web/20200403101510/http://www.kernelthread.com/publications/appleoshistory/5.html |archive-date=April 3, 2020 |url-status=dead}}</ref>

==Use of RISC architectures==
RISC architectures are now used across a range of platforms, from smartphones and [[tablet computer]]s to some of the world's fastest [[supercomputer]]s such as [[Fugaku (supercomputer)|Fugaku]], the fastest on the [[TOP500]] list {{as of|2020|11|lc=yes}}, and [[Summit (supercomputer)|Summit]], [[Sierra (supercomputer)|Sierra]], and [[Sunway TaihuLight]], the next three on that list.<ref name="top500-november-2020">{{Cite web|url=https://www.top500.org/lists/2020/11/|title=Top 500 The List: November 2020|website=TOP 500|access-date=2 January 2021}}</ref>

===Low-end and mobile systems===
By the beginning of the 21st century, the majority of low-end and mobile systems relied on RISC architectures.<ref>{{harvnb|Dandamudi|2005|pp=121–123}}</ref> Examples include:
 
* The [[ARM architecture]] dominates the market for low-power and low-cost embedded systems (typically 200–1800&nbsp;MHz in 2014). It is used in a number of systems such as most [[Android (operating system)|Android]]-based systems, the Apple [[iPhone]], [[iPod Touch]], [[iPad]], [[Apple Watch]], and [[Apple TV (device)|Apple TV]], [[Palm (PDA)|Palm]], Microsoft [[Windows Phone]] (former [[Windows Mobile]] / Windows CE), [[BlackBerry Limited|RIM]] devices, Nintendo [[Game Boy Advance]], [[Nintendo DS|DS]], [[3DS]] and [[Nintendo Switch|Switch]], [[Raspberry Pi]], etc.
* IBM's PowerPC was used in the [[GameCube]], [[Wii]], [[PlayStation 3]], [[Xbox 360]] and [[Wii U]] gaming consoles.
* The [[MIPS architecture|MIPS]] line (at one point used in many [[Silicon Graphics|SGI]] computers) was used in the [[PlayStation (console)|PlayStation]], [[PlayStation 2]], [[Nintendo 64]], [[PlayStation Portable]] game consoles, and [[residential gateway]]s like [[Linksys WRT54G series]].
* [[Hitachi]]'s [[SuperH]], originally in wide use in the [[32X]], [[Sega Saturn|Saturn]], and [[Dreamcast]] consoles, now developed and sold by [[Renesas]] as the [[SuperH|SH4]].
* [[Atmel AVR]], used in a variety of products ranging from [[Xbox (console)|Xbox]] handheld controllers and the [[Arduino]] open-source microcontroller platform to [[BMW]] cars.
* [[RISC-V]], the current iteration of Berkeley's [[open standard]]  RISC ISA, with 32- or 64-bit [[Virtual address space|address space]]s, a small core integer instruction set, and an experimental "Compressed" ISA for code density and designed for standard and special-purpose extensions.

===Desktop and laptop computers===
* IBM's PowerPC architecture was used in Apple's [[Macintosh]] computers from 1994, when they began a switch from [[Motorola 68000 family]] processors, to 2005, when they [[Mac transition to Intel processors|transitioned to Intel x86 processors]].<ref>{{cite news |last1=Bennett |first1=Amy |title=Apple shifting from PowerPC to Intel |url=https://www.computerworld.com/article/2809210/apple-shifting-from-powerpc-to-intel.html |access-date=24 August 2020 |work=[[Computerworld]] |date=2005 |archive-date=13 November 2020 |archive-url=https://web.archive.org/web/20201113060929/https://www.computerworld.com/article/2809210/apple-shifting-from-powerpc-to-intel.html |url-status=dead }}</ref>
* Some [[chromebook]]s use ARM-based platforms since 2012.<ref>{{Cite web|last=Vaughan-Nichols|first=Steven J.|title=Review: The ARM-powered Samsung Chromebook|url=https://www.zdnet.com/article/review-the-arm-powered-samsung-chromebook/|access-date=2021-04-28|website=ZDNet|language=en}}</ref>  
* [[Apple Inc.|Apple]] uses [[Apple silicon|inhouse-designed processors]] based on the ARM architecture for its lineup of desktop and laptop computers since its [[Mac transition to Apple silicon|transition]] from [[Intel]] processors,<ref>{{cite news |last1=DeAngelis |first1=Marc |title=Apple starts its two-year transition to ARM this week |url=https://www.engadget.com/apple-arm-transition-timeline-191106454.html |access-date=24 August 2020 |work=[[Engadget]] |quote=Apple has officially announced that it will be switching from Intel processors to its own ARM-based, A-series chips in its Mac computers.|date=22 June 2020}}</ref> and the first such computers were released in November 2020.<ref name="ARM-Macs-available"/>
* [[Microsoft]] uses Qualcomm<ref>{{Cite web|title=Microsoft to launch a new ARM-based Surface this fall|first=Chris|last=Smith|date=September 16, 2020|url=https://bgr.com/tech/surface-pro-x-2020-release-date-october-snapdragon-8cx-gen-2-chip-5872000/|website=[[Boy Genius Report]]|access-date=2023-03-20}}</ref> ARM-based processors for its [[Microsoft Surface|Surface]] line. [[HP Inc]] and [[Lenovo]] have released [[Windows]] PCs with an ARM-based [[Qualcomm Snapdragon]].

===Workstations, servers, and supercomputers===
* [[MIPS Technologies|MIPS]], by [[Silicon Graphics]] (ceased making MIPS-based systems in 2006).
* [[SPARC]], by [[Oracle Corporation|Oracle]] (previously [[Sun Microsystems]]), and [[Fujitsu]].
* [[IBM]]'s [[IBM POWER architecture]], PowerPC, and [[Power ISA]] were and are used in many of IBM's supercomputers, mid-range servers and workstations.
* [[Hewlett-Packard]]'s [[PA-RISC]], also known as HP-PA (discontinued at the end of 2008).
* [[DEC Alpha|Alpha]], used in [[single-board computer]]s, workstations, servers and supercomputers from [[Digital Equipment Corporation]], then [[Compaq]] and finally [[Hewlett-Packard]] (HP)(discontinued as of 2007).
* [[RISC-V]], the fifth Berkeley RISC ISA, with 64- or 128-bit [[Virtual address space|address spaces]], and the integer core extended with floating point, [[Atomic operations (computing)|atomics]] and [[vector processing]], and designed to be extended with instructions for networking, I/O, and data processing. A specification for a 64-bit superscalar design, "Rocket", is available for download. It is implemented in the [[European Processor Initiative]] processor.
* The [[ARM architecture]] currently in use by cloud providers for servers. One example is the [[AWS Graviton]] series processor used for various services on the AWS platform.<ref>{{Cite web |title=ARM Processor - AWS Graviton Processor - AWS |url=https://aws.amazon.com/ec2/graviton/ |access-date=2024-01-09 |website=Amazon Web Services, Inc. |language=en-US}}</ref> ARM was also used in the [[Fujitsu A64FX]] chip to create Fugaku, the world's fastest supercomputer in 2020.

===Open source, standard, or use===
RISC architectures have become popular in [[Open-source hardware|open source processors]] and [[soft microprocessor]]s since they are relatively simple to implement, which makes them suitable for [[FPGA]] implementations and prototyping, for instance. Examples include:

* [[OpenRISC]], an open instruction set and micro-architecture first introduced in 2000.
* Open [[MIPS architecture]], for part of 2019 the specifications were free to use, royalty free, for registered MIPS developers.<ref>{{Cite web |date=2019-11-15 |title=Wave Computing Shutters MIPS Open Programme with Immediate Effect |url=https://abopen.com/news/wave-computing-shutters-mips-open-programme-with-immediate-effect/ |access-date=2024-06-23 |website=AB Open |language=en-US}}</ref>
* [[OpenSPARC]], in 2005, Sun released its Ultra Sparc documentation and specifications, under the GPLv2.
** [[LEON]], an open source, radiation-tolerant implementation of the [[SPARC]] V8 instruction set (targeting space applications).
* [[Libre-SOC]], an open source [[System on chip|SoC]] based on the [[Power ISA]] with extensions for video and 3D graphics.
* [[RISC-V#Open_source|RISC-V]], in 2010, the Berkeley RISC version 5, specification, tool chain, and brand, were made available, free of charge, for non-commercial purposes.<ref>{{Cite web |title=Branding Guidelines – RISC-V International |url=https://riscv.org/about/risc-v-branding-guidelines/ |access-date=2024-06-23 |language=en-US}}</ref>
* [[SuperH#J_Core|SuperH - J Core]], in 2015, a project to offer clean room implementations of the, patent expired, Hitachi SuperH RISC ISA was started.
* ARM DesignStart, in 2018 ARM, in partnership with FPGA supplier Xilinx, started to offer free access to some of ARM's IP, including FPGA specification for some older CPU cores.<ref>{{Cite web |title=Arm Expands Design Possibilities with Free Cortex-M Processors for Xilinx FPGAs |url=https://newsroom.arm.com/news/arm-expands-design-possibilities-with-free-cortex-m-processors-for-xilinx-fpgas |access-date=2024-06-23 |website=Arm Newsroom |language=en-US}}</ref>

==Awards==
In 2022 [[Steve Furber]], [[John L. Hennessy]], [[David Patterson (computer scientist)|David A. Patterson]] and [[Sophie Wilson|Sophie M. Wilson]] were awarded the [[Charles Stark Draper Prize]] by the United States [[National Academy of Engineering]] for their contributions to the invention, development, and implementation of reduced instruction set computer (RISC) chips.<ref name=risc>{{cite web|url=https://www.nae.edu/55291/DraperWinners|website=nae.edu|title=Recipients of the Charles Stark Draper Prize for Engineering}}</ref><ref name=draper>{{cite web|url=https://www.nae.edu/20681/DraperPrize|website=nae.edu|title=Charles Stark Draper Prize for Engineering}}</ref>

==See also==
* [[Explicitly parallel instruction computing]]
* [[No instruction set computing]]
* [[One-instruction set computer]]
* [[Very long instruction word]]

==References==
{{Reflist|refs=

<ref name="computer-sep1985">{{cite magazine |last1=Colwell |first1=Robert P. |last2=Hitchcock III |first2=Charles Y. |last3=Jensen |first3=E. Douglas |last4=Sprunt |first4=H. M. Brinkley |last5=Kollar |first5=Charles P. |date=September 1985 |title=Instruction Sets and Beyond: Computers, Complexity, and Controversy |url=https://pages.cs.wisc.edu/~markhill/restricted/ieeecomputer85_cisc.pdf |magazine=[[Computer (magazine)|Computer]] |pages=8–19 |location= |publisher=IEEE |access-date=}}</ref>

<ref name="aletanpaper">{{cite conference |url=https://dl.acm.org/doi/10.1145/143559.143570 |title=An overview of RISC architecture |last1=Aletan |first1=Samuel O. |author-link1= |date=1 April 1992 |publisher=[[Association for Computing Machinery]] |book-title=Proceedings of the 1992 ACM/SIGAPP Symposium on Applied computing: technological challenges of the 1990's |pages=11–20 |location=Kansas City, Missouri |conference=SAC '92 |id= |doi=10.1145/143559.143570 |url-access=subscription }}</ref>

<ref name="byte-nov1984">{{cite magazine |last=Markoff |first=John |date=November 1984 |title=New Chips — RISC Chips |url=https://archive.org/details/byte-magazine-1984-11/page/n191/mode/2up |magazine=[[Byte (magazine)|Byte]] |volume=9 |number=12 |pages=191–206 |location= |publisher=McGraw-Hill |access-date=}}</ref>

<ref name="pbdla-histoire">{{cite web |url=http://boursinp.free.fr/bonus4.htm |title=Histoire de l'Informatique et d'Internet |last=Boursin de l'Arc |first=Philippe |date= |website=boursinp.free.fr |publisher= |access-date= }}</ref>

<ref name="em-sep1987-p59">{{cite magazine |last=Manuel |first=Tom |date=3 September 1987 |title=Inside Technology — The Frantic Search for More Speed |url=https://worldradiohistory.com/Archive-Electronics/80s/87/Electronics-1987-09-03.pdf#page=65 |magazine=[[Electronics (magazine)|Electronics]] |pages=59–62 |location= |publisher=McGraw-Hill |access-date=}}</ref>

}}

==External links==
{{refbegin}}
* {{cite web |title=RISC vs. CISC |date=2000 |work=RISC Architecture |publisher=Stanford University |url=http://cs.stanford.edu/people/eroberts/courses/soco/projects/2000-01/risc/risccisc/}}
* {{cite web |title=What is RISC |date=2000 |work=RISC Architecture |publisher=Stanford University |url=http://cs.stanford.edu/people/eroberts/courses/soco/projects/2000-01/risc/whatis/}}
* {{cite web |first=John J. G. |last=Savard |title=Not Quite RISC |work=Computers |url=http://www.quadibloc.com/arch/sriscint.htm}}
*{{cite newsgroup
 |title=Yet Another Post of the Old RISC Post [unchanged from last time]
 |first=John R. |last=Mashey |author-link=John R. Mashey
 |date=5 September 2000
 |newsgroup=comp.arch
 |message-id=8p20b0$dhh$3@murrow.corp.sgi.com
 |url= https://groups.google.com/d/topic/comp.arch/IZP5KUJprHw/discussion
 |quote=Nth re-posting of CISC vs RISC (or what is RISC, really)
}}
{{refend}}

{{RISC architectures|state=uncollapsed}}
{{CPU technologies}}
{{Authority control}}

{{DEFAULTSORT:Reduced Instruction Set Computing}}
[[Category:Classes of computers]]
[[Category:Instruction set architectures| ]]