View source for R4200

{{Inline improve|date=January 2015}}
{{short description|Microprocessor designed by MIPS Technologies, Inc.}}
The '''R4200''' is a [[microprocessor]] designed by [[MIPS Technologies]] that implemented the [[MIPS architecture|MIPS III instruction set architecture]] and was initially referred to as the VRX during development. MIPS, which had no production capability of its own, licensed the design to [[NEC]], which fabricated and marketed it as the VR4200. The first VR4200, running at 80&nbsp;[[Hertz|MHz]], was introduced in 1993, with a faster 100&nbsp;MHz version following in 1994.

Primarily aimed at low-power [[Windows NT]] systems such as personal computers and laptops,<ref name="pcw199404_processors">{{cite magazine |last1=Rockman |first1=Simon |date=April 1994 |title=Six of the best |magazine=Personal Computer World |pages=464-468,470,472}}</ref>{{rp|pages=468|quote=If anyone wanted to build a notebook specifically for running NT, the R4200 would be an obvious choice. Glenn Henry, formerly of IBM and then head of advanced R&D at Dell, is now working for the division at MIPS which makes the R4200. While he's a chip designer at heart he knows better than anyone how the PC industry views chip designs.}} the R4200 was marketed as offering "Pentium processor performance at a tenth of the price." It was initially expected to deliver twice the performance of a 66&nbsp;MHz Intel [[Intel DX2|486DX2]] processor. SPECint benchmark results showed the microprocessor’s integer performance at approximately 85% of the [[Pentium (original)|original Pentium]], while its floating-point performance was about half that of the Pentium. 

The R4300i is a derivative of the R4200, designed by MIPS for embedded applications. A variant of the R4300i was used in the widely popular [[Nintendo 64]] and SNK's [[Hyper Neo Geo 64]] arcade board. 

The R4200 never saw use in personal computers and was eventually repositioned as an embedded microprocessor complementing the [[R4600]].

==Description==
The R4200 is a [[Scalar processor|scalar]] design with a five-stage [[classic RISC pipeline]]. Notably, [[floating point]] [[Significand|mantissa]] calculation reused the 64-bit integer [[datapath]] (only the exponent needed a separate 12-bit datapath).<ref>{{Cite journal |last=Yeung |first=N. |last2=Zivkov |first2=B. |last3=Ezer |first3=G. |date=February 1994 |title=Unified datapath: an innovative approach to the design of a low-cost, low-power, high-performance microprocessor |url=https://ieeexplore.ieee.org/document/282948 |journal=Proceedings of COMPCON '94 |pages=32–37 |doi=10.1109/CMPCON.1994.282948}}</ref> This scheme reduced chip size and transistor count, reducing cost and power consumption. Whilst this reduced [[floating point]] performance, the R4200's intended applications did not require high floating point performance.

The R4200 has a 16&nbsp;[[Kilobyte|kB]] instruction [[CPU cache|cache]] and an 8&nbsp;kB data cache. Both caches are [[CPU cache#Associativity|direct-mapped]]. The instruction cache has a 32-byte line size, whereas the data cache has 16-byte line size. The data cache uses the [[write-back]] write protocol.

The R4200 has a 32-entry [[translation lookaside buffer]] (TLB) for data, and a 4-entry TLB for instructions. A 33-bit [[physical address]] is supported. The [[system bus]] is 64 bits wide and operates at half the internal clock frequency.

The R4200 contained 1.3 million transistors and had an area of 81&nbsp;mm<sup>2</sup>. NEC fabricated the R4200 in a [[600 nm process]] with three levels of interconnect. It was packaged in a 179-pin [[ceramic pin grid array]] that was compatible with the [[R4000|R4x00PC]] and [[R4600]], or a 208-pin [[PQFP|plastic quad flat pack]] (PQFP). It used a 3.3&nbsp;V power supply, dissipating 1.8&nbsp;W typically and a maximum of 2&nbsp;W at 80&nbsp;MHz.

In comparison to the Pentium, [[SPECint]] ratings had the Pentium at 64.5 and the R4200 at 55. [[SPECfp]] ratings had the Pentium at 56 versus the R4200 at 30.<ref name="byte199307_mips">{{ cite magazine | url=https://archive.org/details/BYTEVol1808199307PentiumPCs/page/n31/mode/1up | title=Low-Power RISC from MIPS | magazine=[[Byte (magazine)|Byte]] | date=July 1993 | access-date=26 April 2022 | last1=Halfhill | first1=Tom R. | pages=28 }}</ref>

==R4300i==
[[File:CPU-NUS 01.jpg|thumb|CPU-NUS in a Nintendo 64. It is a custom version of the NEC R4300 and is based on the R4300i]]
The R4300i is a derivative of the R4200, designed by MIPS for embedded applications and announced on 17 April 1995.<ref name="MTI1995" /> It improves on the R4200 with a faster integer multiplier featuring lower latency and a simplified 32-bit system bus to reduce costs. The chip, measuring 45&nbsp;mm², was fabricated using a [[350 nm process]] and was packaged in a low-cost [[Quad flat package|120-pin PQFP]] by employing multiplexed address and data lines. It operates on a 3.3&nbsp;V power supply and dissipating 1.5&nbsp;W at 40&nbsp;MHz (80&nbsp;MHz internally),<ref name="byte199612_supermario">{{cite magazine |last1=Simha |first1=Satya |date=December 1996 |title=Super Mario Chip |url=https://archive.org/details/eu_BYTE-1996-12_OCR/page/n94/mode/1up |access-date=25 April 2022 |magazine=Byte |pages=59–60}}</ref> 1.8&nbsp;W at 100&nbsp;MHz and 2.2&nbsp;W at 133&nbsp;MHz.

The R4300i was licensed to NEC and [[Toshiba]], who marketed it as the VR4300 and TX4300, respectively, with 100 and 133&nbsp;MHz versions. 

NEC produced a version of the VR4300 for the Nintendo 64 called the CPU-NUS, clocked at 93.75&nbsp;MHz with a performance of 125 [[million instructions per second]].<ref name="NECVR43002">{{Cite web |title=Main specifications of VR4300TM-series |url=http://www.nec.co.jp/press/en/9711/1401-01.html |archive-url=https://web.archive.org/web/20200710173520/http://www.nec.co.jp/press/en/9711/1401-01.html |archive-date=July 10, 2020 |access-date=May 20, 2006 |publisher=[[NEC]]}}</ref> ''[[Popular Electronics]]'' compared its processing power to that of contemporary [[Pentium]] desktop processors.<ref name="Popular Will">{{Cite magazine |date=March 1997 |title=(Will You Still Love Me) When I'm 64 |magazine=[[Popular Electronics]] |volume=14 |issue=3}}</ref> Though constrained by a narrower [[32-bit]] system [[Bus (computing)|bus]], the VR4300 retained the computational capabilities of the more powerful 64-bit R4300i.<ref name="NECVR4300">{{Cite web |title=Main specifications of VR4300TM-series |url=http://www.nec.co.jp/press/en/9711/1401-01.html |archive-url=https://web.archive.org/web/20200710173520/http://www.nec.co.jp/press/en/9711/1401-01.html |archive-date=July 10, 2020 |access-date=May 20, 2006 |publisher=[[NEC]]}}</ref> However, software rarely utilized 64-bit precision, as Nintendo 64 games primarily relied on faster and more compact 32-bit operations.<ref name="32bitmode">{{Cite web |last=Copetti |first=Rodrigo |date=September 12, 2019 |title=Nintendo 64 Architecture: A Practical Analysis |url=https://www.copetti.org/writings/consoles/nintendo-64/ |archive-url=https://web.archive.org/web/20230730091625/https://www.copetti.org/writings/consoles/nintendo-64/ |archive-date=July 30, 2023 |access-date=August 4, 2023 |publisher=}}</ref>

NEC also developed two other derivatives for the embedded market, the VR4305 and VR4310, announced on 20 January 1998.<ref name="NEC1998" /> The VR4310, available at 100, 133, or 167&nbsp;MHz, was manufactured in a [[250 nm process]] and packaged in a 120-pin PQFP.

==References==
{{reflist | refs=
<ref name="MTI1995">{{cite press release | publisher=MIPS Technologies, Inc. | date=17 April 1995 | title=MIPS/NEC Announce New Consumer-market RISC Processor}}</ref>
<ref name="NEC1998">{{cite press release | publisher=NEC Corporation | date=20 January 1998 | title=NEC Offers Two High Cost Performance 64-bit RISC Microprocessors}}</ref>
}}
* "MIPS, NEC will launch 64-bit device". (17 April 1995). ''[[Electronic News]]''.
* "NEC Unveils New MIPS Chip for Nintendo". (8 May 1995). ''[[Microprocessor Report]]''.
* Gwennap, Linley (31 May 1993). "MIPS Reaches New Lows With R4200 Design". ''[[Microprocessor Report]]'', pp.&nbsp;6&ndash;9.
* Levy, Marcus (15 September 1994). "EDN's 21st Annual Microprocessor Directory". ''[[EDN (magazine)|EDN]]''.
* Ryan, Bob; Thompson, Tom (January 1994). "RISC Grows Up". ''[[Byte (magazine)|Byte]]''.
* Yeung, N.K. et al. (1994). "The design of a 55SPECint92 RISC processor under 2W". ''ISSCC Digest of Technical Papers''. pp.&nbsp;206&ndash;207.
* Zivkov, B.; Ferguson, B.; Gupta, M. (1994). ''Compcon Spring '94, Digest of Papers''. pp.&nbsp;18&ndash;25.

{{MIPS microprocessors}}
{{Nintendo hardware}}
{{NEC Corporation}}

[[Category:MIPS implementations]]
[[Category:MIPS microprocessors]]
[[Category:NEC microprocessors]]
[[Category:64-bit microprocessors]]