View source for Package on a package

{{Short description|Integrated circuit packaging method}}
{{Confuse|System in a package}}
'''Package on a package''' ('''PoP''') is an [[integrated circuit packaging]] method to vertically combine [[ball grid array]] (BGA) packages for discrete logic and [[Semiconductor memory|memory]]. Two or more packages are installed atop each other, i.e. stacked, with a standard interface to route signals between them. PoP allows higher component density in devices, such as [[mobile phone]]s, [[personal digital assistant]]s (PDA), and [[digital camera]]s, at the cost of being slightly taller. Stacks with more than 2 packages are uncommon, due to heat dissipation considerations.

==Configuration==
Two widely used configurations exist for PoP:
* Pure memory stacking: two or more memory only packages are stacked on each other
* Mixed logic-memory stacking: logic (CPU) package on the bottom, memory package on top. For example, the bottom could be a [[system on a chip]] (SoC) for a [[mobile phone]]. The logic package is on the bottom because it needs many more BGA connections to the motherboard.

[[Image:ASIC + Memory PoP Schematic.JPG|center|thumb|upright=2.9|Typical logic plus memory PoP stack, common to mobile phone [[System on a chip|SoC]]s or baseband modems from 2005 onward]]

During [[PCB assembly]], the bottom package of a PoP stack is placed directly on the PCB, and the other package(s) of the stack are stacked on top.
The packages of a PoP stack become attached to each other (and to the PCB) during [[reflow soldering]].

PoP packaging can be done by the chip manufacturer (such as [[Samsung]] or [[TSMC]]), or can be done by the OEM (such as [[Meizu]]).

==Benefits==
The package on a package technique tries to combine the benefits of traditional packaging with the benefits of [[Three-dimensional integrated circuit|die-stacking]] techniques, while avoiding their drawbacks.

Traditional packaging places each die in its own package, a package designed for normal PCB assembly techniques that place each package directly on the PCB side-by-side.
The [[3D die-stacking]] [[system in package]] (SiP) techniques stacks multiple die in a single package, which has several advantages and also some disadvantages compared to traditional PCB assembly.

In embedded PoP techniques, chips are embedded in a substrate on the bottom of the package. This PoP technology enables smaller packages with shorter electrical connections and is supported by companies such as [[Advanced Semiconductor Engineering]] (ASE).<ref name="LaPedus_2014"/>

=== Advantages over traditional isolated-chip packaging ===

The most obvious benefit is motherboard space savings. PoP uses much less PCB area, almost as little as stacked-die packages.

Electrically, PoP offers benefits by minimizing track length between different interoperating parts, such as a controller and memory. This yields better electrical performance of devices, since shorter routing of interconnections between circuits yields faster signal propagation and reduced noise and cross-talk.

=== Advantages over chip stacking ===

There are several key differences between stacked-die and stacked-package products.

The main financial benefit of package on a package is that the memory device is decoupled from the logic device. Therefore this gives PoP all the same advantages that traditional packaging has over stacked-die products:
* The memory package can be tested separately from the logic package
* Only "known good" packages are used in final assembly (if the memory is bad only the memory is discarded and so on). Compare this to stacked-die packages where the entire set is useless and rejected if either the memory or logic is bad.
* The end user (such as makers of [[mobile phone]]s or [[digital camera]]s) controls the logistics. This means memory from different suppliers can be used at different times without changing the logic. The memory becomes a commodity to be sourced from the lowest cost supplier. This trait is also a benefit compared to PiP (package in package) which requires a specific memory device to be designed in and sourced upstream of the end user.
* Any mechanically mating top package can be used. For a low-end phone, a smaller memory configuration may be used on the top package. For a high-end phone, more memory could be used with the same bottom package.<ref name="Thomas_2015"/> This simplifies inventory control by the OEM. For a stacked-die package or even PiP (package in package), the exact memory configuration must be known weeks or months in advance.
* Because the memory only comes into the mix at final assembly, there is no reason for logic suppliers to source any memory. With a stacked-die device, the logic provider must buy wafers of memory from a memory supplier.

==JEDEC standardization==
* [[JEDEC]] JC-11 committee deals with package outline drawing standards related to the bottom PoP package. See documents MO-266A and JEDEC publication 95, Design Guide 4.22.
* JEDEC JC-63 committee deals with top (memory) PoP package pinout standardization. See JEDEC Standard No. 21-C, Page 3.12.2 – 1

==Other names==
Package on a package is also known by other names:
* PoP: refers to the combined top and bottom packages
* PoPt: refers to the top package
* PoPb: refers to the bottom package
* PSvfBGA: refers to the bottom package: ''P''ackage ''S''tackable ''V''ery thin ''F''ine pitch ''B''all ''G''rid ''A''rray<ref name="Amkor_2015"/>
* PSfcCSP: refers to the bottom package: ''P''ackage ''S''tackable ''F''lip ''C''hip ''C''hip ''S''cale ''P''ackage

==History==
{{Main|Three-dimensional integrated circuit#History}}

In 2001, a [[Toshiba]] research team including T. Imoto, M. Matsui and C. Takubo developed a "System Block Module" wafer bonding process for manufacturing [[3D integrated circuit]] (3D IC) packages.<ref>{{cite book |last1=Garrou |first1=Philip |title=Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits |date=6 August 2008 |publisher=[[Wiley-VCH]] |isbn=9783527623051 |chapter=Introduction to 3D Integration |doi=10.1002/9783527623051.ch1 |pages=4 |url=https://application.wiley-vch.de/books/sample/3527332650_c01.pdf}}</ref><ref>{{cite journal |last1=Imoto |first1=T.|last2=Matsui |first2=M. |last3=Takubo |first3=C. |last4=Akejima |first4=S. |last5=Kariya |first5=T. |last6=Nishikawa |first6=T. |last7=Enomoto |first7=R. |title=Development of 3-Dimensional Module Package, "System Block Module" |journal=Electronic Components and Technology Conference |date=2001 |issue=51 |publisher=[[Institute of Electrical and Electronics Engineers]] |pages=552–7 |url=https://www.tib.eu/en/search/id/BLCP%3ACN039662991/Development-of-3-Dimensional-Module-Package-System/}}</ref> The earliest known commercial use of a 3D package-on-package chip was in [[Sony]]'s [[PlayStation Portable]] (PSP) [[handheld game console]], released in 2004. The [[PSP hardware]] includes [[eDRAM]] (embedded [[Dynamic random-access memory|DRAM]]) memory manufactured by [[Toshiba]] in a 3D package chip with two dies stacked vertically.<ref name="James">{{cite book |last1=James |first1=Dick |title=25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014) |chapter=3D ICs in the real world |date=2014 |pages=113–119 |doi=10.1109/ASMC.2014.6846988 |isbn=978-1-4799-3944-2 |s2cid=42565898 |chapter-url=https://www.researchgate.net/publication/271453642}}</ref> Toshiba called it "semi-embedded DRAM" at the time, before later calling it a stacked "chip-on-chip" (CoC) solution.<ref name="James"/><ref>{{cite web |title=System-in-Package (SiP) |url=http://www.toshiba-components.com/ASIC/SiP.html |archive-url=https://web.archive.org/web/20100403003319/http://www.toshiba-components.com/ASIC/SiP.html |url-status=dead |archive-date=3 April 2010 |website=[[Toshiba]] |access-date=3 April 2010}}</ref>

In April 2007, Toshiba commercialized an eight-layer 3D chip package, the 16{{nbsp}}[[Gibibyte|GB]] THGAM [[Embedded system|embedded]] [[NAND flash]] memory chip, which was manufactured with eight stacked 2{{nbsp}}GB NAND flash chips.<ref>{{cite news |title=TOSHIBA COMMERCIALIZES INDUSTRY'S HIGHEST CAPACITY EMBEDDED NAND FLASH MEMORY FOR MOBILE CONSUMER PRODUCTS |url=http://www.toshiba.com/taec/news/press_releases/2007/memy_07_470.jsp |archive-url=https://web.archive.org/web/20101123023805/http://www.toshiba.com/taec/news/press_releases/2007/memy_07_470.jsp |url-status=dead |archive-date=November 23, 2010 |access-date=23 November 2010 |work=[[Toshiba]] |date=April 17, 2007}}</ref> The same month, {{US patent|7923830}} ("Package-on-package secure module having anti-tamper mesh in the substrate of the upper package") was filed by Steven M. Pope and Ruben C. Zeta of [[Maxim Integrated]].<ref name="US7923830"/> In September 2007, [[Hynix Semiconductor]] introduced 24-layer 3D packaging technology, with a 16{{nbsp}}GB flash memory chip that was manufactured with 24 stacked NAND flash chips using a wafer bonding process.<ref>{{cite news |title=Hynix Surprises NAND Chip Industry |url=https://www.koreatimes.co.kr/www/news/biz/2007/09/123_9628.html |access-date=8 July 2019 |work=[[Korea Times]] |date=5 September 2007}}</ref>

==References==
{{reflist|refs=
<ref name="LaPedus_2014">{{cite journal |author-first=Mark |author-last=LaPedus |journal=Semiconductor Engineering |title=Mobile Packaging Market Heats Up |date=2014-06-19 |url=http://semiengineering.com/mobile-packaging-market-heats-up/ |access-date=2016-04-28}}</ref>
<ref name="Thomas_2015">{{cite web |author-first=Glen |author-last=Thomas |location=Indium Corporation |title=Package-on-Package Flux |url=http://www.indium.com/flux-and-epoxy/package-on-package-flux/ |access-date=2015-07-30}}</ref>
<ref name="Amkor_2015">{{cite web |author=Amkor Technology |title=Package on Package (PoP {{!}} PSfvBGA {{!}} PSfcCSP {{!}} TMV® PoP) |url=http://www.amkor.com/go/packaging/all-packages/psvfbga/psvfbga-package-stackable-very-thin-fine-pitch-bga |access-date=2015-07-30}}</ref>
<ref name="US7923830">{{cite web |title=United States Patent US 7,923,830 B2 |date=2011-04-12 |url=https://docs.google.com/viewer?url=patentimages.storage.googleapis.com/pdfs/US7923830.pdf |access-date=2015-07-30}}</ref>
}}

==Further reading==
* [https://web.archive.org/web/20131110013920/http://www.statschippac.com/services/documentlibrary/~/media/Files/DocLibrary/tech_articles/Semiconductor_Intl_PoP_April_2010.ashx ''Innovations push Package on Package into new markets,''] Flynn Carson, Semiconductor International, April 2010
* [https://web.archive.org/web/20080528145157/http://www.practicalcomponents.com/amkor/amkor-pop.htm Practical Components PoP Samples and Test Boards (daisy chains)]
* [https://web.archive.org/web/20081201144058/https://kemasanpack.com/ The Story Behind This Industry Hit (Semiconductor International, 2007-06-01)]
* [http://www.eetimes.com/news/semi/rss/showArticle.jhtml?articleID=209900383&cid=RSSfeed_eetimes_semiRSS Package-on-package is killer app for handsets (EETimes Article July 2008)]
* [http://www.assemblymag.com/CDA/Articles/Feature_Article/BNP_GUID_9-5-2006_A_10000000000000433369 "POP" Goes the Future (Assembly Magazine, 2008-09-30)]
* Package on Package: [https://web.archive.org/web/20161002051233/http://www.statschippac.com/services/packagingservices/3dsdsp/~/media/Files/Package%20Datasheets/POP.ashx Top and Bottom PoP Technologies] 
* [https://web.archive.org/web/20140518084355/http://circuitsassembly.com/cms/component/content/article/207-2010-articles/10618-defects-database PoP Solder Balling (Circuits Assembly Magazine, December 2010)]
* The [http://beagleboard.org/ BeagleBoard] uses a PoP processor
* [http://www.eetimes.com/news/design/showArticle.jhtml?articleID=211201709 Killer app for cell handsets EETimes 2008-10-20]
* [https://web.archive.org/web/20240111134723/https://kemasanpack.com/?desc=topstory TMV: An ‘Enabling’ Technology for Next-Gen PoP Requirements Semicon International 2008-11-04]
* [https://web.archive.org/web/20140518201502/http://circuitsassembly.com/cms/component/content/article/207-2010-articles/10284-defectsdatabase Rolling with Solder Balls (Circuits Assembly Magazine, October 2010)]
* [https://web.archive.org/web/20140516135339/http://circuitsassembly.com/cms/component/content/article/207-2010-articles/10161-defects-database Don't Drown the Part! (Circuits Assembly Magazine, August 2010)]
* [http://smta.org/knowledge/proceedings_abstract.cfm?PROC_ID=2649 POP (Package On Package): An Ems Perspective On Assembly, Rework And Reliability 2009-02-12]
* Hamid Eslampour et al.[https://web.archive.org/web/20110716133912/http://www.statschippac.com/services/documentlibrary/~/media/Files/DocLibrary/whitepapers/STATSChipPAC_ECTC2010_s40p01.ashx ''Comparison of Advanced PoP Package Configurations''], 2010 Electronic Components and Technology Conference (ECTC) Proceedings
* [https://web.archive.org/web/20151122102505/http://packageonpackagebook.com/ Package On Package Assembly Inspection & Quality Control Ebook], Bob Willis

{{Semiconductor packages}}
{{System on a chip}}
[[Category:Semiconductor device fabrication]]
[[Category:Chip carriers]]
[[Category:Packaging (microfabrication)]]