View source for Nios II

{{Short description|Processor architecture}}
{{other uses of|NIOS|Nios (disambiguation)}}
{{More citations needed|date=July 2018}}
{{Infobox CPU architecture
| name       = Nios II
| designer   = [[Altera]]/[[Intel]]
| bits       = 32-bit
| introduced = 
| version    = 
| design     = RISC
| type       = 
| encoding   =
| branching  = 
| endianness = Little-Endian
| extensions = 
| open       = No
| registers  =
| gpr        = 32
}}

'''Nios II''' is a [[32-bit]] embedded processor architecture designed specifically for the [[Altera]] family of [[field-programmable gate array]] (FPGA) [[Integrated circuit|integrated circuits]]. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from [[digital signal processing]] (DSP) to system-control.

Nios II is a successor to Altera's first configurable [[16-bit]] embedded processor [[Nios embedded processor|Nios]], introduced in 2000.<ref>{{cite web|url=https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/pr/nios2_backgrounder.pdf|title=Nios II Embedded Processor Backgrounder|author=Altera}}</ref>

Intel announced the discontinuation of Nios II in 2023, with its successor being [[Nios V]], based on the [[RISC-V]] architecture.<ref>{{Cite web |title=Intel is discontinuing IP ordering codes listed in PDN2312 for Nios® II IP |url=https://www.intel.com/content/www/us/en/content-details/781327/intel-is-discontinuing-ip-ordering-codes-listed-in-pdn2312-for-nios-ii-ip.html |access-date=2025-01-22 |website=Intel}}</ref>

==Key features==
Like the original Nios, the Nios II architecture is a [[RISC]] [[Soft microprocessor|soft-core]] architecture which is implemented entirely in the programmable logic and memory blocks of Altera FPGAs. Unlike its predecessor it is a full [[32-bit_computing|32-bit]] design:

* 32 general-purpose 32-bit registers,
* Full 32-bit instruction set, data path, and address space,
* Single-instruction 32 × 32 multiply and divide producing a 32-bit result.

The soft-core nature of the Nios II processor lets the system designer specify and generate a custom Nios II core, tailored for his or her specific application requirements. System designers can extend the Nios II's basic functionality by, for example, adding a predefined memory management unit, or defining custom instructions and custom peripherals.

=== Custom instructions ===
Similar to native Nios II instructions, user-defined instructions accept values from up to two 32-[[bit]] source registers and optionally write back a result to a 32-bit destination register. By using custom instructions, the system designers can fine-tune the system hardware to meet performance goals and also the designer can easily handle the instruction as a macro in [[C (programming language)|C]].

=== Custom peripherals ===
For performance-critical systems that spend most CPU cycles executing a specific section of code, a user-defined peripheral can potentially offload part or all of the execution of a software-algorithm to user-defined [[hardware logic]], improving power-efficiency or application throughput.

=== Memory Management Unit ===
Introduced with [[Altera Quartus|Quartus]] 8.0, the optional MMU enables Nios II to run operating systems which require hardware-based paging and protection, such as the Linux kernel. Without an MMU, Nios is restricted to operating systems which use a simplified protection and virtual memory-model: e.g., [[μClinux]] and [[FreeRTOS]].

=== Memory Protection Unit ===
Introduced with Quartus 8.0, the optional MPU provides memory protection similar to that provided by an MMU but with a simpler programming model and without the performance overhead associated with an MMU.

== Nios II CPU family ==
Nios II classic is offered in 3 different configurations: Nios II/f (fast), Nios II/s (standard), and Nios II/e (economy).
Nios II gen2 is offered in 2 different configurations: Nios II/f (fast), and Nios II/e (economy).

=== Nios II/f ===
The Nios II/f core is designed for maximum performance at the expense of core size. Features of Nios II/f include:
* Separate instruction and data caches (512&nbsp;[[byte|B]] to 64&nbsp;[[kilobyte|KB]])
* Optional [[memory management unit|MMU]] or [[Memory protection unit|MPU]]
* Access to up to 2&nbsp;[[gigabyte|GB]] of external address space
* Optional tightly coupled memory for instructions and data
* Six-stage pipeline to achieve maximum [[DMIPS]]/MHz
* Single-cycle hardware multiply and barrel shifter
* Optional hardware divide option
* Dynamic [[branch predictor|branch prediction]]
* Up to 256 custom instructions and unlimited hardware accelerators
* [[JTAG]] debug module
* Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace

=== Nios II/s ===
Nios II/s core is designed to maintain a balance between performance and cost. This core implementation is not longer supported for Altera Quartus II v.17 and newer. Features of Nios II/s include:
* Instruction cache
* Up to 2&nbsp;GB of external address space
* Optional tightly coupled memory for instructions
* Five-stage pipeline
* Static branch prediction
* Hardware multiply, divide, and shift options
* Up to 256 custom instructions
* [[JTAG]] debug module
* Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace

=== Nios II/e ===
The Nios II/e core is designed for smallest possible logic utilization of FPGAs. This is especially efficient for low-cost Cyclone II FPGA applications. Features of Nios II/e include:
* Up to 2&nbsp;GB of external address space
* [[JTAG]] debug module
* Complete systems in fewer than 700&nbsp;[[Logic block#Architecture|LE]]s
* Optional debug enhancements
* Up to 256 custom instructions
* Free, no license required

== Avalon switch fabric interface ==
{{Anchor|Avalon}}
Nios II uses the Avalon [[switched fabric|switch fabric]] as the interface to its embedded peripherals. Compared to a traditional bus in a processor-based system, which lets only one bus master access the bus at a time, the Avalon switch fabric, using a slave-side arbitration scheme, lets multiple masters operate simultaneously.

== Development processes ==
Development for Nios II consists of two separate steps: hardware generation and software creation.

Development is hosted inside an Altera application called the Embedded Design Suite (EDS). The EDS contains a complete integrated development environment to manage both hardware and software in two separate steps:

=== Hardware generation process ===
Nios II hardware designers use the Qsys system integration tool, a component of the Quartus-II package, to configure and generate a Nios system. The configuration [[graphical user interface]] (GUI) allows users to choose the Nios-II's feature-set, and to add peripheral and I/O-blocks (timers, memory-controllers, serial interface, etc.) to the embedded system. When the hardware specification is complete, Quartus-II performs the synthesis, place & route to implement the entire system on the selected FPGA target.<br />
Qsys is replacing the older SOPC (System-on-a-Programmable-Chip) Builder, which could also be used to build a Nios II system, and is being recommended for new projects.<ref name=Altera>{{cite web|title=5 Reasons to Switch from SOPC Builder to Qsys|url=http://www.altera.com/education/webcasts/all/wc-2011-reasons-switch-qsys.html|publisher=Altera|access-date=16 March 2012}}</ref>

=== Software creation process ===
A separate package, called the Embedded Design Suite (EDS), manages the software development. Based on the [[Eclipse (software)|Eclipse]] IDE, the EDS includes a C/C++ compiler (based on the [[GNU toolchain]]), debugger, and an instruction-set simulator. EDS allows programmers to test their application in simulation, or download and run their compiled application on the actual FPGA host.

Because the C/C++ development-chain is based on [[GNU Compiler Collection|GCC]], the vast majority of [[Open-source software|open source]] software for [[Linux]] compiles and runs with minimal or no modification. Third-party operating-systems have also been ported to Nios II. These include Micrium [[MicroC/OS-II]], [[eCos]], [[Segger_Microcontroller_Systems|Segger Microcontroller]] embOS, [[ChibiOS/RT]], [[μCLinux]] and [[FreeRTOS]].

GCC 15 removed support for Nios II processors due to Nios II's discontinuation.<ref>{{Cite web |title=GCC 15 Ends Support For Altera Nios II Embedded Processors |url=https://www.phoronix.com/news/GCC-15-Drops-Altera-Nios-II |access-date=2025-01-22 |website=www.phoronix.com |language=en}}</ref>

=== Licensing ===
Nios II is comparable to [[MicroBlaze]], a competing [[Soft microprocessor|softcore CPU]] for the [[Xilinx]] family of FPGA. Unlike MicroBlaze, Nios II is licensable for standard-cell [[Application-specific integrated circuit|ASIC]]s through a third-party IP provider, [[Synopsys]] Designware. Through the Designware license, designers can port Nios-based designs from an FPGA-platform to a mass production ASIC-device.

== See also ==
<!-- see the Talk page for discussion of this section -->
* [[LatticeMico8]]
* [[LatticeMico32]]
* [[MicroBlaze]]
* [[PicoBlaze]]
* [[Micon P200]]

== References ==
{{Reflist}}

== External links ==
*[https://www.intel.com/content/www/us/en/products/details/fpga/nios-processor/ii.html Intel's site about Nios II]
*[https://community.intel.com/t5/Nios-V-II-Embedded-Design-Suite/bd-p/nios-II-embedded-design-suite Nios II Embedded Design Suite forum]
*[https://web.archive.org/web/20090121133048/http://nioswiki.com/ Nios community wiki]
*[[RTEMS]] real-time operating system
*[http://instruct1.cit.cornell.edu/courses/ece576/ Cornell ECE576 Microcontroller course using NiosII]
*[http://www.freertos.org/FreeRTOS-Nios2.html FreeRTOS demo documentation for NiosII]
*[https://sites.google.com/site/ece31289upb/practicas-de-clase/practica-5-nios-ii UPB ECE31289 course using Nios II]

{{Programmable Logic}}
{{RISC-based processor architectures}}
{{Soft microprocessors}}

{{DEFAULTSORT:Nios Ii}}
[[Category:Soft microprocessors]]