View source for Nanocircuitry

{{short description|Electrical circuits operating on the nanometer scale.}}
{{Nanoelec}}
'''Nanocircuits''' are electrical circuits operating on the nanometer scale where quantum mechanical effects become important.  One [[nanometer]] is equal to 10<sup>−9</sup> meters or a row of 10 hydrogen atoms.  With such progressively smaller circuits, more can be fitted on a computer chip.  This allows faster and more complex functions using less power.  Nanocircuits are composed of three different fundamental components.  These are [[transistors]], [[Transmission line|interconnections]], and [[Computer architecture|architecture]], all fabricated on the nanometer scale.

== Various approaches to nanocircuitry==
A variety of proposals have been made to implement nanocircuitry in different forms. These include [[Nanowires]], [[Coulomb blockade|Single-Electron Transistors]], [[Quantum dot cellular automata]], and Nanoscale [[Crossbar latch|Crossbar Latches]]. However, likely nearer-term approaches will involve incorporation of nanomaterials to improve [[MOSFETs]] (metal–oxide–semiconductor field-effect transistors). These currently form the basis of most analog and digital circuit designs, the scaling of which drives [[Moore's Law]]. A review article<ref>Colinge, J., Multiple-gate SOI MOSFETs, Solid-State Electronics 48, 2004</ref> covering the MOSFET design and its future was published in 2004 comparing different geometries of MOSFETs under scale reduction and noted that circular cross-section vertical channel FETs are optimal for scale reduction. This configuration is capable of being implemented with a high density using vertical semiconductor cylindrical channels with nanoscale diameters and [[Infineon Technologies]] and [[Samsung]] have begun research and development in this direction resulting in some basic patents<ref>{{US patent|6740910}}</ref><ref>{{US patent|6566704}}</ref> using [[nanowires]] and [[carbon nanotubes]] in MOSFET designs. In an alternative approach,<ref>{{US patent|7135728}}</ref> [[Nanosys]] uses solution based deposition and alignment processes to pattern pre-fabricated arrays of nanowires on a substrate to serve as a lateral channel of an FET. While not capable of the same scalability as single nanowire FETs, the use of pre-fabricated multiple nanowires for the channel increases reliability and reduces production costs since large volume printing processes may be used to deposit the nanowires at a lower temperature than conventional fabrication procedures. In addition, due to the lower temperature deposition a wider variety of materials such as polymers may be used as the carrier substrate for the transistors opening the door to flexible electronic applications such as electronic paper, bendable flat panel displays, and wide area solar cells.

== Production methods ==
One of the most fundamental concepts to understanding nanocircuits is the formulation of [[Moore’s Law]].  This concept arose when Intel co-founder [[Gordon Moore]] became interested in the cost of transistors and trying to fit more onto one chip.  It relates that the number of transistors that can be fabricated on a silicon integrated circuit—and therefore the computing abilities of such a circuit—is doubling every 18 to 24 months.<ref>Stokes, Jon. ”[https://arstechnica.com/articles/paedia/cpu/moore.ars/1 Understanding Moore's Law]","ars technica", 2003-02-20. Retrieved on March 23, 2007.</ref> The more transistors one can fit on a circuit, the more computational abilities the computer will have.  This is why scientists and engineers are working together to produce these nanocircuits so increasingly more and more transistors will be able to fit onto a chip.  Despite how good this may sound, there are many problems that arise when so many transistors are packed together.  With circuits being so tiny, they tend to have more problems than larger circuits, more particularly heat - the amount of power applied over a smaller surface area makes heat dissipation difficult, this excess heat will cause errors and can destroy the chip.  Nanoscale circuits are more sensitive to temperature changes, [[cosmic rays]] and [[Electromagnetic radiation|electromagnetic]] interference than today's circuits.<ref>Patch, Kimberly. “[http://www.trnmag.com/Stories/2003/032603/Design_handles_iffy_nanocircuits_032603.html Design handles iffy nanocircuits]","TRN",2003-03-26. Retrieved on March 23, 2007.</ref>  As more transistors are packed onto a chip, phenomena such as stray signals on the chip, the need to dissipate the heat from so many closely packed devices, tunneling across insulation barriers due to the small scale, and fabrication difficulties will halt or severely slow progress.<ref>Patch, retrieved on March 23, 2007.</ref> There will be a time when the cost of making circuits even smaller will be too much, and the speed of computers will reach a maximum.  For this reason, many scientists believe that Moore’s Law will not hold forever and will soon reach a peak, since Moore's law is largely predicated on computational gains caused by improvements in micro-lithographic etching technologies. 
 
In producing these nanocircuits, there are many aspects involved.  The first part of their organization begins with transistors.  As of right now, most electronics are using silicon-based transistors.  Transistors are an integral part of circuits as they control the flow of electricity and transform weak electrical signals to strong ones.  They also control electric current as they can turn it on off, or even amplify signals.  Circuits now use silicon as a transistor because it can easily be switched between conducting and nonconducting states.  However, in [[nanoelectronics]], transistors might be organic molecules or nanoscale inorganic structures.<ref>Eds. Scientific American, Understanding Nanotechnology (New York: Warner Books, 2002) p.93.</ref>  [[Semiconductors]], which are part of transistors, are also being made of organic molecules in the nano state.

The second aspect of nanocircuit organization  is interconnection.  This involves logical and mathematical operations and the wires linking the transistors together that make this possible.  In nanocircuits, [[Carbon nanotube|nanotubes]] and other wires as narrow as one nanometer are used to link transistors together.  [[Nanowires]] have been made from carbon nanotubes for a few years.  Until a few years ago, transistors and nanowires were put together to produce the circuit.  However, scientists have been able to produce a nanowire with transistors in it.  In 2004, Harvard University nanotech pioneer Charles Lieber and his team have made a nanowire—10,000 times thinner than a sheet of paper—that contains a string of transistors.<ref>Pescovitz, David.“[http://www.boingboing.net/2004/07/01/nanowires_with_built.html Nanowires with built-in transistors] {{webarchive|url=https://web.archive.org/web/20070803044357/http://www.boingboing.net/2004/07/01/nanowires_with_built.html |date=2007-08-03 }}","boing boing", 2004-07-01. Retrieved on March 23, 2007.
</ref> Essentially, transistors and nanowires are already pre-wired so as to eliminate the difficult task of trying to connect transistors together with nanowires.

The last part of nanocircuit organization is architecture.  This has been explained as the overall way the transistors are interconnected, so that the circuit can plug into a computer or other system and operate independently of the lower-level details.<ref>Eds. Scientific American, 93.
</ref>  With nanocircuits being so small, they are destined for error and defects.  Scientists have devised a way to get around this.  Their architecture combines circuits that have redundant [[logic gates]] and interconnections with the ability to reconfigure structures at several levels on a chip.<ref>Patch, retrieved on March 23, 2007.</ref>  The redundancy lets the circuit identify problems and reconfigure itself so the circuit can avoid more problems.  It also allows for errors within the logic gate and still have it work properly without giving a wrong result.

== Experimental breakthroughs and potential applications ==
{{See|Nanoelectronics|History of nanotechnology}}

In 1987, an [[IBM]] research team led by [[Bijan Davari]] demonstrated a [[metal–oxide–semiconductor field-effect transistor]] (MOSFET) with a [[10 nm process|10 nm]] gate oxide thickness, using [[tungsten]]-gate technology.<ref name="Davari1987">{{cite journal |last1=Davari |first1=Bijan |author1-link=Bijan Davari |last2=Ting |first2=Chung-Yu |last3=Ahn |first3=Kie Y. |last4=Basavaiah |first4=S. |last5=Hu |first5=Chao-Kun |last6=Taur |first6=Yuan |last7=Wordeman |first7=Matthew R. |last8=Aboelfotoh |first8=O. |last9=Krusin-Elbaum |first9=L. |last10=Joshi |first10=Rajiv V. |last11=Polcari |first11=Michael R. |title=Submicron Tungsten Gate MOSFET with 10 nm Gate Oxide |journal=1987 Symposium on VLSI Technology. Digest of Technical Papers |date=1987 |pages=61–62 |url=https://ieeexplore.ieee.org/document/4480422}}</ref> [[Multi-gate MOSFET]]s enabled [[MOSFET scaling|scaling]] below [[20 nm]] gate length, starting with the [[FinFET]] (fin field-effect transistor), a three-dimensional, non-planar, double-gate MOSFET.<ref name="Liu" /> The FinFET originates from the research of Digh Hisamoto at [[Hitachi|Hitachi Central Research Laboratory]] in 1989.<ref name="Colinge">{{cite book |last1=Colinge |first1=J.P. |title=FinFETs and Other Multi-Gate Transistors |date=2008 |publisher=Springer Science & Business Media |isbn=9780387717517 |page=11 |url=https://books.google.com/books?id=t1ojkCdTGEEC&pg=PA11}}</ref><ref>{{cite book |last1=Hisamoto |first1=D. |last2=Kaga |first2=T. |last3=Kawamoto |first3=Y. |last4=Takeda |first4=E. |title=International Technical Digest on Electron Devices Meeting |chapter=A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET |date=December 1989 |pages=833–836 |doi=10.1109/IEDM.1989.74182|s2cid=114072236 }}</ref><ref>{{cite web |title=IEEE Andrew S. Grove Award Recipients |url=https://www.ieee.org/about/awards/bios/grove-recipients.html |archive-url=https://web.archive.org/web/20180909112404/https://www.ieee.org/about/awards/bios/grove-recipients.html |url-status=dead |archive-date=September 9, 2018 |website=[[IEEE Andrew S. Grove Award]] |publisher=[[Institute of Electrical and Electronics Engineers]] |access-date=4 July 2019}}</ref><ref name="intel">{{cite web |title=The Breakthrough Advantage for FPGAs with Tri-Gate Technology |url=https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01201-fpga-tri-gate-technology.pdf |publisher=[[Intel]] |year=2014 |access-date=4 July 2019}}</ref> At [[University of California, Berkeley|UC Berkeley]], FinFET devices were fabricated by a group consisting of Hisamoto along with [[TSMC]]'s [[Chenming Hu]] and other international researchers including [[Tsu-Jae King Liu]], [[Jeffrey Bokor]], Hideki Takeuchi, K. Asano, Jakub Kedziersk, Xuejue Huang, Leland Chang, Nick Lindert, Shibly Ahmed and Cyrus Tabery. The team fabricated FinFET devices down to a [[16 nanometer|17{{nbsp}}nm]] process in 1998, and then [[16 nanometer|15{{nbsp}}nm]] in 2001. In 2002, a team including Yu, Chang, Ahmed, Hu, Liu, Bokor and Tabery fabricated a [[10 nanometer|10{{nbsp}}nm]] FinFET device.<ref name="Liu">{{cite web |last1=Tsu-Jae King |first1=Liu |authorlink1=Tsu-Jae King Liu |title=FinFET: History, Fundamentals and Future |url=https://people.eecs.berkeley.edu/~tking/presentations/KingLiu_2012VLSI-Tshortcourse |website=[[University of California, Berkeley]] |publisher=Symposium on VLSI Technology Short Course |date=June 11, 2012 |access-date=9 July 2019}}</ref>

In 2005, Indian physicists Prabhakar Bandaru and Apparao M. Rao at [[University of California, San Diego|UC San Diego]] developed the world's smallest transistor based to be made entirely from [[carbon nanotubes]]. It was intended to be used for nanocircuits. [[Nanotubes]] are rolled up sheets of carbon atoms and are more than a thousand times thinner than human hair.{{cn|date=April 2024}} In 2006, a team of Korean researchers from the [[KAIST|Korea Advanced Institute of Science and Technology]] (KAIST) and the National Nano Fab Center developed a [[3&nbsp;nm]] MOSFET, the world's smallest [[nanoelectronic]] device, based on [[gate-all-around]] (GAA) FinFET technology.<ref>{{citation|url=http://www.highbeam.com/doc/1G1-145838158.html|archive-url=https://web.archive.org/web/20121106011401/http://www.highbeam.com/doc/1G1-145838158.html|url-status=dead|archive-date=6 November 2012|title=Still Room at the Bottom (nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology)|date=1 April 2006|work=Nanoparticle News|access-date=24 September 2019}}</ref><ref>{{Cite book|first=Hyunjin |last=Lee |title=2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers |chapter=Sub-5nm All-Around Gate FinFET for Ultimate Scaling |year=2006 |pages=58–59 |doi=10.1109/VLSIT.2006.1705215 |display-authors=etal|isbn=978-1-4244-0005-8 |hdl=10203/698 |s2cid=26482358 |hdl-access=free }}</ref>

Normally, circuits use [[silicon]]-based transistors, but carbon nanotubes are intended to replace those.  The transistor has two different branches that meet at a single point, hence giving it a Y shape.  Current can flow throughout both branches and is controlled by a third branch that turns the voltage on or off.  This new breakthrough can now allow for nanocircuits to hold completely to their name as they can be made entirely from nanotubes.  Before this discovery, logic circuits used nanotubes, but needed metal gates to be able to control the flow of [[electric current]].

Arguably the biggest potential application of nanocircuits deals with computers and electronics.  Scientists and engineers are always looking to make computers faster.  Some think in the nearer term, we could see hybrids of [[micro-]] and nano-: [[silicon]] with a nano core—perhaps a high-density computer memory that retains its contents forever.<ref>Eds. Scientific American, 93.</ref>  Unlike conventional circuit design, which proceeds from blueprint to photographic pattern to chip, nanocircuit design will probably begin with the chip—a haphazard jumble of as many as 1024 components and wires, not all of which will even work—and gradually sculpt it into a useful device.<ref>Eds. Scientific American, 94.
</ref>  Instead of taking the traditional [[Top-down and bottom-up design#Nanotechnology|top-down]] approach, the [[Top-down and bottom-up design#Nanotechnology|bottom-up]] approach will probably soon have to be adopted because of the sheer size of these nanocircuits.  Not everything in the circuit will probably work because at the nano level, nanocircuits will be more defective and faulty because of their compactness.  Scientists and engineers have created all of the essential components of nanocircuits such as transistors, logic gates and diodes.  They have all been constructed from [[organic molecules]], carbon nanotubes and nanowire semiconductors.  The only thing left to do is find a way to eliminate the errors that come with such a small device and nanocircuits will become a way of all electronics.  However, eventually there will be a limit as to how small nanocircuits can become and computers and electronics will reach their equilibrium speeds.

==See also==
*[[Moore's Law]]
*[[Nanotechnology]]
*[[History of nanotechnology]]
*[[List of nanotechnology applications]]
*[[Implications of nanotechnology]]

== References ==
{{Reflist}}

{{Breakthrough of the Year}}

[[Category:Nanoelectronics]]