View source for NAND gate

{{Short description|Logical gate whose output is false if all its inputs are true}}
{{One source|date=July 2023}}
{| class="wikitable floatright" style="text-align:center"
|-
! colspan="3" | NAND gate [[truth table]]
|- bgcolor="#ddeeff"
|colspan=2|'''Input''' || '''Output'''
|- bgcolor="#ddeeff"
| A || B || A NAND B
|-
|{{no2|0}} || {{no2|0}} || {{yes2|1}}
|-
|{{no2|0}} || {{yes2|1}} || {{yes2|1}}
|-
|{{yes2|1}} || {{no2|0}} || {{yes2|1}}
|-
|{{yes2|1}} || {{yes2|1}} || {{no2|0}}
|}

In [[digital electronics]], a '''NAND''' ('''NOT AND''') '''gate''' is a [[logic gate]] which produces an output which is false only if all its inputs are true; thus its output is [[Complement (set theory)|complement]] to that of an [[AND gate]]. A LOW (0) output results only if all the inputs to the gate are HIGH (1); if any input is LOW (0), a HIGH (1) output results. A NAND gate is made using transistors and junction diodes. By [[De Morgan's laws]], a two-input NAND gate's logic may be expressed as <math>\overline{A} \lor \overline{B} = \overline{A \cdot B}</math>, making a NAND gate equivalent to [[Inverter (logic gate)|inverters]] followed by an [[OR gate]].

The NAND gate is significant because any [[Boolean function]] can be implemented by using a combination of NAND gates. This property is called "[[functional completeness]]". It shares this property with the [[NOR gate]]. Digital systems employing certain logic circuits take advantage of NAND's functional completeness.

NAND gates with two or more inputs are available as [[integrated circuit]]s in [[transistor–transistor logic]], [[CMOS]], and other [[logic family|logic families]].

== Symbols ==
There are three symbols for NAND gates: the ''MIL/[[ANSI]]'' symbol, the ''[[International Electrotechnical Commission|IEC]]'' symbol and the deprecated ''[[DIN]]'' symbol sometimes found on old schematics. The ANSI symbol for the NAND gate is a standard AND gate with an inversion bubble connected.

{| align=center style="text-align:center"
|[[File:NAND ANSI Labelled.svg]]
|[[File:NAND IEC.svg]]
|[[file:NAND DIN.svg]]
|-
|''MIL/ANSI Symbol''&nbsp;&nbsp;&nbsp;
|''IEC Symbol''&nbsp;&nbsp;&nbsp;
|''DIN Symbol''
|}

== Logic ==

The function {{nowrap|NAND(''a''<sub>1</sub>, ''a''<sub>2</sub>, ..., ''a<sub>n</sub>'')}} is [[Logical equivalence|logically equivalent]] to {{nowrap|NOT(''a''<sub>1</sub> AND ''a''<sub>2</sub> AND ... AND ''a<sub>n</sub>'').}}

One way of expressing A NAND B is <math>\overline{A \land B}</math>, where the symbol <math>{\land}</math> signifies AND and the bar signifies the negation of the expression under it: in essence, simply <math>{\displaystyle \lnot (A \land B)}</math>.

== Implementations ==
The basic implementations can be understood from the image on the left below: If either of the switches S1 or S2 is open, the [[pull-up resistor]] R will set the output signal Q to 1 (high). If S1 and S2 are both closed, the pull-up resistor will be overridden by the switches, and the output will be 0 (low).

In the [[depletion-load NMOS logic]] realization in the middle below, the switches are the transistors T2 and T3, and the transistor T1 fulfills the function of the pull-up resistor.

In the [[CMOS]] realization on the right below, the switches are the [[Extrinsic_semiconductor#N-type_semiconductors|n-type]] transistors T3 and T4, and the pull-up resistor is made up of the [[Extrinsic_semiconductor#Ptype_semiconductors|p-type]] transistors T1 and T2, which form the complement of transistors T3 and T4.

<gallery class="center" caption="Realization of NAND gates in different logic families" perrow="3">
Funktionsprinzip eines NAND-Gatters.svg|Implementation using switches and a pull-up resistor
Nmos enhancement saturated nand.svg|[[Depletion-load NMOS logic|NMOS]]
Cmos nand.svg|[[CMOS]]
</gallery>

In CMOS, NAND gates are more efficient than [[NOR gate|NOR gates]]. This is due to the faster charge mobility in n-MOSFETs compared to p-MOSFETs, so that the parallel connection of two p-MOSFETs (T1 and T2) realised in the NAND gate is more favourable than their series connection in the NOR gate. For this reason, NAND gates are generally preferred over NOR gates in CMOS circuits.<ref>{{Cite web |title=Digital circuits, sizing, output impedance, rise and fall time. |url=https://inst.eecs.berkeley.edu/~ee105/sp04/handouts/lectures/Lecture18.pdf |last=Smith |first=J.S. |archive-url=https://web.archive.org/web/20070706145946/https://inst.eecs.berkeley.edu/~ee105/sp04/handouts/lectures/Lecture18.pdf |archive-date=2007-07-06 }}</ref>

== Hardware design and pinout ==
[[Image:4011 Pinout.svg|thumb|Diagram of the NAND gates in a CMOS type 4011 integrated circuit]]

NAND gates are basic logic gates, and as such they are recognised in [[Transistor–transistor logic|TTL]] and [[CMOS]] [[integrated circuit|IC]]s.

The standard, [[4000 series]], [[CMOS]] [[integrated circuit|IC]] is the 4011, which includes four independent, two-input, NAND gates. These devices are available from many semiconductor manufacturers. These are usually available in both through-hole [[Dual in-line package|DIL]] and [[small Outline Integrated Circuit|SOIC]] formats. Datasheets are readily available in most [[datasheet#Datasheet Search Engines|datasheet databases]].

The standard two-, three-, four- and eight-input NAND gates are available:

* [[CMOS]]
** 4011: Quad two-input NAND gate
** 4023: Triple three-input NAND gate
** 4012: Dual four-input NAND gate
** 4068: Mono eight-input NAND gate
* [[Transistor–transistor logic|TTL]]
** 7400: Quad two-input NAND gate
** 7410: Triple three-input NAND gate
** 7420: Dual four-input NAND gate
** 7430: Mono eight-input NAND gate

== Functional completeness ==
[[file:NAND from NOR.svg|thumb|Construction of a NAND gate from NOR gates]]
{{main|NAND logic|NOR logic}}

The NAND gate has the property of [[functional completeness]], which it shares with the [[NOR Gate|NOR gate]]. That is, any other logic function (AND, OR, etc.) can be implemented using only NAND gates.<ref name="Mano">Mano, M. Morris and Charles R. Kime. ''Logic and Computer Design Fundamentals, Third Edition.'' Prentice Hall, 2004. p. 73.</ref> An entire processor can be created using NAND gates alone. In TTL ICs using multiple-emitter [[transistors]], it also requires fewer transistors than a NOR gate.

As NOR gates are also functionally complete, if no specific NAND gates are available, one can be made from [[NOR Gate|NOR]] gates using [[NOR logic]].<ref name="Mano" />

== See also ==
* [[Boolean algebra]]
* [[Flash memory]]
* [[logic gate#Symbols|Logic gate symbols]]
* [[Sheffer stroke]]

== References ==
{{refs}}

== External links ==
{{commonscat|NAND gates}}

* [http://www.allaboutcircuits.com/vol_4/chpt_3/5.html TTL NAND and AND gates] at All About Circuits

{{Logical connectives}}

[[Category:Logic gates|NAND gate]]