View source for MicroSPARC

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{{Infobox CPU
| name           = microSPARC
| image          =
| image_size     =
| caption        =
| produced-start = 1992
| produced-end   = 1994
| slowest        = 40
| fastest        = 125
| slow-unit      = MHz
| fast-unit      = MHz
| fsb-slowest    = 
| fsb-fastest    = 
| fsb-slow-unit  = 
| fsb-fast-unit  = 
| size-from      = 
| size-to        = 
| soldby         =
| designfirm     = [[Sun Microsystems]]
| manuf1         = 
| core1          = 
| sock1          = 
| pack1          =
| arch           = [[SPARC]] V8
| microarch      = 
| numcores       = 1
}}

The '''microSPARC''' (code-named ''Tsunami'') is a discontinued [[microprocessor]] implementing the [[SPARC|SPARC V8]] [[instruction set architecture]] (ISA), developed by [[Sun Microsystems]]. It is a low-end microprocessor intended for low-end [[workstation]]s and [[embedded system]]s. The microprocessor was developed by Sun, but the [[floating-point unit]] (FPU) was licensed from [[Meiko Scientific#Meiko SPARC FPU | Meiko Scientific]]. It contains 800,000 transistors.  It was used in the [[SPARCclassic]] and [[SPARCstation LX]] among others.

There are two variants of the '''microSPARC-II''' (code-named ''Swift''): the microSPARC-II and microSPARC-IIep. The microSPARC-II is used in the [[SPARCstation 5]]. The microSPARC-IIep is a 100&nbsp;MHz microSPARC-II with an integrated [[Peripheral Component Interconnect|PCI]] controller for [[embedded system]]s. It was developed and fabricated by [[LSI Logic]] for Sun, and used in their [[JavaStation]] [[Network Computer]].

{| class="wikitable sortable"
|- style="vertical-align: top; font-size: 85%;"
!                            Name (codename)
!                            Model
! abbr="Frequency"         | Frequency (MHz)
! abbr="Architecture"      | Arch. version
!                            Year
! abbr="Threads"           | Total threads<ref name=threads>Threads per core × number of cores</ref>
! abbr="Process"           | Process (μm)
! abbr="Transistors"       | Transistors (millions)
! abbr="Size"              | Die size (mm²)
!                            IO Pins
! abbr="Power"             | Power (W)
! abbr="Voltage"           | Voltage (V)
! abbr="Data cache"        | L1 Dcache (k)
! abbr="Instruction cache" | L1 Icache (k)
! abbr="L2 Cache"          | L2 Cache (k)
! abbr="L3 Cache"          | L3 Cache (k)
|-
!microSPARC I (Tsunami)
|TI TMS390S10 / TMX390S10
|40&ndash;50||V8||1992||1×1=1||0.8||0.8||225?||288||2.5||5||2||4||none||none
|-
!microSPARC II (Swift)
|Fujitsu MB86904 / Sun STP1012
|60&ndash;125||V8||1994||1×1=1||0.5||2.3||233||321||5||3.3||8||16||none||none
|}

<gallery caption="Die photos" mode=packed heights=200px>
Image:TI_microSPARC_I_die.jpg|TI microSPARC I
Image:Sun_microSPARC_II_die.JPG|Sun microSPARC II
</gallery>

== References ==
{{Reflist}}
* [[Sun Microsystems, Inc.]] (10 August 1992). "Highly Integrated SPARC Processor Implementation (Tsunami)". Hot Chips presentation.'

{{Sun hardware}}

[[Category:Sun microprocessors]]
[[Category:SPARC microprocessors]]
[[Category:32-bit microprocessors]]
[[Category:Computer-related introductions in 1992]]

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