View source for MicroBlaze

{{Short description|Microprocessor core}}
{{refimprove|date=August 2018}}
{{Infobox CPU architecture
| name       = MicroBlaze
| designer   = [[Xilinx]]
| bits       = [[32-bit]]/[[64-bit]] (32 → 64)
| introduced = 
| version    = 11.0
| design     = RISC
| type       = 
| encoding   = Fixed
| branching  = 
| endianness = Little (Big)
| extensions = 
| open       = No
| registers  = 32 × 32 bits
}}
The '''MicroBlaze''' is a [[soft microprocessor]] core designed for [[Xilinx]] [[field-programmable gate array]]s (FPGA).  As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs.

MicroBlaze was introduced in 2002.<ref>{{cite web|url=https://www.ee.ryerson.ca/~courses/ee8205/Data-Sheets/sopc/MicroBlaze_DataSheet.pdf|title=MicroBlaze RISC 32-Bit Soft Processor datasheet|author=[[Xilinx]]|date=August 21, 2002}}</ref>

==Overview==
In terms of its instruction set architecture, MicroBlaze is similar to the [[Reduced instruction set computer|RISC]]-based [[DLX]] architecture described in a popular computer architecture book by [[David A. Patterson (scientist)|Patterson]] and [[John L. Hennessy|Hennessy]].  With few exceptions, the MicroBlaze can issue a new instruction every cycle, maintaining single-cycle throughput under most circumstances.

The MicroBlaze has a versatile interconnect system to support a variety of embedded applications.  MicroBlaze's primary I/O bus, the [[Advanced Microcontroller Bus Architecture|AXI interconnect]], is a system-memory mapped transaction bus with master–slave capability. Older versions of the MicroBlaze used the [[CoreConnect]] PLB bus. The majority of vendor-supplied and third-party IP interface to AXI directly (or through an AXI interconnect).  For access to local-memory (FPGA [[RAM]]), MicroBlaze uses a dedicated LMB bus, which provides fast on-chip storage.  User-defined coprocessors are supported through dedicated AXI4-Stream connections.  The coprocessor(s) interface can accelerate computationally intensive algorithms by offloading parts or the entirety of the computation to a user-designed hardware module.

Many aspects of the MicroBlaze can be user configured: cache size, pipeline depth (3-stage, 5-stage, or 8-stage), embedded peripherals, [[memory management unit]], and bus-interfaces can be customized.  The area-optimized version of MicroBlaze, which uses a 3-stage pipeline, sacrifices clock frequency for reduced logic area.  The performance-optimized version expands the execution pipeline to 5 stages, allowing top speeds of more than 700 [[MHz]] (on Virtex UltraScale+ [[Field-programmable gate array|FPGA]] family).  Also, key [[Application-specific instruction set processor|processor instructions]] which are rarely used but more expensive to implement in hardware can be selectively added/removed (e.g. multiply, divide, and floating point operations).  This customization enables a developer to make the appropriate design trade-offs for a specific set of host hardware and application software requirements.

With the memory management unit, MicroBlaze is capable of hosting operating systems requiring hardware-based paging and protection, such as the [[Linux kernel]]. Otherwise it is limited to operating systems with a simplified protection and virtual memory model, e.g. [[FreeRTOS]] or [[μClinux | Linux without MMU support]]. MicroBlaze's overall throughput is substantially less than a comparable hard CPU core (such as the [[ARM Cortex-A9]] in the [[Zynq-7000|Zynq]]).

MicroBlaze V is based on the [[RISC-V]] architecture.

==Vivado==
Xilinx's [[Xilinx Vivado|Vivado Design Suite]] is the development environment for building current MicroBlaze (or [[ARM architecture|ARM]] - see Zynq) embedded processor systems in Xilinx FPGAs. Older versions used Xilinx's EDK (Embedded Development Kit) development package.

Designers use the Vivado IP Integrator to configure and build the hardware specification of their embedded system (processor core, memory-controller, I/O peripherals, etc.)  The IP Integrator converts the designer's block design into a synthesizeable [[Register transfer level|RTL]] description ([[Verilog]] or [[VHDL]]), and automates the implementation of the embedded system (from RTL to the bitstream-file.)  For the MicroBlaze core, Vivado generates an encrypted (non human-readable) netlist.

The SDK handles the software that will execute on the embedded system. Powered by the [[GNU toolchain]] ([[GNU Compiler Collection]], [[GNU Debugger]]), the SDK enables programmers to write, compile, and debug C/C++ applications for their embedded system.  Xilinx's tools provides the possibility of running software in simulation, or using a suitable FPGA-board to download and execute on the actual system.

Purchasers of Vivado are granted a perpetual license to use MicroBlaze in Xilinx FPGAs with no recurring royalties.  The license does not grant the right to use MicroBlaze outside of Xilinx's devices.

Alternative compilers and development tools have been made available from [[Altium]] but an EDK installation and license is still required.

==Open source==

In June 2009, MicroBlaze became the first soft-CPU architecture to be merged into the mainline Linux kernel source tree.  This work was performed by Michal Simek and supported by PetaLogix and Xilinx.

As of September 2009, MicroBlaze GNU tools support is also being contributed to the Free Software Foundation's mainline repositories. Support for MicroBlaze is included in GCC releases starting with version 4.6<ref>{{cite web
| url         = https://gcc.gnu.org/gcc-4.6/changes.html#microblaze
| title       = GCC 4.6 Release Series Changes, New Features, and Fixes
| date        = 2011-03-15
| access-date  = 2011-03-15
| quote       = Support has been added for the Xilinx MicroBlaze softcore processor (microblaze-elf) embedded target.
}}</ref>

Support was added to [[LLVM]] in April 2010,<ref>{{Cite web|url=https://releases.llvm.org/2.7/docs/ReleaseNotes.html|title=LLVM 2.7 Release Notes|website=releases.llvm.org|access-date=2019-04-07}}</ref> but subsequently removed in July 2013<ref>{{Cite web|url=http://lists.llvm.org/pipermail/llvm-dev/2013-July/064126.html|title=[LLVMdev] Deprecating and removing the MBlaze backend|last=Christopher|first=Eric|date=2013-07-24|access-date=2019-04-07}}</ref> due to a lack of maintainer.

==Clones==
* aeMB, implemented in Verilog, [[LGPL|LGPL license]]
* OpenFire subset, implemented in Verilog, [[MIT license]]
* MB-Lite, implemented in VHDL, LGPL license
* MB-Lite+, implemented in VHDL, LGPL license
* myBlaze, implemented in [[MyHDL]], LGPL license
* SecretBlaze, implemented in VHDL, [[GPL|GPL license]]

==Other soft processors==
* [[Nios II]]
* TSK3000
* [[Xtensa]]
* [[LatticeMico32]]
* [[ARC (processor)|ARC]]
* [[RISC-V]] (A number of open source soft cores are available. At least one is [https://github.com/eugene-tarassov/vivado-risc-v packaged for Vivado].)
* [[ARM Cortex-M]] (Cortex-M1 and Cortex-M3 soft cores are available in Vivado)
* [[OpenPOWER Microwatt]]

==See also==
* [[OpenCores]] - a home for many [[Open-source model|open source]] [[soft processor]] projects
* [[PicoBlaze]]
* {{section link|Advanced Microcontroller Bus Architecture|Advanced eXtensible Interface (AXI)}}

==References==
<references/>

==External links==
* [https://www.xilinx.com/microblaze/ MicroBlaze on Xilinx website]{{cbignore|bot=medic}}

{{RISC-based processor architectures}}
{{Soft microprocessors}}
{{Programmable Logic}}
{{CPU technologies}}

[[Category:Soft microprocessors]]