View source for Memory-level parallelism

{{Short description|Computer architecture feature}}
In [[computer architecture]], '''memory-level parallelism''' ('''MLP''') is the ability to have pending multiple [[Computer memory|memory]] operations, in particular [[CPU cache|cache]] misses or [[translation lookaside buffer]] (TLB) misses, at the same time.

In a single processor, MLP may be considered a form of [[instruction-level parallelism]] (ILP). However, ILP is often conflated with [[superscalar]], the ability to execute more than one instruction at the same time, e.g. a processor such as the Intel [[Pentium Pro]] is five-way superscalar, with the ability to start executing five different microinstructions in a given cycle, but it can handle four different cache misses for up to 20 different load microinstructions at any time.

It is possible to have a machine that is not superscalar but which nevertheless has high MLP. 

Arguably a machine that has no ILP, which is not superscalar, which executes one instruction at a time in a non-pipelined manner, but which performs hardware prefetching (not software instruction-level prefetching) exhibits MLP (due to multiple prefetches outstanding) but not ILP. This is because there are multiple memory ''operations'' outstanding, but not ''instructions''. Instructions are often conflated with operations.

Furthermore, multiprocessor and multithreaded computer systems may be said to exhibit MLP and ILP due to parallelism—but not intra-thread, single process, ILP and MLP. Often, however, we restrict the terms MLP and ILP to refer to extracting such parallelism from what appears to be non-parallel single threaded code.

==See also==
*[[Memory disambiguation]]
*[[Memory dependence prediction]]
*[[Hardware scout]]
*[[Runahead]]

==References==
*{{Cite conference |last1=Glew |first1=A. |year=1998 |title=MLP yes! ILP no! |book-title=ASPLOS Wild and Crazy Idea Session '98
 |department=Wild and Crazy Ideas (WACI) I |conference=[[International Conference on Architectural Support for Programming Languages and Operating Systems|ASPLOS]] VIII |postscript=. ([http://www.cs.berkeley.edu/~kubitron/asplos98/abstracts/andrew_glew.pdf abstract] / [http://www.cs.berkeley.edu/~kubitron/asplos98/slides/andrew_glew.pdf slides])}}
*{{Cite journal |last1=Ronen |first1=R. |last2=Mendelson |first2=A. |last3=Lai |first3=K. |last4=Shih-Lien Lu |last5=Pollack |first5=F. |last6=Shen |first6=J. P. |year=2001 |title=Coming challenges in microarchitecture and architecture |journal=[[Proceedings of the IEEE|Proc. IEEE]] |volume=89 |issue=3 |pages=325–340 |citeseerx=10.1.1.136.5349 |doi=10.1109/5.915377}}
*{{Cite conference |last1=Zhou |first1=H. |last2=Conte |first2=T. M. |year=2003 |title=Enhancing memory level parallelism via recovery-free value prediction |book-title=Proceedings of the 17th annual international conference on Supercomputing |conference=[[International Supercomputing Conference|ICS]]'03 |pages=326–335 |citeseerx=10.1.1.14.4405 |doi=10.1145/782814.782859 |isbn=1-58113-733-8}}
*{{Cite conference |last1=Yuan Chou |last2=Fahs |first2=B. |last3=Abraham |first3=S. |year=2004 |title=Microarchitecture optimizations for exploiting memory-level parallelism |book-title=Proceedings. 31st Annual International Symposium on Computer Architecture, 2004 |conference=[[International Symposium on Computer Architecture|ISCA]]'04 |pages=76–87 |citeseerx=10.1.1.534.6032 |doi=10.1109/ISCA.2004.1310765 |isbn=0-7695-2143-6}}
*{{Cite conference |last1=Qureshi |first1=M. K. |last2=Lynch |first2=D. N. |last3=Mutlu |first3= O. |last4=Patt |first4=Y. N. |year=2006 |title=A Case for MLP-Aware Cache Replacement |book-title=33rd International Symposium on Computer Architecture |conference=[[International Symposium on Computer Architecture|ISCA]]'06 |pages=167–178 |citeseerx=10.1.1.94.4663 |doi=10.1109/ISCA.2006.5 |isbn=0-7695-2608-X}}
*{{Cite conference |last1=Van Craeynest |first1=K. |last2=Eyerman |first2=S. |last3=Eeckhout |first3=L. |year=2009 |title=MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor |book-title=High Performance Embedded Architectures and Compilers |conference=[[International Conference on High Performance Embedded Architectures and Compilers|HiPEAC]] 2009 |series=[[Lecture Notes in Computer Science|LNCS]] |volume=5409 |pages=110–124 |citeseerx=10.1.1.214.3261 |doi=10.1007/978-3-540-92990-1_10 |isbn=978-3-540-92989-5}}

{{Parallel Computing}}
{{CPU technologies}}

[[Category:Instruction processing]]
[[Category:Parallel computing]]