View source for MOSFET

{{Short description|Type of field-effect transistor}}
{{pp-sock|small=yes}}
[[file:D2PAK.JPG|thumb|upright=1.3|Two [[power transistor|power MOSFETs]] in [[D2PAK]] [[surface-mount package]]s. Operating as switches, each of these components can sustain a blocking voltage of 120{{nbsp}}[[volts|V]] in the ''off'' state, and can conduct a con&shy;ti&shy;nuous current of 30&nbsp;[[amperes|A]] in the ''on'' state, dissipating up to about 100&nbsp;[[watt|W]] and controlling a load of over 2000&nbsp;W. A [[matchstick]] is pictured for scale.]]

In [[electronics]], the '''metal–oxide–semiconductor field-effect transistor''' ('''MOSFET''', '''MOS-FET''', '''MOS FET''', or '''MOS transistor''') is a type of [[field-effect transistor]] (FET), most commonly fabricated by the [[thermal oxidation|controlled oxidation]] of [[silicon]]. It has an insulated gate, the [[voltage]] of which determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic [[signal]]s. The term ''metal–insulator–semiconductor field-effect transistor'' (''MISFET'') is almost synonymous with ''MOSFET''. Another near-synonym is ''insulated-gate field-effect transistor'' (''IGFET'').

The main advantage of a MOSFET is that it requires almost no input current to control the load current under steady-state or low-frequency conditions, especially compared to [[bipolar junction transistor]]s (BJTs). However, at high frequencies or when switching rapidly, a MOSFET may require significant current to charge and discharge its gate capacitance. In an ''enhancement mode'' MOSFET, voltage applied to the gate terminal increases the conductivity of the device. In ''depletion mode'' transistors, voltage applied at the gate reduces the conductivity.<ref name="depletion">{{cite web |title=D-MOSFET OPERATION AND BIASING |url=https://massless.info/images/CLASS%2025.pdf |archive-url=https://web.archive.org/web/20221022122055/https://massless.info/images/CLASS%2025.pdf |archive-date=2022-10-22 |url-status=live}}</ref>

The "metal" in the name MOSFET is sometimes a [[misnomer]], because the gate material can be a layer of [[polysilicon]] (polycrystalline silicon). Similarly, "oxide" in the name can also be a misnomer, as different dielectric materials are used with the aim of obtaining strong channels with smaller applied voltages.

The MOSFET is by far the most common transistor in [[digital circuit|digital]] circuits, as billions may be included in a [[memory chip]] or [[microprocessor]]. As MOSFETs can be made with either a p-type or n-type channel, complementary pairs of MOS transistors can be used to make switching circuits with very low power consumption, in the form of [[CMOS logic]].

[[file:MOSFET functioning body.svg|thumb|upright=1.3|A cross-section through an nMOSFET when the gate voltage ''V''<sub>GS</sub> is below the threshold for making a conductive channel; there is little or no conduction between the terminals drain and source; the switch is off. When the gate is more positive, it attracts electrons, inducing an ''n''-type conductive channel in the substrate below the oxide (yellow), which allows electrons to flow between the ''n''-doped terminals; the switch is on.]]

== History ==
The basic principle of the [[field-effect transistor]] was first filed as a patent by [[Julius Edgar Lilienfeld]] as a Canadian patent in 1925 and later as a U.S. patent in 1926.<ref>{{Cite patent|number=CA272437A|title=Electric current control mechanism|gdate=1927-07-19|invent1=Julius|inventor1-first=Edgar Lilienfeld|url=https://patents.google.com/patent/CA272437A/en}}</ref><ref name="p12">Lilienfeld, Julius Edgar (1926-10-08) "Method and apparatus for controlling electric currents" {{US Patent|1745175A}}</ref> In 1934, inventor [[Oskar Heil]] independently patented a similar device in Europe.<ref>[http://v3.espacenet.com/publicationDetails/biblio?CC=GB&NR=439457&KC=&FT=E Heil, Oskar, "Improvements in or relating to electrical amplifiers and other control arrangements and devices"], Patent No. GB439457, European Patent Office, filed in Great Britain 1934-03-02, published December 6, 1935 (originally filed in Germany March 2, 1934).</ref>

In the 1940s, [[Bell Labs]] scientists [[William Shockley]], [[John Bardeen]] and [[Walter Houser Brattain]] attempted to build a field-effect device which led to their discovery of the [[transistor]] effect. However, their structure failed to show the anticipated effects due to the problem of [[surface states]]: traps on the semiconductor surface that hold electrons immobile. With no [[surface passivation]] they were only able to build the [[Bipolar junction transistor|BJT]] and [[thyristor]] transistors.

In 1955, [[Carl Frosch]] and Lincoln Derick accidentally grew a layer of silicon dioxide over the silicon wafer, for which they observed surface passivation effects.<ref name=":02">{{Cite journal |last1=Huff |first1=Howard |last2=Riordan |first2=Michael |date=2007-09-01 |title=Frosch and Derick: Fifty Years Later (Foreword) |url=https://iopscience.iop.org/article/10.1149/2.F02073IF |journal=The Electrochemical Society Interface |volume=16 |issue=3 |pages=29 |doi=10.1149/2.F02073IF |issn=1064-8208}}</ref><ref>{{Cite patent|number=US2802760A|title=Oxidation of semiconductive surfaces for controlled diffusion|gdate=1957-08-13|invent1=Lincoln|invent2=Frosch|inventor1-first=Derick|inventor2-first=Carl J.|url=https://patents.google.com/patent/US2802760A}}</ref> By 1957 Frosch and Derick, using masking and predeposition, were able to manufacture silicon dioxide field effect transistors; the first planar transistors, in which drain and source were adjacent at the same surface.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> They showed that silicon dioxide insulated, protected silicon wafers and prevented dopants from diffusing into the wafer.<ref name=":02" /><ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> At Bell Labs, the importance of Frosch and Derick technique and transistors was immediately realized. Results of their work circulated around Bell Labs in the form of BTL memos before being published in 1957. At [[Shockley Semiconductor Laboratory|Shockley Semiconductor]], Shockley had circulated the preprint of their article in December 1956 to all his senior staff, including [[Jean Hoerni]],<ref name="Moskowitz2">{{cite book |last1=Moskowitz |first1=Sanford L. |url=https://books.google.com/books?id=2STRDAAAQBAJ&pg=PA168 |title=Advanced Materials Innovation: Managing Global Technology in the 21st century |date=2016 |publisher=[[John Wiley & Sons]] |isbn=978-0-470-50892-3 |page=168}}</ref><ref>{{cite book |author1=Christophe Lécuyer |url=https://books.google.com/books?id=LaZpUpkG70QC&pg=PA62 |title=Makers of the Microchip: A Documentary History of Fairchild Semiconductor |author2=David C. Brook |author3=Jay Last |date=2010 |publisher=MIT Press |isbn=978-0-262-01424-3 |pages=62–63}}</ref><ref>{{cite book |last1=Claeys |first1=Cor L. |url=https://books.google.com/books?id=bu22JNYbE5MC&pg=PA27 |title=ULSI Process Integration III: Proceedings of the International Symposium |date=2003 |publisher=[[The Electrochemical Society]] |isbn=978-1-56677-376-8 |pages=27–30}}</ref><ref name="Lojek1202">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |page=120}}</ref> who would later invent the [[planar process]] in 1959 while at [[Fairchild Semiconductor]].<ref>{{patent|US|3025589|Hoerni, J. A.: "Method of Manufacturing Semiconductor Devices" filed May 1, 1959}}</ref><ref>{{patent|US|3064167|Hoerni, J. A.: "Semiconductor device" filed May 15, 1960}}</ref>
[[File:1957(Figure_9)-Gate_oxide_transistor_by_Frosch_and_Derrick.png|thumb|310x310px|1957, Diagram of one of the SiO2 transistor devices made by Frosch and Derick<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref>]]
After this, J.R. Ligenza and W.G. Spitzer studied the mechanism of thermally grown oxides, fabricated a high quality Si/[[Silicon dioxide|SiO<sub>2</sub>]] stack and published their results in 1960.<ref>{{Cite journal |last1=Ligenza |first1=J. R. |last2=Spitzer |first2=W. G. |date=1960-07-01 |title=The mechanisms for silicon oxidation in steam and oxygen |url=https://linkinghub.elsevier.com/retrieve/pii/0022369760902195 |journal=Journal of Physics and Chemistry of Solids |volume=14 |pages=131–136 |doi=10.1016/0022-3697(60)90219-5 |bibcode=1960JPCS...14..131L |issn=0022-3697|url-access=subscription }}</ref><ref name="Deal2">{{cite book |last1=Deal |first1=Bruce E. |title=Silicon materials science and technology |date=1998 |publisher=[[The Electrochemical Society]] |isbn=978-1566771931 |page=183 |chapter=Highlights Of Silicon Thermal Oxidation Technology |chapter-url=https://books.google.com/books?id=cr8FPGkiRS0C&pg=PA183}}</ref><ref>{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer Science & Business Media |isbn=978-3540342588 |page=322}}</ref>Following this research, [[Mohamed Atalla]] and [[Dawon Kahng]] proposed a silicon MOS transistor in 1959<ref name="Bassett222">{{cite book |last1=Bassett |first1=Ross Knox |url=https://books.google.com/books?id=UUbB3d2UnaAC&pg=PA22 |title=To the Digital Age: Research Labs, Start-up Companies, and the Rise of MOS Technology |date=2007 |publisher=[[Johns Hopkins University Press]] |isbn=978-0-8018-8639-3 |pages=22–23}}</ref> and successfully demonstrated a working MOS device with their Bell Labs team in 1960.<ref>{{cite journal |last1=Atalla |first1=M. |author1-link=Mohamed Atalla |last2=Kahng |first2=D. |author2-link=Dawon Kahng |date=1960 |title=Silicon-silicon dioxide field induced surface devices |journal=IRE-AIEE Solid State Device Research Conference}}</ref><ref>{{cite journal |title=1960 – Metal Oxide Semiconductor (MOS) Transistor Demonstrated |url=https://www.computerhistory.org/siliconengine/metal-oxide-semiconductor-mos-transistor-demonstrated/ |journal=The Silicon Engine |publisher=[[Computer History Museum]] |access-date=2023-01-16}}</ref> Their team included E. E. LaBate and E. I. Povilonis who fabricated the device; M. O. Thurston, L. A. D'Asaro, and J. R. Ligenza who developed the diffusion processes, and H. K. Gummel and R. Lindner who characterized the device.<ref>{{Cite journal |last=KAHNG |first=D. |date=1961 |title=Silicon-Silicon Dioxide Surface Device |url=https://doi.org/10.1142/9789814503464_0076 |journal=Technical Memorandum of Bell Laboratories |pages=583–596 |doi=10.1142/9789814503464_0076 |isbn=978-981-02-0209-5|url-access=subscription }}</ref><ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> This was a culmination of decades of field-effect research that began with Lilienfeld.
[[File:Threshold_formation_nowatermark.gif|thumb|Simulation of formation of inversion channel (electron density) and attainment of threshold voltage (IV) in a nanowire MOSFET. Note: [[Threshold voltage]] for this device lies around 0.45&nbsp;V.]]
The first MOS transistor at Bell Labs was about 100 times slower than contemporary [[bipolar transistors]] and was initially seen as inferior. Nevertheless, Kahng pointed out several advantages of the device, notably ease of fabrication and its application in [[Integrated circuit|integrated circuits]].

== Composition ==
[[file:MOSFETs.jpg|thumb|upright=1.2|Photomicrograph of two metal-gate MOSFETs in a test pattern. Probe pads for two gates and three source/drain nodes are labeled.]]

Silicon remains the primary [[semiconductor]] in [[CMOS]] devices, but to enhance carrier mobility, manufacturers—most notably [[IBM]] and [[Intel]]—induce [[Strained silicon|strain in the silicon channel]] by incorporating [[Silicon–germanium|silicon-germanium]] (SiGe) in nearby regions or applying stress engineering techniques, thereby improving transistor performance without using SiGe alloys as the channel material itself.{{Citation needed|date=July 2023}} 

Many semiconductors with better electrical properties than silicon, such as [[gallium arsenide]], do not form good semiconductor-to-insulator interfaces, and thus are not suitable for MOSFETs. Research continues on creating insulators with acceptable electrical characteristics on other semiconductor materials.{{Citation needed|date=August 2025}}

To overcome the increase in power consumption due to gate current leakage, a [[high-κ dielectric]] is used instead of silicon dioxide for the gate insulator, while polysilicon is replaced by metal gates (e.g. [[Intel]], 2009).<ref>{{cite web|url=http://www.intel.com/technology/architecture-silicon/45nm-core2/index.htm |archive-url=https://web.archive.org/web/20070705085953/http://www.intel.com/technology/architecture-silicon/45nm-core2/index.htm |url-status=dead |archive-date=July 5, 2007 |title=Intel 45nm Hi-k Silicon Technology |publisher=Intel}}</ref>

The gate is separated from the channel by a thin insulating layer, traditionally of silicon dioxide and later of [[silicon oxynitride]]. Some companies use a high-κ dielectric and metal gate combination in the [[45 nanometer]] node.

When a voltage is applied between the gate and the source, the electric field generated penetrates through the oxide and creates an ''inversion layer'' or ''channel'' at the semiconductor-insulator interface. The inversion layer provides a channel through which current can pass between source and drain terminals. Varying the voltage between the gate and body modulates the [[electrical conductivity|conductivity]] of this layer and thereby controls the current flow between drain and source. This is known as enhancement mode.

== Operation ==
[[file:MOS Capacitor.svg|thumb|upright=1.2|Metal–oxide–semiconductor structure on p-type silicon]]

=== Metal–oxide–semiconductor structure ===
The traditional metal–oxide–semiconductor (MOS) structure is obtained by growing a layer of [[silicon dioxide]] ({{chem|Si|O|2}}) on top of a silicon substrate, commonly by [[thermal oxidation]] and depositing a layer of metal or [[polycrystalline silicon]] (the latter is commonly used). As silicon dioxide is a [[dielectric]] material, its structure is equivalent to a planar [[capacitor]], with one of the electrodes replaced by a semiconductor.

When a voltage is applied across a MOS structure, it modifies the distribution of charges in the semiconductor. If we consider a p-type semiconductor (with ''N''<sub>A</sub> the density of [[acceptor (semiconductors)|acceptors]], ''p'' the density of holes; ''p = N''<sub>A</sub> in neutral bulk), a positive voltage, ''V''<sub>G</sub>, from gate to body (see figure) creates a [[depletion layer]] by forcing the positively charged holes away from the gate-insulator/semiconductor interface, leaving exposed a carrier-free region of immobile, negatively charged acceptor ions (see [[doping (semiconductor)|doping]]). If ''V''<sub>G</sub> is high enough, a high concentration of negative charge carriers forms in an ''inversion layer'' located in a thin layer next to the interface between the semiconductor and the insulator.

Conventionally, the gate voltage at which the volume density of electrons in the inversion layer is the same as the volume density of holes in the body is called the [[threshold voltage]]. When the voltage between transistor gate and source (''V''<sub>G</sub>) exceeds the threshold voltage (''V''<sub>th</sub>), the difference is known as [[overdrive voltage]].

This structure with p-type body is the basis of the n-type MOSFET, which requires the addition of n-type source and drain regions.

=== MOS capacitors and band diagrams ===
{{Unreferenced section|date=January 2019}}
The MOS capacitor structure is the heart of the MOSFET. Consider a MOS capacitor where the silicon base is of p-type. If a positive voltage is applied at the gate, holes which are at the surface of the p-type substrate will be repelled by the electric field generated by the voltage applied. At first, the holes will simply be repelled and what will remain on the surface will be immobile (negative) atoms of the acceptor type, which creates a depletion region on the surface. A hole is created by an acceptor atom, e.g., boron, which has one less electron than a silicon atom. Holes are not actually repelled, being non-entities; electrons are attracted by the positive field, and fill these holes. This creates a depletion region where no charge carriers exist because the electron is now fixed onto the atom and immobile.

As the voltage at the gate increases, there will be a point at which the surface above the depletion region will be converted from p-type into n-type, as electrons from the bulk area will start to get attracted by the larger electric field. This is known as ''inversion''. The threshold voltage at which this conversion happens is one of the most important parameters in a MOSFET.

In the case of a p-type MOSFET, bulk inversion happens when the intrinsic energy level at the surface becomes smaller than the [[Fermi level]] at the surface. This can be seen on a band diagram. The Fermi level defines the type of semiconductor in discussion. If the Fermi level is equal to the Intrinsic level, the semiconductor is of intrinsic, or pure type. If the Fermi level lies closer to the conduction band (valence band) then the semiconductor type will be of n-type (p-type).

When the gate voltage is increased in a positive sense {{Clarify span |text=(for the given example),|reason=Unclear which example this is referring to since both types of MOSFET are simultaneously described|date=February 2024}}  this will shift the intrinsic energy level band so that it will curve downwards towards the valence band. If the Fermi level lies closer to the valence band (for p-type), there will be a point when the Intrinsic level will start to cross the Fermi level and when the voltage reaches the threshold voltage, the intrinsic level does cross the Fermi level, and that is what is known as inversion. At that point, the surface of the semiconductor is inverted from p-type into n-type.

If the Fermi level lies above the intrinsic level, the semiconductor is of n-type, therefore at inversion, when the intrinsic level reaches and crosses the Fermi level (which lies closer to the valence band), the semiconductor type changes at the surface as dictated by the relative positions of the Fermi and Intrinsic energy levels.

=== Structure and channel formation ===
{{See also|Field effect (semiconductor)}}
[[file:Semiconductor band-bending-en.svg|thumb|upright=1.5|''Channel formation in nMOS MOSFET shown as [[band diagram]]'': Top panels: An applied gate voltage bends bands, depleting holes from surface (left). The charge inducing the bending is balanced by a layer of negative acceptor-ion charge (right). Bottom panel: A larger applied voltage further depletes holes but conduction band lowers enough in energy to populate a conducting channel.]]
[[file:Illustration of C-V measurement.gif|thumb|upright=1.5|C–V profile for a bulk MOSFET with different oxide thickness. The leftmost part of the curve corresponds to accumulation. The valley in the middle corresponds to depletion. The curve on the right corresponds to inversion.]]

A MOSFET is based on the modulation of charge concentration by a MOS capacitance between a ''body'' electrode and a ''gate'' electrode located above the body and insulated from all other device regions by a gate dielectric layer. If dielectrics other than an oxide are employed, the device may be referred to as a metal-insulator-semiconductor FET (MISFET). Compared to the MOS capacitor, the MOSFET includes two additional terminals (''source'' and ''drain''), each connected to individual highly doped regions that are separated by the body region. These regions can be either p or n type, but they must both be of the same type, and of opposite type to the body region. The source and drain (unlike the body) are highly doped as signified by a "+" sign after the type of doping.

If the MOSFET is an n-channel or nMOS FET, then the source and drain are ''n+'' regions and the body is a ''p'' region. If the MOSFET is a p-channel or pMOS FET, then the source and drain are ''p+'' regions and the body is a ''n'' region. The source is so named because it is the source of the charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.

The occupancy of the energy bands in a semiconductor is set by the position of the [[Fermi level]] relative to the semiconductor energy-band edges.

{{See also|Depletion region}}
With sufficient gate voltage, the valence band edge is driven far from the Fermi level, and holes from the body are driven away from the gate.

At larger gate bias still, near the semiconductor surface the conduction band edge is brought close to the Fermi level, populating the surface with electrons in an ''inversion layer'' or ''n-channel'' at the interface between the p region and the oxide. This conducting channel extends between the source and the drain, and current is conducted through it when a voltage is applied between the two electrodes. Increasing the voltage on the gate leads to a higher electron density in the inversion layer and therefore increases the current flow between the source and drain. For gate voltages below the threshold value, the channel is lightly populated, and only a very small [[subthreshold leakage]] current can flow between the source and the drain.

When a negative gate-source voltage (positive source-gate) is applied, it creates a ''p-channel'' at the surface of the n region, analogous to the n-channel case, but with opposite polarities of charges and voltages. When a voltage less negative than the threshold value (a negative voltage for the p-channel) is applied between gate and source, the channel disappears and only a very small subthreshold current can flow between the source and the drain. The device may comprise a [[silicon on insulator]] device in which a buried oxide is formed below a thin semiconductor layer. If the channel region between the gate dielectric and the buried oxide region is very thin, the channel is referred to as an ultrathin channel region with the source and drain regions formed on either side in or above the thin semiconductor layer. Other semiconductor materials may be employed. When the source and drain regions are formed above the channel in whole or in part, they are referred to as raised source/drain regions.

{| class="wikitable"
|+ Comparison of n- and p-type MOSFETs<ref name=memory>{{cite web|title=memory components data book|url=http://bitsavers.trailing-edge.com/pdf/intel/_dataBooks/1984_Intel_Memory_Components_Handbook.pdf|archive-url=https://web.archive.org/web/20160304090142/http://bitsavers.trailing-edge.com/pdf/intel/_dataBooks/1984_Intel_Memory_Components_Handbook.pdf|url-status=dead|archive-date=4 March 2016|website=memory components data book|publisher=Intel|accessdate=30 August 2015|pages=2–1}}</ref>
|-
! colspan=2 | Parameter
! nMOS FET
! pMOS FET
|-
! colspan=2 | Source/drain type
| n-type
| p-type
|-
! colspan=2 | {{ubl|Channel type|(MOS capacitor)}}
| n-type
| p-type
|-
! rowspan=2 | {{ubl|Gate|type}}
! Polysilicon
| n+
| p+
|-
! Metal
| {{abbr|φ<sub>m</sub>|Metal's workfunction}} ~ Si conduction band
| φ<sub>m</sub> ~ Si valence band
|-
! colspan=2 | Well type
| p-type
| n-type
|-
! colspan=2 | Threshold voltage, ''V''{{sub|th}}
| {{ubl
 | Positive (enhancement)
 | Negative (depletion)
 }}
| {{ubl
 | Negative (enhancement)
 | Positive (depletion)
 }}
|-
! colspan=2 | Band-bending
| Downwards
| Upwards
|-
! colspan=2 | Inversion layer carriers
| Electrons
| Holes
|-
! colspan=2 | Substrate type
| p-type
| n-type
|}

=== Modes of operation ===
[[file:MOSFET functioning.svg|thumb|upright=2|Source tied to the body to ensure no body bias:{{avoid wrap|top left: Subthreshold, top right: Ohmic mode,}} bottom left: Active mode at onset of pinch-off, bottom right: Active mode well into pinch-off&nbsp;– channel length modulation evident]]
[[file:mosfet n-ch circuit.svg|right|thumb|upright=1.2|When the switched is closed, the n-channel MOSFET's gate raises above its threshold voltage, so the MOSFET then will conduct current to light the LED.<ref name="brunningsoftware_co_uk-FET">{{cite web|title=Using a MOSFET as a Switch|url=http://brunningsoftware.co.uk/FET.htm|archive-url=https://web.archive.org/web/20180411173010/http://brunningsoftware.co.uk/FET.htm |archive-date=2018-04-11 }} 090507 brunningsoftware.co.uk</ref>]]

The operation of a MOSFET can be separated into three different modes, depending on the device's [[threshold voltage]] (<math>V_\text{th}</math>), gate-to-source voltage (<math>V_\text{GS}</math>), and drain-to-source voltage (<math>V_\text{DS}</math>). In the following discussion, a simplified algebraic model is used.<ref name=Hodges>{{cite journal|first1=H.|last1=Shichman |first2=D. A.|last2=Hodges |name-list-style=amp |title=Modeling and simulation of insulated-gate field-effect transistor switching circuits |journal=IEEE Journal of Solid-State Circuits |volume=SC-3 |issue=3 |pages=285–289 |year=1968 |doi=10.1109/JSSC.1968.1049902 |bibcode=1968IJSSC...3..285S }}</ref> Modern MOSFET characteristics are more complex than the algebraic model presented here.<ref name=Hu>For example, see {{cite book
 |title=MOSFET modeling & BSIM3 user's guide
 |url=https://books.google.com/books?id=R5DP56qUql4C
 |isbn=978-0-7923-8575-2 |year=1999 |publisher=Springer
 |first1=Yuhua|last1=Cheng
 |first2=Chenming|last2=Hu
}} The most recent version of the [[BSIM]] model is described in {{cite web
 |title=BSIM-CMG 106.1.0beta Multi-Gate MOSFET Compact Model
 |first1=Sriramkumar|last1=V.
 |first2=Navid|last2=Paydavosi
 |first3=Darsen|last3=Lu
 |first4=Chung-Hsun|last4=Lin
 |first5=Mohan|last5=Dunga
 |first6=Shijing|last6=Yao
 |first7=Tanvir|last7=Morshed
 |first8=Ali|last8=Niknejad
 |first9=Chenming|last9=Hu
 |name-list-style=amp
 |url=http://www-device.eecs.berkeley.edu/bsim/Files/BSIMCMG/BSIMCMG106.0.0/BSIMCMG106.0.0_TechnicalManual_20120313.pdf
 |year=2012
 |publisher=Department of Electronic Engineering and Computer Science, University of California Berkeley
 |access-date=2012-04-01
 |url-status=dead
 |archive-url=https://web.archive.org/web/20140727084407/http://www-device.eecs.berkeley.edu/bsim/Files/BSIMCMG/BSIMCMG106.0.0/BSIMCMG106.0.0_TechnicalManual_20120313.pdf
 |archive-date=2014-07-27
 }}</ref>

For an ''enhancement-mode, n-channel MOSFET'', the three operational modes are:

==== Cutoff, subthreshold, and weak-inversion mode====

Criterion: <math>V_\text{GS} < V_\text{th} .</math>

According to the basic threshold model, the transistor is turned off, and there is no conduction between drain and source. A more accurate model considers the effect of thermal energy on the [[Fermi–Dirac distribution]] of electron energies which allow some of the more energetic electrons at the source to enter the channel and flow to the drain. This results in a subthreshold current that is an exponential function of gate-source voltage. While the current between drain and source should ideally be zero when the transistor is being used as a turned-off switch, there is a weak-inversion current, sometimes called subthreshold leakage.

In weak inversion where the source is tied to bulk, the current varies exponentially with <math>V_\text{GS}</math> as given approximately by:<ref name=Gray-Meyer>
{{ cite book
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 | year = 2004
 | page=78
 | publisher=Springer
 | location=Dordrecht
 | isbn = 978-1-4020-2848-9
 | url=https://books.google.com/books?id=nyken8ivkb8C&pg=PA78 
}}</ref>

<math display="block">I_\text{D} \approx I_\text{D0} e^\frac{V_\text{GS} - V_\text{th}}{nV_\text{T}}, </math>

where:

* <math>I_\text{D0}</math> is the current when <math>V_\text{GS} {=} V_\text{th}</math>,
* <math>V_\text{T} {=} kT/q</math> is the thermal voltage, and
* <math>n</math> is the slope factor given by:

<math display="block">n = 1 + \frac{C_\text{dep}}{C_\text{ox}},</math>

where <math>C_\text{dep}</math> is the capacitance of the depletion layer and <math>C_\text{ox}</math> is the capacitance of the oxide layer. This equation is generally used, but is only an adequate approximation for the source tied to the bulk. For the source not tied to the bulk, the subthreshold equation for drain current in saturation is<ref>{{cite web|last=Degnan|first=Brian|title=Wikipedia fails subvt|url=https://sites.google.com/site/degnan68k/semiconductors/wikipedia-fails-subvt}}</ref><ref>{{cite book|last=Mead|first=Carver|title=Analog VLSI and Neural Systems|year=1989|publisher=Addison-Wesley|location=Reading, Massachusetts|isbn=9780201059922|page=370}}</ref>

<math display="block">I_\text{D} \approx I_\text{D0} e^\frac{V_\text{G} - V_\text{th}}{nV_\text{T}} e^{-\frac{  V_\text{S}}{V_\text{T}}}. </math>

In a long-channel device, there is no drain voltage dependence of the current once <math>V_\text{DS} \gg V_\text{T}</math>, but as channel length is reduced [[drain-induced barrier lowering]] introduces drain voltage dependence that depends in a complex way upon the device geometry (for example, the channel doping, the junction doping and so on). Frequently, threshold voltage ''V''<sub>th</sub> for this mode is defined as the gate voltage at which a selected value of current ''I''<sub>D0</sub> occurs, for example, ''I''<sub>D0</sub> = 1{{nbsp}}μA, which may not be the same ''V''<sub>th</sub>-value used in the equations for the following modes.

Some micropower analog circuits are designed to take advantage of subthreshold conduction.<ref name="Smith-Hamilton">{{cite book |first1=Leslie S.|last1=Smith |first2=Alister|last2=Hamilton |title=Neuromorphic Systems: Engineering Silicon from Neurobiology |date=1998 |pages=52–56 |publisher=World Scientific |isbn=978-981-02-3377-8 | url=https://books.google.com/books?id=kWSXEHyQL9sC&pg=PA55 }}</ref><ref name="Kumar">{{cite book | first=Satish|last=Kumar | title=Neural Networks: A Classroom Approach |date=2004 |page=688 |publisher=Tata McGraw-Hill |isbn=978-0-07-048292-0 |url=https://books.google.com/books?id=GJQh-2p6TvgC&pg=PA688 }}</ref><ref name="Conference">{{cite book | first1 = Manfred|last1=Glesner |first2=Peter|last2=Zipf |first3=Michel|last3=Renovell |title=Field-programmable Logic and Applications: 12th International Conference |date=2002 |page=425 |location=Dordrecht |publisher=Springer |isbn=978-3-540-44108-3 | url = https://books.google.com/books?id=fneXs6IY2-oC&pg=PA425}}</ref> By working in the weak-inversion region, the MOSFETs in these circuits deliver the highest possible transconductance-to-current ratio, namely: <math>g_m/I_\text{D} = 1/\left(nV_\text{T}\right)</math>, almost that of a bipolar transistor.<ref>{{cite book |title=Circuits and systems tutorials |chapter=The Fundamentals of Analog Micropower Design |editor1-first=Chris |editor1-last=Toumazou |editor2-first=Nicholas C. |editor2-last=Battersby |editor3-first=Sonia |editor3-last=Porta |first=Eric A. |last=Vittoz | publisher = John Wiley and Sons |date=1996 |isbn=978-0-7803-1170-1 |pages=365–372 |chapter-url=https://books.google.com/books?id=WTInL9njOKAC&pg=PA367 }}</ref>

The subthreshold ''[[I–V curve]]'' depends exponentially upon threshold voltage, introducing a strong dependence on any manufacturing variation that affects threshold voltage; for example: variations in oxide thickness, junction depth, or body doping that change the degree of drain-induced barrier lowering. The resulting sensitivity to fabricational variations complicates optimization for leakage and performance.<ref name=Shukla>{{ cite book | first1 =Sandeep K.|last1=Shukla |first2=R. Iris|last2=Bahar |author2-link=R. Iris Bahar | title=Nano, Quantum and Molecular Computing | year = 2004 | at=p. 10 and Fig. 1.4, p. 11 | publisher = Springer | isbn=978-1-4020-8067-8 | url = https://books.google.com/books?id=lLvo1iMGhJgC&pg=PA10}}</ref><ref name=Srivasta>{{ cite book | first1 =Ashish|last1=Srivastava |first2=Dennis|last2=Sylvester |first3=David|last3=Blaauw | title=Statistical Analysis and Optimization For VLSI: Timing and Power | year = 2005 | page=135 | publisher=Springer | isbn = 978-0-387-25738-9 | url = https://books.google.com/books?id=WqsQTyOu5jwC&pg=PA9 }}</ref>

[[file:IvsV mosfet.svg|thumb|upright=1.2|MOSFET drain current vs. drain-to-source voltage for several values of <math>V_\text{GS} - V_\text{th}</math>; the boundary between ''linear'' (''Ohmic'') and ''saturation'' (''active'') modes is indicated by the upward curving parabola.]]
[[file:Mosfet linear.svg|thumb|upright=1.2|Cross section of a MOSFET operating in the linear (Ohmic) region; strong inversion region present even near drain.]]
[[file:Mosfet saturation.svg|thumb|upright=1.2|Cross section of a MOSFET operating in the saturation (active) region; channel exhibits [[channel length modulation|channel pinching]] near drain.]]

====Triode mode or linear region (also known as the ohmic mode){{anchor|Linear mode}}====

Criteria: <math>V_\text{GS} > V_\text{th}</math> and <math>V_\text{DS} < (V_\text{GS} - V_\text{th}) .</math>

The transistor is turned on, and a channel has been created which allows current between the drain and the source. The MOSFET operates like a resistor, controlled by the gate voltage relative to both the source and drain voltages. The current from drain to source is modeled as:

<math display="block">I_\text{D} = \mu_n C_\text{ox}\frac{W}{L} \left( \left(V_\text{GS} - V_{\rm th}\right)V_\text{DS} - \frac{{V_\text{DS}}^2}{2} \right) ,</math>

where <math>\mu_n</math> is the charge-carrier effective mobility, <math>W</math> is the gate width, <math>L</math> is the gate length and <math>C_\text{ox}</math> is the gate oxide capacitance per unit area. The transition from the exponential subthreshold region to the triode region is not as sharp as the equations suggest.<ref name=Schneider>{{ cite book | first1 =C. |last1=Galup-Montoro |last2=Schneider|first2=M. C. |name-list-style=amp | title=MOSFET modeling for circuit analysis and design | year = 2007 | page=83 | publisher=World Scientific | location = London/Singapore | isbn=978-981-256-810-6 | url = http://worldcat.org/isbn/981-256-810-7}}</ref><ref name=Malik>{{ cite book | first = Norbert R.|last= Malik | title = Electronic circuits: analysis, simulation, and design | year = 1995 | pages=315–316 | publisher=Prentice Hall | location = Englewood Cliffs, New Jersey | isbn=978-0-02-374910-0 | url = http://worldcat.org/isbn/0-02-374910-5 }}</ref>{{verify source|reason=Citations were unhelpfully attached to the heading. Please move to indicate which claims they support, or leave here if the whole section|date=January 2023}}

====Saturation or active mode====

Critera: <math>V_\text{GS} > V_\text{th}</math> and <math>V_\text{DS} \geq (V_\text{GS} - V_\text{th}) .</math>

The switch is turned on, and a channel has been created, which allows current between the drain and source. Since the drain voltage is higher than the source voltage, the electrons spread out, and conduction is not through a narrow channel but through a broader, two- or three-dimensional current distribution extending away from the interface and deeper in the substrate. The onset of this region is also known as [[channel length modulation|pinch-off]] to indicate the lack of channel region near the drain. Although the channel does not extend the full length of the device, the electric field between the drain and the channel is very high, and conduction continues. The drain current is now weakly dependent upon drain voltage and controlled primarily by the gate-source voltage, and modeled approximately as:

<math display="block">I_\text{D} = \frac{\mu_n C_\text{ox}}{2}\frac{W}{L}\left[V_\text{GS} - V_\text{th}\right]^2 \left[1 + \lambda V_\text{DS}\right].</math>

The additional factor involving λ, the channel-length modulation parameter, models current dependence on drain voltage due to the [[Early effect]], or [[channel length modulation]]. According to this equation, a key design parameter, the MOSFET transconductance is:

<math display="block">g_m = \frac{\partial I_D}{\partial V_\text{GS}} = \frac{2I_\text{D}}{V_\text{GS} - V_\text{th}} = \frac{2I_\text{D}}{V_\text{ov}} , </math>

where the combination ''V''<sub>ov</sub> = ''V''<sub>GS</sub>&nbsp;− ''V''<sub>th</sub> is called the [[overdrive voltage]],<ref name=Sedra2>{{cite book | first1 =A. S.|last1=Sedra |first2=K. C.|last2=Smith |name-list-style=amp |title=Microelectronic Circuits |edition=5th |at=p. 250, Eq. 4.14 |isbn = 978-0-19-514251-8 |url=http://worldcat.org/isbn/0-19-514251-9|year=2004|publisher=Oxford University Press }}</ref> and where ''V''<sub>DSsat</sub> = ''V''<sub>GS</sub>&nbsp;− ''V''<sub>th</sub> accounts for a small discontinuity in <math>I_\text{D}</math> which would otherwise appear at the transition between the triode and saturation regions.

Another key design parameter is the MOSFET output resistance ''r<sub>out</sub>'' given by:

<math display="block">r_\text{out} = \frac{1}{\lambda I_\text{D}} \, .</math>

Note: ''r''<sub>out</sub> is the inverse of ''g''<sub>DS</sub>, where <math>g_\text{DS} = \frac{\partial I_\text{DS}}{\partial V_\text{DS}}</math>. ''I''<sub>D</sub> is the expression in the saturation region.

If λ is taken as zero, an infinite output resistance of the device results that leads to unrealistic circuit predictions, particularly in analog circuits.

As the channel length becomes very short, these equations become quite inaccurate. New physical effects arise. For example, carrier transport in the active mode may become limited by [[velocity saturation]]. When velocity saturation dominates, the saturation drain current is more nearly linear than quadratic in ''V''<sub>GS</sub>. At even shorter lengths, carriers transport with near zero scattering, known as quasi-[[ballistic transport]]. In the ballistic regime, the carriers travel at an injection velocity that may exceed the saturation velocity and approaches the [[Fermi velocity]] at high inversion charge density. In addition, drain-induced barrier lowering increases off-state (cutoff) current and requires an increase in threshold voltage to compensate, which in turn reduces the saturation current.<ref name=Gray-Meyer2>{{cite book |first1=P. R.|last1=Gray |first2=P. J.|last2= Hurst |first3=S. H.|last3= Lewis |first4=R. G.|last4= Meyer | title=Analysis and design of analog integrated circuits |edition=4th |at = §1.5.2 p. 45 |location=New York |publisher=Wiley |isbn=978-0-471-32168-2 | url = http://worldcat.org/isbn/0-471-32168-0|year=2001 }}</ref><!--Credit only supported in linked web page for the first author (Gray), but cover image gives the other three surnames--><ref name=Sedra>{{cite book |first1=A. S.|last1=Sedra |first2=K. C.|last2=Smith |name-list-style=amp |title=Microelectronic circuits |date=2004 |edition=5th |page=552 |publisher=Oxford University Press |location=New York |isbn=978-0-19-514251-8 |url=http://worldcat.org/isbn/0-19-514251-9 }}</ref>{{verify source|reason=Citations were unhelpfully attached to the heading. Please move to indicate which claims they support, or leave here if the whole section|date=January 2023}}

=== Body effect ===
[[file:Inversion with source-body bias.png|thumb|upright=1.2|[[Band diagram]] showing body effect. ''V''<sub>SB</sub> splits Fermi levels F<sub>n</sub> for electrons and F<sub>p</sub> for holes, requiring larger ''V''<sub>GB</sub> to populate the conduction band in an nMOS MOSFET.]]

The occupancy of the energy bands in a semiconductor is set by the position of the [[Fermi level#"Fermi level" in semiconductor physics|Fermi level]] relative to the semiconductor energy-band edges. Application of a source-to-substrate reverse bias of the source-body pn-junction introduces a split between the Fermi levels for electrons and holes, moving the Fermi level for the channel further from the band edge, lowering the occupancy of the channel. The effect is to increase the gate voltage necessary to establish the channel, as seen in the figure. This change in channel strength by application of reverse bias is called the "body effect".

Using an nMOS example, the gate-to-body bias ''V''<sub>GB</sub> positions the conduction-band energy levels, while the source-to-body bias V<sub>SB</sub> positions the electron Fermi level near the interface, deciding occupancy of these levels near the interface, and hence the strength of the inversion layer or channel.

The body effect upon the channel can be described using a modification of the threshold voltage, approximated by the following equation:

: <math>V_\text{TB} = V_{T0} + \gamma \left( \sqrt{V_\text{SB} + 2\varphi_B} - \sqrt{2\varphi_B} \right),</math>

where ''V''<sub>TB</sub> is the threshold voltage with substrate bias present, and ''V''<sub>T0</sub> is the zero-''V''<sub>SB</sub> value of threshold voltage, <math>\gamma</math> is the body effect parameter, and 2''φ''<sub>B</sub> is the approximate potential drop between surface and bulk across the depletion layer when {{nowrap|''V''<sub>SB</sub> {{=}} 0}} and gate bias is sufficient to ensure that a channel is present.<ref name=inversion>

For a uniformly doped p-type substrate with bulk acceptor doping of ''N<sub>A</sub>'' per unit volume,
: <math>\varphi_B = \frac{k_B T}{q} \ln \left(\frac{N_A}{n_i}\right) \ , </math>

with ''n<sub>i</sub>'' the intrinsic mobile carrier density per unit volume in the bulk. See, for example, {{cite book |title=Mosfet modeling for VLSI simulation: theory and practice |first=Narain|last=Arora |chapter=Equation 5.12 |chapter-url=https://books.google.com/books?id=SkT2xOuvpuYC&pg=PA173 |page=173 |isbn= 9789812707581|year=2007 |publisher=World Scientific}}</ref> As this equation shows, a reverse bias {{nowrap|''V''<sub>SB</sub> > 0}} causes an increase in threshold voltage ''V''<sub>TB</sub> and therefore demands a larger gate voltage before the channel populates.

The body can be operated as a second gate, and is sometimes referred to as the "back gate"; the body effect is sometimes called the "back-gate effect".<ref>{{cite web |url=http://equars.com/~marco/poli/phd/node20.html |title=Body effect |publisher=Equars.com |accessdate=2012-06-02 |url-status=dead |archiveurl=https://web.archive.org/web/20141110225738/http://equars.com/~marco/poli/phd/node20.html |archivedate=2014-11-10 }}</ref>

== Circuit symbols ==
A variety of symbols are used for the MOSFET. The basic design is generally a line for the channel with the source and drain leaving it at right angles and then bending back at right angles into the same direction as the channel. Sometimes three line segments are used for [[Channel (transistor)|enhancement mode]] and a solid line for depletion mode (see [[depletion and enhancement modes]]). Another line is drawn parallel to the channel for the gate.
[[File:Four terminal mosfet with body doides.svg|thumb|A 4-terminal nMOS has two ''intrinsic body diodes'' due to the body-to-drain and body-to-source [[P–n junction|p–n junctions]]. In pMOS, these diodes are reversed. The body-to-source diode is made irrelevant by shorting the body to the source in 3-terminal devices. The remaining [[Power MOSFET#Body diode|body-to-drain diode]] prevents the nMOS from blocking source-to-drain current and is used in some [[DC-to-DC converter|DC-to-DC converters]].<ref>{{Cite web |last=DigiKey |date=2016-09-22 |title=The Significance of the Intrinsic Body Diodes Inside MOSFETs |url=https://www.digikey.com/en/articles/the-significance-of-the-intrinsic-body-diodes-inside-mosfets |url-status=live |archive-url=https://web.archive.org/web/20240724010046/https://www.digikey.com/en/articles/the-significance-of-the-intrinsic-body-diodes-inside-mosfets |archive-date=2024-07-24 |access-date=2025-06-26 |website=[[DigiKey]]}}</ref>]]
The ''bulk'' or ''body'' connection, if shown, is shown connected to the back of the channel with an arrow indicating pMOS or nMOS. This arrow always points from P to N, so an nMOS (N-channel in P-well or P-substrate) has the arrow pointing from the bulk to the channel. Typically the bulk is internally connected to the source (as is generally the case with discrete devices), in which case the bulk end of the arrow will have a line drawn between it and the source to explicitly show this connection. Some symbols will also explicitly show the MOSFET's ''intrinsic body diode'' along an outer (and sometimes dotted, as may be done for [[Parasitic structure|parasitic elements]]) path between drain and source. Note that tying the bulk to the source is by no means the only important configuration. In general, the MOSFET is a four-terminal device. In integrated circuits, many of the MOSFETs share a body connection, not necessarily connected to the source terminals of all the transistors.

If the bulk is not shown (as is often the case in IC design as they are generally common bulk) an inversion symbol is sometimes used to indicate pMOS. Alternatively, as is done with bipolar transistors, an arrow on the MOSFET's source may indicate the direction of [[conventional current]]: pointing out for nMOS, in for pMOS.

In the following symbols for [[JFET|JFETs]], enhancement-mode MOSFETs, and depletion-mode MOSFETs, the orientation of the symbols (most significantly the position of source relative to drain) is such that more positive voltages appear higher on the page than less positive voltages, implying [[Electric current#Conventional current|conventional current]] flowing "down" the page:<ref>{{cite web|archive-url=https://web.archive.org/web/20141013185140/http://www.circuitstoday.com/electronic-circuit-symbols|archive-date=13 October 2014|url= http://www.circuitstoday.com/electronic-circuit-symbols|title=Electronic Circuit Symbols|website=circuitstoday.com|date=9 November 2011}}</ref><ref>{{citation|title=IEEE Std 315-1975&nbsp;— Graphic Symbols for Electrical and Electronics Diagrams (Including Reference Designation Letters)}}</ref><ref>{{cite book|url=http://highered.mcgraw-hill.com/sites/dl/free/0073191639/366537/Chapter_4.pdf#page=19 |archive-url=https://ghostarchive.org/archive/20221009/http://highered.mcgraw-hill.com/sites/dl/free/0073191639/366537/Chapter_4.pdf#page=19 |archive-date=2022-10-09 |url-status=live|title=Microelectronic Circuit Design|first1=Richard C.|last1=Jaeger|first2=Travis N.|last2=Blalock|chapter=Figure 4.15 IEEE Standard MOS transistor circuit symbols}}</ref>

{| class="wikitable" style="text-align:center;"
|-
! P-channel
| [[file:JFET P-Channel Labelled.svg|80px|class=skin-invert-image]]
| [[file:IGFET P-Ch Enh Labelled.svg|80px|class=skin-invert-image]] [[File:IGFET P-Ch Enh Diode Labelled.svg|80px|class=skin-invert-image]]
| [[File:IGFET P-Ch Enh Bulk Labelled.svg|80px|class=skin-invert-image]]
| [[file:IGFET P-Ch Enh Labelled simplified.svg|80px|class=skin-invert-image]]
| [[file:Mosfet P-Ch Sedra.svg|80px|class=skin-invert-image]]
| [[file:IGFET P-Ch Dep Labelled.svg|80px|class=skin-invert-image]]
|-
! N-channel
| [[file:JFET N-Channel Labelled.svg|80px|class=skin-invert-image]]
| [[file:IGFET N-Ch Enh Labelled.svg|80px|class=skin-invert-image]] [[File:IGFET N-Ch Enh Diode Labelled.svg|80px|class=skin-invert-image]]
| [[File:IGFET N-Ch Enh Bulk Labelled.svg|80px|class=skin-invert-image]]
| [[file:IGFET N-Ch Enh Labelled simplified.svg|80px|class=skin-invert-image]]
| [[file:Mosfet N-Ch Sedra.svg|80px|class=skin-invert-image]]
| [[file:IGFET N-Ch Dep Labelled.svg|80px|class=skin-invert-image]]
|-
! rowspan="2" |
! rowspan="2" | JFET
! Bulk explicitly tied to source
!Exposed bulk terminal
! colspan="2" | Bulk connection not shown{{NoteTag|Note: The other enhancement-mode diagrams use a dashed-line along the channel to distinguish it as an enhancement-mode device. However, this particular shorthand above uses a plain line for enhancement-mode and instead uses a thick line to indicate a depletion-mode device.}}
! Bulk explicitly tied to source
|-
! colspan="4" |Enhancement-mode MOSFET
!Depletion-mode MOSFET
|}

In schematics where G, S, D are not labeled, the detailed features of the symbol indicate which terminal is source and which is drain. For enhancement-mode and depletion-mode MOSFET symbols (in columns two and five), the source terminal is the one connected to the triangle. Additionally, in this diagram, the gate is shown as an "L" shape, whose input leg is closer to S than D, also indicating which is which. However, these symbols are often drawn with a T-shaped gate (as elsewhere on this page), so it is the triangle which must be relied upon to indicate the source terminal.


== Applications ==
Digital [[integrated circuit]]s such as [[microprocessor]]s and memory devices contain thousands to billions of integrated MOSFETs on each device, providing the basic switching functions required to implement [[logic gate]]s and [[data storage]]. Discrete devices are widely used in applications such as [[switch mode power supplies]], [[variable-frequency drive]]s and other [[power electronics]] applications where each device may be switching thousands of watts. Radio-frequency amplifiers up to the [[UHF]] spectrum use MOSFET transistors as analog signal and power amplifiers. Radio systems also use MOSFETs as oscillators, or [[frequency mixer|mixer]]s to convert frequencies. MOSFET devices are also applied in audio-frequency power amplifiers for public address systems, [[sound reinforcement]] and home and automobile sound systems{{citation needed |date=December 2015}}

=== MOS integrated circuits ===
Following the development of [[clean room]]s to reduce contamination to levels never before thought necessary, and of [[photolithography]]<ref>{{ cite web | url = http://www.computerhistory.org/semiconductor/timeline/1955-Photolithography.html |publisher=Computer History Museum |title=1955&nbsp;– Photolithography Techniques Are Used to Make Silicon Devices |access-date=2012-06-02}}</ref> and the [[planar process]] to allow circuits to be made in very few steps, the Si–SiO<sub>2</sub> system possessed the technical attractions of low cost of production (on a per circuit basis) and ease of integration. Largely because of these two factors, the MOSFET has become the most widely used type of transistor in the [[Institution of Engineering and Technology]] (IET).{{citation needed|date=March 2023}}

[[General Micro-electronics]] introduced the first commercial MOS integrated circuit in 1964.<ref>{{cite web|url=http://www.computerhistory.org/semiconductor/timeline/1964-Commecial.htm|title=1964 – First Commercial MOS IC Introduced}}{{Dead link|date=August 2018 |bot=InternetArchiveBot |fix-attempted=yes }}</ref> Additionally, the method of coupling two complementary MOSFETs (P-channel and N-channel) into one high/low switch, known as CMOS, means that digital circuits dissipate very little power except when actually switched.

The [[microprocessor chronology|earliest microprocessors]] starting in 1970 were all MOS microprocessors, fabricated entirely from [[PMOS logic]] or fabricated entirely from [[nMOS logic]]. In the 1970s, MOS microprocessors were often contrasted with CMOS microprocessors and bipolar bit-slice processors.<ref name="cushman">{{cite web|first=Robert H.|last=Cushman|url=http://www.swtpc.com/mholley/Microprocessors/EDN_Sep_20_1975_6502.pdf|title=2-1/2-generation μP's-$10 parts that perform like low-end mini's|publisher=EDN|date=20 September 1975|access-date=8 August 2013|archive-date=24 April 2016|archive-url=https://web.archive.org/web/20160424050556/http://www.swtpc.com/mholley/Microprocessors/EDN_Sep_20_1975_6502.pdf|url-status=dead}}</ref>

=== CMOS circuits ===
The MOSFET is used in digital complementary metal–oxide–semiconductor ([[CMOS]]) logic,<ref>{{cite web|url=http://www.computerhistory.org/semiconductor/timeline/1963-CMOS.html |title=Computer History Museum&nbsp;– The Silicon Engine {{pipe}} 1963&nbsp;– Complementary MOS Circuit Configuration is Invented |publisher=Computerhistory.org |accessdate=2012-06-02}}</ref> which uses p- and n-channel MOSFETs as building blocks. Overheating is a major concern in [[integrated circuit]]s since ever more transistors are packed into ever smaller chips. CMOS logic reduces power consumption because no current flows (ideally), and thus no [[Power (physics)|power]] is consumed, except when the inputs to [[logic gate]]s are being switched. CMOS accomplishes this current reduction by complementing every nMOS FET with a pMOS FET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOS FET to conduct and the pMOS FET not to conduct and a low voltage on the gates causes the reverse. During the switching time as the voltage goes from one state to another, both MOSFETs will conduct briefly. This arrangement greatly reduces power consumption and heat generation.

==== Digital ====
The growth of digital technologies like the [[microprocessor]] has provided the motivation to advance MOSFET technology faster than any other type of silicon-based transistor.<ref>{{cite web|url=http://www.computerhistory.org/microprocessors/ |title=Computer History Museum&nbsp;– Exhibits&nbsp;– Microprocessors |publisher=Computerhistory.org |accessdate=2012-06-02}}</ref> A big advantage of MOSFETs for digital switching is that the oxide layer between the gate and the channel prevents DC current from flowing through the gate, further reducing power consumption and giving a very large input impedance. The insulating oxide between the gate and channel effectively isolates a MOSFET in one logic stage from earlier and later stages, which allows a single MOSFET output to drive a considerable number of MOSFET inputs. Bipolar transistor-based logic (such as [[transistor-transistor logic|TTL]]) does not have such a high fanout capacity. This isolation also makes it easier for the designers to ignore to some extent loading effects between logic stages independently. That extent is defined by the operating frequency: as frequencies increase, the input impedance of the MOSFETs decreases.

==== Analog ====
The MOSFET's advantages in digital circuits do not translate into supremacy in all [[analog circuit]]s. The two types of circuit draw upon different features of transistor behavior. Digital circuits switch, spending most of their time either fully on or fully off. The transition from one to the other is only of concern with regards to speed and charge required. Analog circuits depend on operation in the transition region where small changes to ''V''{{sub|gs}} can modulate the output (drain) current. The JFET and [[bipolar junction transistor]] (BJT) are preferred for accurate matching (of adjacent devices in integrated circuits), higher [[transconductance]] and certain temperature characteristics which simplify keeping performance predictable as circuit temperature varies.

Nevertheless, MOSFETs are widely used in many types of analog circuits because of their own advantages (zero gate current, high and adjustable output impedance and improved robustness vs. BJTs which can be permanently degraded by even lightly breaking down the emitter-base).{{Vague|date=January 2016}} The characteristics and performance of many analog circuits can be scaled up or down by changing the sizes (length and width) of the MOSFETs used. By comparison, bipolar transistors follow a different [[scaling law]]. MOSFETs' ideal characteristics regarding gate current (zero) and drain-source offset voltage (zero) also make them nearly ideal switch elements, and also make [[switched capacitor]] analog circuits practical. In their linear region, MOSFETs can be used as precision resistors, which can have a much higher controlled resistance than BJTs. In high power circuits, MOSFETs sometimes have the advantage of not suffering from [[thermal runaway]] as BJTs do.{{Dubious|reason=Depends on circuit topology?|date=January 2016}} This means that complete analog circuits can be made on a silicon chip in a much smaller space and with simpler fabrication techniques. MOSFETS are ideally suited to switch inductive loads because of tolerance to [[Counter-electromotive force|inductive kickback]].

Some ICs combine analog and digital MOSFET circuitry on a single [[mixed-signal integrated circuit]], making the needed board space even smaller. This creates a need to isolate the analog circuits from the digital circuits on a chip level, leading to the use of isolation rings and [[silicon on insulator]] (SOI). Since MOSFETs require more space to handle a given amount of power than a BJT, fabrication processes can incorporate BJTs and MOSFETs into a single device. Mixed-transistor devices are called bi-FETs (bipolar FETs) if they contain just one BJT-FET and [[BiCMOS]] (bipolar-CMOS) if they contain complementary BJT-FETs. Such devices have the advantages of both insulated gates and higher current density.

=== Analog switches ===
{{Unreferenced section|date=September 2016}}

Bidirectional analog switches pass analog signals when on or block them (by presenting a high impedance) when off. The MOSFETs used are typically symmetrical, such that their drain and source exchange places depending on the relative voltages of their electrodes; at any moment, the source would be the more negative side for an nMOS or the more positive side for a pMOS. All of these switches are limited on what signals they can pass or stop by their gate-source, gate-drain and source–drain voltages; exceeding the voltage, current, or power limits will potentially damage the switch. See [[#Power MOSFET|Power MOSFET]] subsection down below.

==== Single-type ====
This analog switch uses a four-terminal symmetrical MOSFET of either P or N type.

In the case of an n-type switch, the body is connected to the most negative supply (usually GND) and the gate is used as the switch control. Whenever the gate voltage exceeds the source voltage by at least a threshold voltage, the MOSFET conducts. The higher the voltage, the more the MOSFET can conduct. An nMOS switch passes all voltages less than V{{sub|gate}}&nbsp;−&nbsp;''V''<sub>thresold_nMOS</sub>, but passes lower voltages better than higher ones. When the switch is conducting, it typically operates in the linear (or ohmic) mode of operation, since the source and drain voltages will typically be nearly equal.

In the case of a pMOS, the body is connected to the most positive voltage, and the gate is brought to a lower potential to turn the switch on. The pMOS switch passes all voltages higher than V{{sub|gate}}&nbsp;−&nbsp;''V''<sub>thresold_pMOS</sub> (note: enhancement-mode pMOS FETs have a negative threshold voltage), but passes higher voltages better than lower ones.

==== Dual-type (CMOS) ====
{{Main article|Transmission gate#Electronic switch}}
[[File:Transmission gate.svg|thumb|The CMOS analog switch passes the signal through both a pMOS (QP) and an nMOS (QN). When ST is high, the switch provides a low resistance between UA and UB, either of which could be considered the input or output. ]]
This "complementary" or CMOS type of switch uses one pMOS and one nMOS FET connected in parallel to counteract the limitations of the single-type switch.<ref>{{Cite web |last1=Wong |first1=James |last2=Whitmore |first2=Jerry |title=Section 2: Multiplexing Signals with Analog Switches |url=https://www.analog.com/media/en/training-seminars/design-handbooks/system-applications-guide/Section2.pdf}}</ref> When used in digital logic it is called a [[transmission gate]]. The FETs have their drains and sources connected in parallel, the body of the pMOS is connected to the high potential (Vpos in diagram) and the body of the nMOS is connected to the low potential (Vneg). To turn the switch on, the gate of the pMOS is driven to the low potential and the gate of the nMOS is driven to the high potential. For voltages between Vpos&nbsp;−&nbsp;''V''<sub>thresold_nMOS</sub> and Vneg&nbsp;−&nbsp;''V''<sub>thresold_pMOS</sub>, both FETs conduct the signal, though with the nMOS passing lower voltages better while the pMOS passes higher voltages better. For voltages less than Vneg&nbsp;−&nbsp;''V''<sub>thresold_pMOS</sub>, the nMOS conducts alone. For voltages greater than Vpos&nbsp;−&nbsp;''V''<sub>thresold_nMOS</sub>, the pMOS conducts alone.

The voltage limits for this switch are the gate-source, gate-drain and source-drain voltage limits for both FETs. Also, the pMOS is typically two to three times wider than the nMOS, so the switch will be balanced for speed in the two directions.

[[Three-state logic|Tri-state circuitry]] sometimes incorporates a CMOS MOSFET switch on its output to provide for a low-ohmic, full-range output when on, and a high-ohmic, mid-level signal when off.

== Construction ==

=== Gate material ===
The primary criterion for the gate material is that it is a good [[conductor (material)|conductor]]. Highly doped [[polycrystalline silicon]] is an acceptable but certainly not ideal conductor, and also suffers from some more technical deficiencies in its role as the standard gate material. Nevertheless, there are several reasons favoring use of polysilicon:

# The [[threshold voltage]] (and consequently the drain to source on-current) is modified by the [[work function]] difference between the gate material and channel material. Because polysilicon is a semiconductor, its work function can be modulated by adjusting the type and level of doping. Furthermore, because polysilicon has the same [[bandgap]] as the underlying silicon channel, it is quite straightforward to tune the work function to achieve low threshold voltages for both nMOS and pMOS devices. By contrast, the work functions of metals are not easily modulated, so tuning the [[work function]] to obtain [[low threshold voltage]]s (LVT) becomes a significant challenge. Additionally, obtaining low-threshold devices on both pMOS and nMOS devices sometimes requires the use of different metals for each device type.
# The silicon-SiO<sub>2</sub> interface has been well studied and is known to have relatively few defects. By contrast many metal-insulator interfaces contain significant levels of defects which can lead to [[Fermi level pinning]], charging, or other phenomena that ultimately degrade device performance.
# In the MOSFET [[IC fabrication]] process, it is preferable to deposit the gate material prior to certain high-temperature steps in order to make better-performing transistors. Such high temperature steps would melt some metals, limiting the types of metal that can be used in a metal-gate-based process.

While polysilicon gates have been the de facto standard for the last twenty years, they do have some disadvantages which have led to their likely future replacement by metal gates. These disadvantages include:

* Polysilicon is not a great conductor (approximately 1000 times more resistive than metals) which reduces the signal propagation speed through the material. The resistivity can be lowered by increasing the level of doping, but even highly doped polysilicon is not as conductive as most metals. To improve conductivity further, sometimes a high-temperature metal such as [[tungsten]], [[titanium]], [[cobalt]], and more recently [[nickel]] is alloyed with the top layers of the polysilicon. Such a blended material is called [[silicide]]. The silicide-polysilicon combination has better electrical properties than polysilicon alone and still does not melt in subsequent processing. Also the threshold voltage is not significantly higher than with polysilicon alone, because the silicide material is not near the channel. The process in which silicide is formed on both the gate electrode and the source and drain regions is sometimes called [[salicide]], self-aligned silicide.
* When the transistors are extremely scaled down, it is necessary to make the gate dielectric layer very thin, around 1&nbsp;nm in state-of-the-art technologies. A phenomenon observed here is the so-called [[poly depletion]], where a depletion layer is formed in the gate polysilicon layer next to the gate dielectric when the transistor is in the inversion. To avoid this problem, a metal gate is desired. A variety of metal gates such as [[tantalum]], tungsten, [[tantalum nitride]], and [[titanium nitride]] are used, usually in conjunction with [[high-κ dielectric]]s. An alternative is to use fully silicided polysilicon gates, a process known as [[FUSI]].

Present high performance CPUs use metal gate technology, together with [[high-κ dielectric]]s, a combination known as ''high-κ, metal gate'' (HKMG). The disadvantages of metal gates are overcome by a few techniques:<ref>{{cite web|archive-url=https://web.archive.org/web/20100919004000/http://www.revera.com/VeraFlex/hkmg_approaches.htm|archive-date=19 September 2010|url= http://www.revera.com/VeraFlex/hkmg_approaches.htm|title=ReVera's FinFET Control|website=revera.com}}</ref>

# The threshold voltage is tuned by including a thin "work function metal" layer between the high-κ dielectric and the main metal. This layer is thin enough that the total work function of the gate is influenced by both the main metal and thin metal work functions (either due to alloying during annealing, or simply due to the incomplete screening by the thin metal). The threshold voltage thus can be tuned by the thickness of the thin metal layer.
# High-κ dielectrics are now well studied, and their defects are understood.
# HKMG processes exist that do not require the metals to experience high temperature anneals; other processes select metals that can survive the annealing step.

=== Insulator ===
As devices are made smaller, insulating layers are made thinner, often through steps of [[thermal oxidation]] or localised oxidation of silicon ([[LOCOS]]). For nano-scaled devices, at some point [[quantum tunneling|tunneling]] of carriers through the insulator from the channel to the gate electrode takes place. To reduce the resulting [[leakage (semiconductors)|leakage]] current, the insulator can be made thinner by choosing a material with a higher dielectric constant. To see how thickness and dielectric constant are related, note that [[Gauss's law]] connects field to charge as:

: <math>Q = \kappa \epsilon_0 E, </math>

with ''Q'' = charge density, κ = dielectric constant, ε<sub>0</sub> = permittivity of empty space and ''E'' = electric field. From this law it appears the same charge can be maintained in the channel at a lower field provided κ is increased. The voltage on the gate is given by:

: <math>V_\text{G} = V_\text{ch} + E\, t_\text{ins} = V_\text{ch} + \frac{Q t_\text{ins}}{\kappa \epsilon_0}, </math>

with ''V''<sub>G</sub> = gate voltage, ''V''<sub>ch</sub> = voltage at channel side of insulator, and ''t''<sub>ins</sub> = insulator thickness. This equation shows the gate voltage will not increase when the insulator thickness increases, provided κ increases to keep ''t''<sub>ins</sub> / κ = constant (see the article on high-κ dielectrics for more detail, and the section in this article on [[#Increased gate-oxide leakage|gate-oxide leakage]]).

The insulator in a MOSFET is a dielectric which can in any event be silicon oxide, formed by [[LOCOS]] but many other dielectric materials are employed. The generic term for the dielectric is gate dielectric since the dielectric lies directly below the gate electrode and above the channel of the MOSFET.

=== Junction design ===
The source-to-body and drain-to-body [[p–n junction|junctions]] are the object of much attention because of three major factors: their design affects the [[Current–voltage characteristic|current–voltage (''I–V'') characteristics]] of the device, lowering output resistance, and also the speed of the device through the loading effect of the junction [[capacitance]]s, and finally, the component of stand-by power dissipation due to junction leakage.
[[file:MOSFET junction structure.png|thumb|upright=1.2|MOSFET showing shallow junction extensions, raised source and drain and halo implant. Raised source and drain are separated from gate by oxide spacers.]]
The drain induced barrier lowering of the threshold voltage and [[channel length modulation]] effects upon ''I-V'' curves are reduced by using shallow junction extensions. In addition, ''halo'' doping can be used, that is, the addition of very thin heavily doped regions of the same doping type as the body tight against the junction walls to limit the extent of [[depletion region]]s.<ref name=Colinge>{{ cite book | first1 = Jean-Pierre|last1=Colinge |first2=Cynthia A.|last2=Colinge | title=Physics of Semiconductor Devices | year = 2002 | page = 233, Figure 7.46 | publisher = Springer | location = Dordrecht | isbn = 978-1-4020-7018-1 | url = https://books.google.com/books?id=ZcDE-ENKh2gC&pg=PA233}}</ref>

The capacitive effects are limited by using raised source and drain geometries that make most of the contact area border thick dielectric instead of silicon.<ref name=Weber>{{ cite book | editor1-first= Eicke R.|editor1-last=Weber|editor2-first=Jarek|editor2-last=Dabrowski| title = Predictive Simulation of Semiconductor Processing: Status and Challenges | year = 2004 | page = 5, Figure 1.2 | publisher = Springer | location = Dordrecht | isbn = 978-3-540-20481-7 | url = https://books.google.com/books?id=oCH9tiY7VeoC&pg=PA5}}</ref>

These various features of junction design are shown (with [[artistic license]]) in the figure.

== Scaling ==
{{Essay|section|date=September 2016}}
{{Further|Dennard scaling}}
[[file:Intel gate length trend.PNG|thumb|upright=1.2|Trend of Intel CPU transistor gate length]]
[[file:WIde-swing MOSFET mirror.PNG|thumb|upright=1.2|MOSFET version of gain-boosted [[current mirror]]; M<sub>1</sub> and M<sub>2</sub> are in active mode, while M<sub>3</sub> and M<sub>4</sub> are in Ohmic mode, and act like resistors. The operational amplifier provides feedback that maintains a high output resistance.]]

Over the past decades, the MOSFET (as used for digital logic) has continually been scaled down in size; typical MOSFET channel lengths were once several [[micrometre]]s, but modern integrated circuits are incorporating MOSFETs with channel lengths of tens of nanometers. [[Robert Dennard]]'s work on [[scaling law|scaling theory]] was pivotal in recognising that this ongoing reduction was possible. Intel began production of a process featuring a 32&nbsp;nm feature size (with the channel being even shorter) in late 2009. The semiconductor industry maintains a "roadmap", the [[International Technology Roadmap for Semiconductors|ITRS]],<ref>{{cite web |url=http://www.itrs.net |title=International Technology Roadmap for Semiconductors |url-status=dead |archive-url=https://web.archive.org/web/20151228041321/http://www.itrs.net/ |archive-date=2015-12-28 }}</ref> which sets the pace for MOSFET development. Historically, the difficulties with decreasing the size of the MOSFET have been associated with the semiconductor device fabrication process, the need to use very low voltages, and with poorer electrical performance necessitating circuit redesign and innovation (small MOSFETs exhibit higher leakage currents and lower output resistance).

Smaller MOSFETs are desirable for several reasons. The main reason to make transistors smaller is to pack more and more devices in a given chip area. This results in a chip with the same functionality in a smaller area, or chips with more functionality in the same area. Since fabrication costs for a [[semiconductor wafer]] are relatively fixed, the cost per integrated circuits is mainly related to the number of chips that can be produced per wafer. Hence, smaller ICs allow more chips per wafer, reducing the price per chip. In fact, over the past 30 years the number of transistors per chip has been doubled every 2–3 years once a new technology node is introduced. For example, the number of MOSFETs in a microprocessor fabricated in a [[45 nm]] technology can well be twice as many as in a [[65 nm]] chip. This doubling of transistor density was first observed by [[Gordon Moore]] in 1965 and is commonly referred to as [[Moore's law]].<ref>{{cite web | title = 1965&nbsp;– "Moore's Law" Predicts the Future of Integrated Circuits | work = Computer History Museum | url = http://www.computerhistory.org/semiconductor/timeline/1965-Moore.html}}</ref> It is also expected that smaller transistors switch faster. For example, one approach to size reduction is a scaling of the MOSFET that requires all device dimensions to reduce proportionally. The main device dimensions are the channel length, channel width, and oxide thickness. When they are scaled down by equal factors, the transistor channel resistance does not change, while gate capacitance is cut by that factor. Hence, the [[RC delay]] of the transistor scales with a similar factor. While this has been traditionally the case for the older technologies, for the state-of-the-art MOSFETs reduction of the transistor dimensions does not necessarily translate to higher chip speed because the delay due to interconnections is more significant.

Producing MOSFETs with channel lengths much smaller than a [[micrometre]] is a challenge, and the difficulties of semiconductor device fabrication are always a limiting factor in advancing integrated circuit technology. Though processes such as [[atomic layer deposition|ALD]] have improved fabrication for small components, the small size of the MOSFET (less than a few tens of nanometers) has created operational problems:

===Higher subthreshold conduction===
As MOSFET geometries shrink, the voltage that can be applied to the gate must be reduced to maintain reliability. To maintain performance, the threshold voltage of the MOSFET has to be reduced as well. As threshold voltage is reduced, the transistor cannot be switched from complete turn-off to complete turn-on with the limited voltage swing available; the circuit design is a compromise between strong current in the ''on'' case and low current in the ''off'' case, and the application determines whether to favor one over the other. Subthreshold leakage (including subthreshold conduction, gate-oxide leakage and reverse-biased junction leakage), which was ignored in the past, now can consume upwards of half of the total power consumption of modern high-performance VLSI chips.<ref name=Roy>{{ cite book | first1 =Kaushik|last1=Roy |first2=Kiat Seng|last2=Yeo | title=Low Voltage, Low Power VLSI Subsystems | year = 2004 | page = Fig. 2.1, p. 44, Fig. 1.1, p. 4 | publisher = McGraw-Hill Professional | isbn = 978-0-07-143786-8 | url = https://books.google.com/books?id=jXm4pNxCSCYC&pg=PA4 | no-pp = true }}</ref><ref name=Goodnick>{{ cite book | first1 =Dragica|last1=Vasileska |author1-link=Dragica Vasileska|first2=Stephen|last2=Goodnick | title=Computational Electronics | year = 2006 | page = 103 | publisher = Morgan & Claypool | isbn = 978-1-59829-056-1 | url = https://books.google.com/books?id=DBPnzqy5Fd8C&pg=PA103 }}</ref>

===Increased gate-oxide leakage===
The gate oxide, which serves as insulator between the gate and channel, should be made as thin as possible to increase the channel conductivity and performance when the transistor is on and to reduce subthreshold leakage when the transistor is off. However, with current gate oxides with a thickness of around 1.2&nbsp;[[nanometer|nm]] (which in silicon is ~5&nbsp;[[atom]]s thick) the [[quantum mechanical]] phenomenon of [[electron tunneling]] occurs between the gate and channel, leading to increased power consumption. [[Silicon dioxide]] has traditionally been used as the gate insulator. Silicon dioxide however has a modest dielectric constant. Increasing the dielectric constant of the gate dielectric allows a thicker layer while maintaining a high capacitance (capacitance is proportional to dielectric constant and inversely proportional to dielectric thickness). All else equal, a higher dielectric thickness reduces the [[quantum tunneling]] current through the dielectric between the gate and the channel.

Insulators that have a larger [[dielectric constant]] than silicon dioxide (referred to as [[high-κ dielectric]]s), such as group IVb metal silicates e.g. [[hafnium]] and [[zirconium]] silicates and oxides are being used to reduce the gate leakage from the 45 nanometer technology node onwards. On the other hand, the barrier height of the new gate insulator is an important consideration; the difference in [[conduction band]] energy between the semiconductor and the dielectric (and the corresponding difference in [[valence band]] energy) also affects leakage current level. For the traditional gate oxide, silicon dioxide, the former barrier is approximately 8 [[Electronvolt|eV]]. For many alternative dielectrics the value is significantly lower, tending to increase the tunneling current, somewhat negating the advantage of higher dielectric constant. The maximum gate-source voltage is determined by the strength of the electric field able to be sustained by the gate dielectric before significant leakage occurs. As the insulating dielectric is made thinner, the electric field strength within it goes up for a fixed voltage. This necessitates using lower voltages with the thinner dielectric.

===Increased junction leakage===
To make devices smaller, junction design has become more complex, leading to higher [[Doping (semiconductors)|doping]] levels, shallower junctions, "halo" doping and so forth,<ref>{{cite web|url=http://frontiersemi.com/pdf/papers/RsLransist.pdf |title=Frontier Semiconductor Paper |accessdate=2012-06-02 |url-status=dead |archiveurl=https://web.archive.org/web/20120227064415/http://frontiersemi.com/pdf/papers/RsLransist.pdf |archivedate=February 27, 2012 }}</ref><ref name=Chen>{{ cite book | first = Wai-Kai|last=Chen | title = The VLSI Handbook | page = Fig. 2.28, p. 2–22 | year = 2006 | publisher = CRC Press | isbn = 978-0-8493-4199-1 | url = https://books.google.com/books?id=NDdsjtTLTd0C&pg=PT49 | no-pp = true}}</ref> all to decrease drain-induced barrier lowering (see the section on [[#Junction design|junction design]]). To keep these complex junctions in place, the annealing steps formerly used to remove damage and electrically active defects must be curtailed<ref>{{cite journal |doi=10.1557/PROC-765-D7.4 |first1=R. |last1=Lindsay |title=A Comparison of Spike, Flash, SPER and Laser Annealing for 45nm CMOS |journal=MRS Proceedings |volume=765 |year=2011 |last2=Pawlak |last3=Kittl |last4=Henson |last5=Torregiani |last6=Giangrandi |last7=Surdeanu |last8=Vandervorst |last9=Mayur |last10=Ross |last11=McCoy |last12=Gelpey |last13=Elliott |last14=Pages |last15=Satta |last16=Lauwers |last17=Stolk |last18=Maex |article-number=D7.4 }}</ref> increasing junction leakage. Heavier doping is also associated with thinner depletion layers and more recombination centers that result in increased leakage current, even without lattice damage.

===Drain-induced barrier lowering and ''V''<sub>T</sub> roll off===
[[Drain-induced barrier lowering]] (DIBL) and ''V''<sub>T</sub> roll off: Because of the [[short-channel effect]], channel formation is not entirely done by the gate, but now the drain and source also affect the channel formation. As the channel length decreases, the depletion regions of the source and drain come closer together and make the threshold voltage (''V''<sub>T</sub>) a function of the length of the channel. This is called ''V''<sub>T</sub> roll-off. ''V''<sub>T</sub> also becomes function of drain to source voltage ''V''<sub>DS</sub>. As we increase the ''V''<sub>DS</sub>, the depletion regions increase in size, and a considerable amount of charge is depleted by the ''V''<sub>DS</sub>. The gate voltage required to form the channel is then lowered, and thus, the ''V''<sub>T</sub> decreases with an increase in ''V''<sub>DS</sub>. This effect is called drain induced barrier lowering (DIBL).

===Lower output resistance===
For analog operation, good gain requires a high MOSFET output impedance, which is to say, the MOSFET current should vary only slightly with the applied drain-to-source voltage. As devices are made smaller, the influence of the drain competes more successfully with that of the gate due to the growing proximity of these two electrodes, increasing the sensitivity of the MOSFET current to the drain voltage. To counteract the resulting decrease in output resistance, circuits are made more complex, either by requiring more devices, for example the [[cascode]] and [[cascade amplifier]]s, or by feedback circuitry using [[operational amplifiers]], for example a circuit like that in the adjacent figure.

===Lower transconductance===
The [[transconductance]] of the MOSFET decides its gain and is proportional to hole or [[electron mobility]] (depending on device type), at least for low drain voltages. As MOSFET size is reduced, the fields in the channel increase and the dopant impurity levels increase. Both changes reduce the carrier mobility, and hence the transconductance. As channel lengths are reduced without proportional reduction in drain voltage, raising the electric field in the channel, the result is velocity saturation of the carriers, limiting the current and the transconductance.

===Interconnect capacitance===
Traditionally, switching time was roughly proportional to the gate capacitance of gates. However, with transistors becoming smaller and more transistors being placed on the chip, [[capacitance|interconnect capacitance]] (the capacitance of the metal-layer connections between different parts of the chip) is becoming a large percentage of capacitance.<ref>{{cite web|url=http://www.research.ibm.com/journal/rd/293/ibmrd2903G.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.research.ibm.com/journal/rd/293/ibmrd2903G.pdf |archive-date=2022-10-09 |url-status=live|title=VLSI wiring capacitance|date=9 February 2021 |publisher=IBM Journal of Research and Development}}{{dead link|date=June 2015}}</ref><ref name=Soudris>{{ cite book | editor1-first = D.|editor1-last= Soudris|editor2-first=P.|editor2-last=Pirsch|editor3-first=E.|editor3-last=Barke | title = Integrated Circuit Design: Power and Timing Modeling, Optimization, and Simulation (10th Int. Workshop) | year = 2000 | page = 38 | publisher = Springer | isbn = 978-3-540-41068-3 | url = https://books.google.com/books?id=TGQxMLsGzVUC&pg=PA38}}</ref> Signals have to travel through the interconnect, which leads to increased delay and lower performance.

===Heat production===
The ever-increasing density of MOSFETs on an integrated circuit creates problems of substantial localized heat generation that can impair circuit operation. Circuits operate more slowly at high temperatures, and have reduced reliability and shorter lifetimes. Heat sinks and other cooling devices and methods are now required for many integrated circuits including microprocessors. [[Power MOSFET]]s are at risk of [[thermal runaway]]. As their on-state resistance rises with temperature, if the load is approximately a constant-current load then the power loss rises correspondingly, generating further heat. When the [[heatsink]] is not able to keep the temperature low enough, the junction temperature may rise quickly and uncontrollably, resulting in destruction of the device.

===Process variations===
With MOSFETs becoming smaller, the number of atoms in the silicon that produce many of the transistor's properties is becoming fewer, with the result that control of dopant numbers and placement is more erratic. During chip manufacturing, random process variations affect all transistor dimensions: length, width, junction depths, oxide thickness ''etc.'', and become a greater percentage of overall transistor size as the transistor shrinks. The transistor characteristics become less certain, more statistical. The random nature of manufacture means we do not know which particular example MOSFETs actually will end up in a particular instance of the circuit. This uncertainty forces a less optimal design because the design must work for a great variety of possible component MOSFETs. See [[Process variation (semiconductor)|process variation]], [[design for manufacturability]], [[reliability engineering]], and [[statistical process control]].<ref name=Boning>{{ cite book |first1=Michael|last1=Orshansky |first2=Sani |last2=Nassif |first3=Duane |last3=Boning |title=Design for Manufacturability And Statistical Design: A Constructive Approach |date=2007 | publisher=Springer |location=New York |url=https://www.amazon.com/gp/reader/0387309284/ref=sib_dp_pt/002-1766819-0058402#reader-link|isbn=9780387309286 }}</ref>

===Modeling challenges===
Modern ICs are computer-simulated with the goal of obtaining working circuits from the first manufactured lot. As devices are miniaturized, the complexity of the processing makes it difficult to predict exactly what the final devices look like, and modeling of physical processes becomes more challenging as well. In addition, microscopic variations in structure due simply to the probabilistic nature of atomic processes require statistical (not just deterministic) predictions. These factors combine to make adequate simulation and "right the first time" manufacture difficult.

== Other types ==

=== Dual-gate ===
[[file:FINFET MOSFET.png|thumb|upright=1.2|A [[FinFET]]]]
{{Main|Multigate device}}

The dual-gate MOSFET has a [[tetrode]] configuration, where both gates control the current in the device. It is commonly used for small-signal devices in radio frequency applications where biasing the drain-side gate at constant potential reduces the gain loss caused by [[Miller effect]], replacing two separate transistors in [[cascode]] configuration. Other common uses in RF circuits include gain control and mixing (frequency conversion). The ''tetrode'' description, though accurate, does not replicate the vacuum-tube tetrode. Vacuum-tube tetrodes, using a screen grid, exhibit much lower grid-plate capacitance and much higher output impedance and voltage gains than triode vacuum tubes. These improvements are commonly an order of magnitude (10 times) or considerably more. Tetrode transistors (whether bipolar junction or field-effect) do not exhibit improvements of such a great degree.

The [[FinFET]] is a double-gate [[silicon-on-insulator]] device, one of a number of geometries being introduced to mitigate the effects of short channels and reduce drain-induced barrier lowering. The ''fin'' refers to the narrow channel between source and drain. A thin insulating oxide layer on either side of the fin separates it from the gate. SOI FinFETs with a thick oxide on top of the fin are called ''double-gate'' and those with a thin oxide on top as well as on the sides are called ''triple-gate'' FinFETs.<ref name=SOI>{{cite book |title=Frontiers in electronics: future chips : proceedings of the 2002 Workshop on Frontiers in Electronics (WOFE-02), St Croix, Virgin Islands, USA, 6–11 January 2002 |year=2002|publisher=World Scientific |chapter=Figure 12: Simplified cross section of FinFET double-gate MOSFET |isbn=978-981-238-222-1|first1=P. M.|last1= Zeitzoff |first2=J. A.|last2= Hutchby |first3=H. R.|last3= Huff |editor1-first=Yoon-Soo|editor1-last=Park |editor2-first=Michael|editor2-last=Shur |editor3-first=William|editor3-last=Tang |chapter-url=https://books.google.com/books?id=uC6h4-OEWsMC&pg=PA82 |page=82}}</ref><ref>{{cite book |title=Silicon-on-Insulator Technology and Devices |chapter=Comparison of SOI FinFETs and bulk FinFETs: Figure 2 |first1=J.-H.|last1= Lee |first2=J.-W.|last2= Lee |first3=H.-A.-R.|last3= Jung |first4=B.-K.|last4= Choi |chapter-url=https://books.google.com/books?id=OVbb42PwZysC&pg=PA102 |page=102 |publisher=The Electrochemical Society |year=2009 |isbn=978-1-56677-712-4}}</ref>

=== Depletion-mode ===
There are ''depletion-mode'' MOSFET devices, which are less commonly used than the standard ''enhancement-mode'' devices already described. These are MOSFET devices that are doped so that a channel exists even with zero voltage from gate to source. To control the channel, a negative voltage is applied to the gate (for an n-channel device), depleting the channel, which reduces the current flow through the device. In essence, the depletion-mode device is equivalent to a [[normally closed]] (on) switch, while the enhancement-mode device is equivalent to a [[normally open]] (off) switch.<ref>{{cite encyclopedia
 | title= Depletion Mode
 | encyclopedia= Techweb
 | date= 29 January 2010
 | location= 
 | id= 
 | url= http://www.techweb.com/encyclopedia/imageFriendly.jhtml;?term=depletion+mode
 | accessdate= 27 November 2010
 | archive-date= 31 October 2010
 | archive-url= https://web.archive.org/web/20101031061941/http://www.techweb.com/encyclopedia/imageFriendly.jhtml;?term=depletion+mode
 | url-status= dead
 }}</ref>

Due to their low [[noise figure]] in the [[RF]] region, and better [[gain (electronics)#Power gain|gain]], these devices are often preferred to [[bipolar junction transistors|bipolars]] in [[RF front end|RF front-ends]] such as in [[TV]] sets.

Depletion-mode MOSFET families include the BF960 by [[Siemens]] and [[Telefunken]], and the BF980 in the 1980s by [[Philips]] (later to become [[NXP Semiconductors]]), whose derivatives are still used in [[automatic gain control|AGC]] and RF [[frequency mixer|mixer]] front-ends.

=== Metal–insulator–semiconductor field-effect transistor (MISFET) ===
Metal–insulator–semiconductor field-effect-transistor,<ref>{{cite web
 | url = http://www.semi1source.com/glossary/default.asp?searchterm=MIS
 | title = MIS
 | work = Semiconductor Glossary
 | access-date = 2017-05-14
 | archive-date = 2017-01-22
 | archive-url = https://web.archive.org/web/20170122153452/http://www.semi1source.com/glossary/default.asp?searchterm=MIS
 | url-status = dead
 }}</ref><ref>
{{cite book
 | title = Semiconducting polymers: chemistry, physics and engineering
 | first1= Georges | last1 = Hadziioannou
 | first2=George G. | last2=Malliaras
 | publisher = Wiley-VCH
 | year = 2007
 | isbn = 978-3-527-31271-9
 | url = https://books.google.com/books?id=D37RykvobWwC&dq=misfet+metal-insulator-semiconductor-field-effect-transistor&pg=PA532
}}</ref><ref name=Jones>
{{cite book
 | title = Organic Molecular Solids: Properties and Applications
 | first = William | last=Jones
 | publisher = CRC Press
 | year = 1997
 | isbn = 978-0-8493-9428-7
 | url = https://books.google.com/books?id=8sb1kwH6EgIC&dq=misfet+metal-insulator-semiconductor-field-effect-transistor&pg=PA350
}}</ref> or ''MISFET'', is a more general term than ''MOSFET'' and a synonym to ''insulated-gate field-effect transistor'' (IGFET). All MOSFETs are MISFETs, but not all MISFETs are MOSFETs.

The gate dielectric insulator in a MISFET is a substrate oxide (hence typically [[silicon dioxide]]) in a MOSFET, but other materials can also be employed. The [[gate dielectric]] lies directly below the [[gate electrode]] and above the [[channel (semiconductor)|channel]] of the MISFET. The term ''metal'' is historically used for the gate material, even though now it is usually [[doping (semiconductor)|highly doped]] [[polysilicon]] or some other [[non-metal]].

Insulator types may be:

* Silicon dioxide, in silicon MOSFETs 
* Organic insulators (e.g., undoped trans-[[polyacetylene]]; [[cyanoethyl]] [[pullulan]], CEP<ref>
{{cite journal
 | url=https://pubs.rsc.org/en/Content/ArticleLanding/2013/TC/C3TC30134F|title=High performance organic field-effect transistors using cyanoethyl pullulan (CEP) high-k polymer cross-linked with trimethylolpropane triglycidyl ether (TTE) at low temperatures
 | journal=Journal of Materials Chemistry C
|volume=1
 |issue=25
 |pages=3955
 |doi=10.1039/C3TC30134F
 |year=2013
 |last1=Xu
 |first1=Wentao
 |last2=Guo
 |first2=Chang
 |last3=Rhee
 |first3=Shi-Woo
 }}</ref>), for organic-based FETs.<ref name=Jones/>

=== NMOS logic ===
For devices of equal current driving capability, n-channel MOSFETs can be made smaller than p-channel MOSFETs, due to p-channel charge carriers ([[electron hole|holes]]) having lower [[electron mobility|mobility]] than do n-channel charge carriers ([[electrons]]), and producing only one type of MOSFET on a silicon substrate is cheaper and technically simpler. These were the driving principles in the design of [[nMOS logic]] which uses n-channel MOSFETs exclusively. However, neglecting [[leakage current]], unlike CMOS logic, nMOS logic consumes power even when no switching is taking place. With advances in technology, CMOS logic displaced nMOS logic in the mid-1980s to become the preferred process for digital chips.

=== Power MOSFET ===
[[file:Power mos cell layout.svg|thumb|upright=1.2|Cross section of a power MOSFET, with square cells. A typical transistor is constituted of several thousand cells.]]
{{Main|Power MOSFET}}

[[Power MOSFET]]s have a different structure.<ref>{{cite book|title=Power Semiconductor Devices|first=B. Jayant|last=Baliga|publisher=PWS publishing Company|location=Boston|isbn=978-0-534-94098-0|year=1996}}</ref> As with most power devices, the structure is vertical and not planar. Using a vertical structure, it is possible for the transistor to sustain both high blocking voltage and high current. The voltage rating of the transistor is a function of the doping and thickness of the N-[[epitaxial]] layer (see cross section), while the current rating is a function of the channel width (the wider the channel, the higher the current). In a planar structure, the current and breakdown voltage ratings are both a function of the channel dimensions (respectively width and length of the channel), resulting in inefficient use of the "silicon estate". With the vertical structure, the component area is roughly proportional to the current it can sustain, and the component thickness (actually the N-epitaxial layer thickness) is proportional to the breakdown voltage.<ref>{{cite web|url=http://www.element-14.com/community/docs/DOC-18273/l/power-mosfet-basics-understanding-mosfet-characteristics-associated-with-the-figure-of-merit|title=Power MOSFET Basics: Understanding MOSFET Characteristics Associated With The Figure of Merit|website=element14|accessdate=27 November 2010|archive-url=https://web.archive.org/web/20150405142659/http://www.element-14.com/community/docs/DOC-18273/l/power-mosfet-basics-understanding-mosfet-characteristics-associated-with-the-figure-of-merit |archive-date=5 April 2015 }}</ref>

Power MOSFETs with lateral structure are mainly used in high-end audio amplifiers and high-power PA systems. Their advantage is a better behaviour in the saturated region (corresponding to the linear region of a bipolar transistor) than the vertical MOSFETs. Vertical MOSFETs are designed for switching applications.<ref>{{cite web|url=http://www.element-14.com/community/docs/DOC-18275/l/power-mosfet-basics-understanding-gate-charge-and-using-it-to-assess-switching-performance|title=Power MOSFET Basics: Understanding Gate Charge and Using It To Assess Switching Performance|website=element14|accessdate=27 November 2010|archive-url=https://web.archive.org/web/20140630044120/http://www.element-14.com/community/docs/DOC-18275/l/power-mosfet-basics-understanding-gate-charge-and-using-it-to-assess-switching-performance |archive-date=30 June 2014 }}</ref>

=== Double-diffused metal–oxide–semiconductor ({{vanchor|DMOS}}) ===
There are ''[[LDMOS]]'' (lateral double-diffused metal oxide semiconductor) and ''VDMOS'' (vertical double-diffused metal oxide semiconductor). Most power MOSFETs are made using this technology.

=== Radiation-hardened-by-design (RHBD) ===
Semiconductor sub-micrometer and nanometer electronic circuits are the primary concern for operating within the normal tolerance in harsh [[radiation]] environments like [[outer space]]. One of the design approaches for making a [[radiation hardening|radiation-hardened-by-design]] (RHBD) device is enclosed-layout-transistor (ELT). Normally, the gate of the MOSFET surrounds the drain, which is placed in the center of the ELT. The source of the MOSFET surrounds the gate. Another RHBD MOSFET is called H-Gate. Both of these transistors have very low leakage currents with respect to radiation. However, they are large in size and take up more space on silicon than a standard MOSFET. In older STI (shallow trench isolation) designs, radiation strikes near the silicon oxide region cause the channel inversion at the corners of the standard MOSFET due to accumulation of radiation induced trapped charges. If the charges are large enough, the accumulated charges affect STI surface edges along the channel near the channel interface (gate) of the standard MOSFET. This causes a device channel inversion to occur along the channel edges, creating an off-state leakage path. Subsequently, the device turns on; this process severely degrades the reliability of circuits. The ELT offers many advantages, including an improvement of [[reliability (semiconductor)|reliability]] by reducing unwanted surface inversion at the gate edges which occurs in the standard MOSFET. Since the gate edges are enclosed in ELT, there is no gate oxide edge (STI at gate interface), and thus the transistor off-state leakage is reduced very much. Low-power microelectronic circuits including computers, communication devices, and monitoring systems in space shuttles and satellites are very different from what is used on earth. They are radiation (high-speed atomic particles like [[proton]] and [[neutron]], [[solar flare]] magnetic energy dissipation in Earth's space, energetic [[cosmic rays]] like [[X-ray]], [[gamma ray]] etc.) tolerant circuits. These special electronics are designed by applying different techniques using RHBD MOSFETs to ensure safe space journeys and safe space-walks of astronauts.

== Notes ==
{{NoteFoot}}

== See also ==
{{Portal|Electronics}}
<!-- alphabetical order please [[WP:SEEALSO]] -->
<!-- please add a short description [[WP:SEEALSO]], via {{subst:AnnotatedListOfLinks}} or {{Annotated link}} -->
* {{Annotated link |Floating-gate MOSFET}}
* {{Annotated link |BSIM}}
* {{Annotated link |ggNMOS}}
* {{Annotated link |High-electron-mobility transistor}}
* {{Annotated link |Polysilicon depletion effect}}
* {{Annotated link |Transistor model}}
* {{Annotated link |Power MOSFET#Body diode|Intrinsic diode}}
<!-- alphabetical order please [[WP:SEEALSO]] -->

== References ==
{{reflist}}

== External links ==
* [https://www.wecanfigurethisout.org/VL/MOS_kit.htm How Semiconductors and Transistors Work (MOSFETs)] WeCanFigureThisOut.org


{{commons category|MOSFET}}




{{Electronic components}}
{{Authority control}}

[[Category:Transistor types]]
[[Category:MOSFETs| ]]