View source for LPDDR

{{short description|Computer hardware}}
[[File:Tolino shine - controller board - Samsung K4X2G323PD-8GD8-1997.jpg|thumb|Mobile DDR: Samsung K4X2G323PD-8GD8]]
{{Memory types}}

'''Low-Power Double Data Rate''' ('''LPDDR''') is a type of [[synchronous dynamic random-access memory]] (SDRAM) designed to use less power than conventional memory. It is commonly used in [[smartphones]], [[tablet computers]], and [[laptops]], where reducing power consumption is important for battery life. For this reason, earlier versions of the technology were also known as '''Mobile DDR'''.

LPDDR differs from standard [[DDR SDRAM]] in both design and features, with changes that make it more suitable for mobile devices. Unlike DDR, which is typically installed in removable modules, LPDDR is usually soldered directly onto the device's motherboard to save space and improve efficiency. Although LPDDR uses a generational naming convention similar to that of DDR memory (such as LPDDR4 and DDR4), the two follow separate development standards, and the version numbers do not indicate that they share the same technologies.<ref name=":0">{{cite web |url=https://blogs.synopsys.com/committedtomemory/2014/01/10/when-is-lpddr3-not-lpddr3-when-its-ddr3l/ |title=When is LPDDR3 not LPDDR3? When it's DDR3L... |work=Committed to Memory blog |access-date=16 July 2021}}</ref> The LPDDR standard is developed and maintained by the [[JEDEC]] Solid State Technology Association.

==Bus width==
In contrast with standard SDRAM, used in stationary devices and laptops and usually connected over a 64-bit wide memory bus, LPDDR also permits 16- or 32-bit wide channels.<ref>{{cite web |url=http://processors.wiki.ti.com/index.php/LPDDR |title=LPDDR |work=[[Texas Instruments]] wiki |access-date=10 March 2015 |archive-date=5 March 2012 |archive-url=https://web.archive.org/web/20120305050353/http://processors.wiki.ti.com/index.php/LPDDR |url-status=dead }}</ref>

The "E" and "X" versions mark enhanced versions of the specifications. They formalize overclocking the memory array by usually 33%.

As with standard SDRAM, most generations double the internal fetch size and external transfer speed. (DDR4 and LPDDR5 being the exceptions.)

== Generations ==
{{Row hover highlight}}
{| class="mw-datatable wikitable sortable" style="text-align: center;"
|+ {{anchor|Comparison}} Comparison of LPDDR SDRAM generations
! scope="col" rowspan="2" | Gene-<br>ration
! scope="col" rowspan="2" | Release<br>year
! scope="col" colspan="3" | [[Chip (computing)|Chip]]
! scope="col" colspan="3" | [[Bus (computing)|Bus]]
! scope="col" rowspan="2" | [[Voltage]]<br />(V)
|- style="line-height:120%"
! scope="col" | [[Clock rate]]<br />(MHz)
! scope="col" | Cycle time<br />(ns)
! scope="col" | [[Prefetch buffer|Pre-<br>fetch]]
! scope="col" | Clock rate<br />(MHz)
! scope="col" | [[Transfer (computing)|Transfer rate]]<br />([[MT/s]])
! scope="col" | [[Bandwidth (computing)|Bandwidth]]<br />(MB/s)
|-
! scope="row" | 1
| rowspan="2" | 2006
| 200
| 
| rowspan="2" | 2''n''
| 200
| 400
| 50
| rowspan="2" | 1.8
|-
! scope="row" | 1E
| 266
| 
| 266
| 533
| 66.63
|-
! scope="row" | 2
| rowspan="2" | 2009
| 200
| 
| rowspan="2" | 4''n''
| 400
| 800
| 100
| rowspan="2" | {{Unbulleted list center
  | 1.2
  | 1.8
  }}
|-
! scope="row" | 2E
| 266
| 
| 533
| 1067
| 133.38
|-
! scope="row" | 3
| rowspan="2" |2012
|200
|
| rowspan="2" | 8''n''
|800
|1600
|200
| rowspan="2" | {{Unbulleted list center
  | 1.2
  | 1.8
  }}
|-
! scope="row" | 3E
| 266
|
|1067
|2133
|266.63
|-
! scope="row" | 4
|2014
|200
|
| rowspan="2" | 16''n''
|1600
|3200
|400
| {{Unbulleted list center
  | 1.1
  | 1.8
  }}
|-
! scope="row" | 4X
|2017
|266
|
|2133
|4267
|533.38
| {{Unbulleted list center
  | 0.6
  | 1.1
  | 1.8
  }}
|-
! scope="row" | 5
|2019
|400
|
| rowspan="2" | 16''n''
|3200
|6400
|800
| rowspan="2" |  {{Unbulleted list center
  | 0.5
  | 1.05
  | 1.8
  }}
|-
! scope="row" | 5X
|2021
|533
|
|4267
|8533
|1,066.63
|}

=== LPDDR(1) ===
The original low-power DDR (sometimes retroactively called '''LPDDR1'''), released in 2006 is a slightly modified form of [[DDR SDRAM]], with several changes to reduce overall power consumption.

Most significantly, the supply voltage is reduced from 2.5 to 1.8&nbsp;V. Additional savings come from temperature-compensated refresh (DRAM requires refresh less often at low temperatures), partial array self refresh, and a "deep power down" mode which sacrifices all memory contents. Additionally, chips are smaller, using less board space than their non-mobile equivalents. [[Samsung Electronics|Samsung]] and [[Micron Technology|Micron]] are two of the main providers of this technology, which is used in tablet and phone devices such as the [[iPhone 3GS]], [[iPad (1st generation)|original iPad]], [[Samsung Galaxy Tab 7.0]] and [[Motorola Droid X]].<ref>[http://www.anandtech.com/show/4062/samsung-galaxy-tab-the-anandtech-review Anandtech Samsung Galaxy Tab - The AnandTech Review], 23 December 2010</ref>

=== LPDDR2 ===
[[File:Motorola Xoom - Samsung K4P4G154EC-FGC1 on main board-0122.jpg|thumb|Samsung K4P4G154EC-FGC1 4&nbsp;Gbit LPDDR2 chip
]]
In 2009, the standards group [[JEDEC]] published JESD209-2, which defined a more dramatically revised low-power DDR interface.<ref name="lpddr2" /><ref>{{Cite news |title= JEDEC Announces Publication of LPDDR2 Standard for Low Power Memory Devices |work= Press release |date= 2 April 2009 |url= https://www.jedec.org/news/pressreleases/jedec-announces-publication-lpddr2-standard-low-power-memory-devices |access-date= 28 November 2021 }}</ref>
It is not compatible with either DDR1 or [[DDR2 SDRAM]], but can accommodate any one of:

* LPDDR2-S2: 2''n'' prefetch memory (like DDR1),
* LPDDR2-S4: 4''n'' prefetch memory (like DDR2), or
* LPDDR2-N: Non-volatile ([[NAND flash]]) memory.

Low-power states are similar to basic LPDDR, with some additional partial array refresh options.

Timing parameters are specified for LPDDR-200 to LPDDR-1066 (clock frequencies of 100 to 533&nbsp;MHz).

Working at 1.2&nbsp;V, LPDDR2 multiplexes the control and address lines onto a 10-bit [[double data rate]] CA bus. The commands are similar to [[SDRAM#SDRAM control signals|those of normal SDRAM]], except for the reassignment of the precharge and burst terminate opcodes:

{|class="wikitable" style="text-align:center; border-width:0px;"
|+ LPDDR2/LPDDR3 command encoding<ref name="lpddr2">{{Citation |url= http://www.jedec.org/sites/default/files/docs/JESD209-2B.pdf |title=JEDEC Standard: Low Power Double Data Rate 2 (LPDDR2) |date=February 2010 |access-date=2010-12-30 |publisher=JEDEC Solid State Technology Association}}</ref>
|-
! rowspan="2" | Operation
| rowspan="17" style="border-width:0px; background-color:white" | 
! colspan="10" style="line-height:110%" | <big>↗</big> Rising clock <big>↗</big>
! colspan="10" style="line-height:110%" | <big>↘</big> Falling clock <big>↘</big>
|- style="line-height:110%; vertical-align: top;"
! CA0<br/><small>({{overline|RAS}})</small> || CA1<br/><small>({{overline|CAS}})</small> || CA2<br/><small>({{overline|WE}})</small> || CA3 || CA4 || CA5 || CA6 || CA7 || CA8 || CA9
! CA0<br/><small>({{overline|RAS}})</small> || CA1<br/><small>({{overline|CAS}})</small> || CA2<br/><small>({{overline|WE}})</small> || CA3 || CA4 || CA5 || CA6 || CA7 || CA8 || CA9
|-
| No operation
| {{no|'''H'''}} || {{no|'''H'''}} || {{no|'''H'''}} ||colspan="17" bgcolor=lightgrey| — 
|-
| Precharge all banks
| {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{no|'''H'''}} ||colspan="15" bgcolor=lightgrey| — 
|-
| Precharge one bank
| {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}} ||colspan=2 bgcolor=lightgrey| — ||bgcolor=PaleTurquoise | BA0 ||bgcolor=PaleTurquoise | BA1 ||bgcolor=PaleTurquoise | BA2 
| colspan="10" bgcolor=lightgrey| —
|-
| Preactive (LPDDR2-N only)
| {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || A30 || A31 || A32 ||bgcolor=PaleTurquoise | BA0 ||bgcolor=PaleTurquoise | BA1 ||bgcolor=PaleTurquoise | BA2 
| A20 || A21 || A22 || A23 || A24 || A25 || A26 || A27 || A28 || A29
|-
| Burst terminate
| {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} ||colspan="16" bgcolor=lightgrey| — 
|-
| Read (AP=auto-precharge)
| {{no|'''H'''}} || {{yes|'''L'''}} || {{no|'''H'''}} ||colspan=2 bgcolor=lightgrey| ''reserved'' || C1 || C2 ||bgcolor=PaleTurquoise | BA0 ||bgcolor=PaleTurquoise | BA1 ||bgcolor=PaleTurquoise | BA2
| {{maybe|AP}} || C3 || C4 || C5 || C6 || C7 || C8 || C9 || C10 || C11
|-
| Write (AP=auto-precharge)
| {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} ||colspan=2 bgcolor=lightgrey| ''reserved'' || C1 || C2 ||bgcolor=PaleTurquoise | BA0 ||bgcolor=PaleTurquoise | BA1 ||bgcolor=PaleTurquoise | BA2 
| {{maybe|AP}} || C3 || C4 || C5 || C6 || C7 || C8 || C9 || C10 || C11
|-
| Activate (R0–14=Row address)
| {{yes|'''L'''}} || {{no|'''H'''}} || R8 || R9 || R10 || R11 || R12 ||bgcolor=PaleTurquoise | BA0 ||bgcolor=PaleTurquoise | BA1 ||bgcolor=PaleTurquoise | BA2 
| R0 || R1 || R2 || R3 || R4 || R5 || R6 || R7 || R13 || R14
|-
| Activate (LPDDR2-N only)
| {{yes|'''L'''}} || {{no|'''H'''}} || A15 || A16 || A17 || A18 || A19 ||bgcolor=PaleTurquoise | BA0 ||bgcolor=PaleTurquoise | BA1 ||bgcolor=PaleTurquoise | BA2 
| A5 || A6 || A7 || A8 || A9 || A10 || A11 || A12 || A13 || A14
|-
| Refresh all banks (LPDDR2-Sx only)
| {{yes|'''L'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{no|'''H'''}} ||colspan="16" bgcolor=lightgrey| — 
|-
| Refresh one bank (round-robin addressing)
| {{yes|'''L'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}} ||colspan="16" bgcolor=lightgrey| — 
|-
| Mode register read (MA0–7=address)
| {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || MA0 || MA1 || MA2 || MA3 || MA4 || MA5 
| MA6 || MA7 ||colspan="8" bgcolor=lightgrey| —
|-
| Mode register write (OP0–7=data)
| {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || MA0 || MA1 || MA2 || MA3 || MA4 || MA5
| MA6 || MA7 || OP0 || OP1 || OP2 || OP3 || OP4 || OP5 || OP6 || OP7
|}

Column address bit C0 is never transferred, and is assumed to be zero. Burst transfers thus always begin at even addresses.

LPDDR2 also has an active-low chip select (when high, everything is a NOP) and clock enable CKE signal, which operate like SDRAM. Also like SDRAM, the command sent on the cycle that CKE is first dropped selects the power-down state:

* If the chip is active, it freezes in place.
* If the command is a NOP ({{overline|CS}} low or CA0–2 = HHH), the chip idles.
* If the command is a refresh command (CA0–2 = LLH), the chip enters the self-refresh state.
* If the command is a burst terminate (CA0–2 = HHL), the chip enters the deep power-down state. (A full reset sequence is required when leaving.)

The mode registers have been greatly expanded compared to conventional SDRAM, with an 8-bit address space, and the ability to read them back. Although smaller than a [[serial presence detect]] EEPROM, enough information is included to eliminate the need for one.

S2 devices smaller than 4&nbsp;[[gigabit|Gbit]], and S4 devices smaller than 1&nbsp;Gbit have only four banks. They ignore the BA2 signal, and do not support per-bank refresh.

Non-volatile memory devices do not use the refresh commands, and reassign the precharge command to transfer address bits A20 and up. The low-order bits (A19 and down) are transferred by a following Activate command. This transfers the selected row from the memory array to one of 4 or 8 (selected by the BA bits) row data buffers, where they can be read by a Read command. Unlike DRAM, the bank address bits are not part of the memory address; any address can be transferred to any row data buffer. A row data buffer may be from 32 to 4096 bytes long, depending on the type of memory. Rows larger than 32 bytes ignore some of the low-order address bits in the Activate command. Rows smaller than 4096 bytes ignore some of the high-order address bits in the Read command.

Non-volatile memory does not support the Write command to row data buffers. Rather, a series of control registers in a special address region support Read and Write commands, which can be used to erase and program the memory array.

=== LPDDR3 ===
In May 2012, [[JEDEC]] published the JESD209-3 Low Power Memory Device Standard.<ref>[http://www.electroiq.com/articles/sst/2012/05/jedec-publishes-lpddr3-standard-for-low-power-memory-chips.html JEDEC publishes LPDDR3 standard for low-power memory chips] {{Webarchive|url=https://web.archive.org/web/20120520044744/http://www.electroiq.com/articles/sst/2012/05/jedec-publishes-lpddr3-standard-for-low-power-memory-chips.html |date=20 May 2012 }}, Solid State Technology magazine</ref><ref name="lpddr3">[http://www.jedec.org/sites/default/files/docs/JESD209-3.pdf JESD209-3 LPDDR3 Low Power Memory Device Standard], JEDEC Solid State Technology Association</ref><ref>{{cite web|url=http://www.jedec.org/news/pressreleases/jedec-announces-publication-lpddr3-standard-low-power-memory-devices|title=JEDEC Announces Publication of LPDDR3 Standard for Low Power Memory Devices|work=jedec.org|access-date=10 March 2015}}</ref> In comparison to LPDDR2, LPDDR3 offers a higher data rate, greater bandwidth and power efficiency, and higher memory density. LPDDR3 achieves a data rate of 1600&nbsp;MT/s and utilizes key new technologies: write-leveling and command/address training,<ref>[http://denalimemoryreport.com/2012/06/13/want-a-quick-and-dirty-overview-of-the-new-jedec-lpddr3-spec-eetimes-serves-it-up/ Want a quick and dirty overview of the new JEDEC LPDDR3 spec? EETimes serves it up] {{webarchive|url=https://web.archive.org/web/20130728110139/http://denalimemoryreport.com/2012/06/13/want-a-quick-and-dirty-overview-of-the-new-jedec-lpddr3-spec-eetimes-serves-it-up/ |date=2013-07-28 }}, Denali Memory Report</ref> optional on-die termination (ODT), and low-I/O capacitance. LPDDR3 supports both package-on-package (PoP) and discrete packaging types.

The command encoding is identical to LPDDR2, using a 10-bit double data rate CA bus.<ref name="lpddr3"/> However, the standard only specifies 8''n''-prefetch DRAM, and does not include the flash memory commands.

Products using LPDDR3 include the 2013 MacBook Air, [[iPhone 5S]], [[iPhone 6]], [[Nexus 10]], [[Samsung Galaxy S4]] (GT-I9500) and Microsoft [[Surface Pro 3]] and 4.<ref>[http://www.chipworks.com/blog/recentteardowns/2013/04/25/inside-the-samsung-galaxy-s4 Inside the Samsung Galaxy S4] {{webarchive|url=https://web.archive.org/web/20130429232326/http://www.chipworks.com/blog/recentteardowns/2013/04/25/inside-the-samsung-galaxy-s4/ |date=2013-04-29 }}, Chipworks</ref> LPDDR3 went mainstream in 2013, running at 800&nbsp;MHz DDR (1600&nbsp;MT/s), offering bandwidth comparable to PC3-12800 [[SODIMM|notebook memory]] in 2011 (12.8&nbsp;GB/s of bandwidth).<ref>[http://www.brightsideofnews.com/news/2012/6/27/samsung-lpddr3-high-performance-memory-enables-amazing-mobile-devices-in-20132c-2014.aspx Samsung LPDDR3 High-Performance Memory Enables Amazing Mobile Devices in 2013, 2014] - Bright Side of News</ref> To achieve this bandwidth, the controller must implement dual-channel memory. For example, this is the case for the Exynos 5 Dual<ref>{{cite web|url=http://www.samsung.com/global/business/semiconductor/minisite/Exynos/products5dual.html|title=Samsung Exynos|work=samsung.com|access-date=10 March 2015}}</ref> and the 5 Octa.<ref>[http://www.eetimes.com/document.asp?doc_id=1280297 Samsung reveals eight-core mobile processor] on EEtimes</ref>

==== LPDDR3E ====

An "enhanced" version of the specification called LPDDR3E increases the data rate to 2133&nbsp;MT/s. [[Samsung Electronics]] introduced the first 4&nbsp;[[gigabit]] 20&nbsp;nm-class LPDDR3 modules capable of transmitting data at up to 2,133&nbsp;MT/s, more than double the performance of the older LPDDR2 which is only capable of 800&nbsp;MT/s.<ref>[http://www.businesswire.com/news/home/20130429006782/en/Samsung-Producing-Gigabit-LPDDR3-Mobile-DRAM-20nm-classSamsung Now Producing Four Gigabit LPDDR3 Mobile DRAM, Using 20nm-class* Process Technology], Businesswire</ref> Various [[System On Chip|SoCs]] from various manufacturers also natively support 800&nbsp;MHz LPDDR3 RAM. Such include the [[Snapdragon (system on chip)|Snapdragon]] 600 and 800 from [[Qualcomm]]<ref>[http://www.qualcomm.com/media/blog/2013/01/07/snapdragon-800-series-and-600-processors-unveiled Snapdragon 800 Series and 600 Processors Unveiled ], Qualcomm</ref> as well as some SoCs from the [[Exynos (system on chip)|Exynos]] and [[Allwinner Technology|Allwinner]] series.

=== LPDDR4 ===
On 14 March 2012, JEDEC hosted a conference to explore how future mobile device requirements will drive upcoming standards like LPDDR4.<ref>{{cite web|url=http://www.jedec.org/news/pressreleases/jedec-focus-mobile-technology-upcoming-conference|title=JEDEC to Focus on Mobile Technology in Upcoming Conference|work=jedec.org|access-date=10 March 2015}}</ref> On 30 December 2013, Samsung announced that it had developed the first 20&nbsp;nm-class 8 gigabit (1&nbsp;GB) LPDDR4 capable of transmitting data at 3,200&nbsp;MT/s, thus providing 50 percent higher performance than the fastest LPDDR3 and consuming around 40 percent less energy at 1.1 volts.<ref>{{cite web|url=http://global.samsungtomorrow.com/?p=31752|title=Samsung Develops Industry's First 8Gb LPDDR4 Mobile DRAM|publisher=Samsung Electronics|type=Official Blog|work=Samsung Tomorrow|access-date=10 March 2015|archive-date=1 October 2014|archive-url=https://web.archive.org/web/20141001025158/http://global.samsungtomorrow.com/?p=31752|url-status=dead}}</ref><ref>http://www.softnology.biz/pdf/JESD79-4_DDR4_SDRAM.pdf JESD79 DDR4 SDRAM Standard</ref>

On 25 August 2014, [[JEDEC]] published the JESD209-4 LPDDR4 Low Power Memory Device Standard.<ref>[http://www.jedec.org/news/pressreleases/jedec-releases-lpddr4-standard-low-power-memory-devices  'JEDEC Releases LPDDR4 Standard for Low Power Memory Devices'], JEDEC Solid State Technology Association.</ref><ref name=lpddr4 />

Significant changes include:
* Doubling of the interface speed, and numerous consequent electrical changes, including changing the I/O standard to low-voltage swing-terminated logic (LVSTL)
* Doubling of the internal prefetch size, and minimum transfer size
* Change from a 10-bit DDR command/address bus to a 6-bit SDR bus
* Change from one 32-bit wide bus to two independent 16-bit wide buses
* Self-refresh is enabled by dedicated commands, rather than being controlled by the CKE line

The standard defines SDRAM packages containing two independent 16-bit access channels, each connected to up to two [[Die (integrated circuit)|dies]] per package. Each channel is 16 data bits wide, has its own control/address pins, and allows access to 8 banks of DRAM. Thus, the package may be connected in three ways:
* Data lines and control connected in parallel to a 16-bit data bus, and only chip selects connected independently per channel.
* To two halves of a 32-bit wide data bus, and the control lines in parallel, including chip select.
* To two independent 16-bit wide data buses

Each die provides 4, 6, 8, 12, or 16&nbsp;[[gigabit]]s of memory, half to each channel. Thus, each bank is one sixteenth the device size. This is organized into the appropriate number (16&nbsp;[[kilobit|K]] to 64&nbsp;K) of 16384-bit (2048-byte) rows. Extension to 24 and 32&nbsp;gigabits is planned, but it is not yet decided if this will be done by increasing the number of rows, their width, or the number of banks.

Larger packages providing double width (four channels) and up to four dies per pair of channels (8 dies total per package) are also defined.

Data is accessed in bursts of either 16 or 32 transfers (256 or 512 bits, 32 or 64 bytes, 8 or 16 cycles DDR). Bursts must begin on 64-bit boundaries.

Since the clock frequency is higher and the minimum burst length longer than earlier standards, control signals can be more highly multiplexed without the command/address bus becoming a bottleneck. LPDDR4 multiplexes the control and address lines onto a 6-bit single data rate CA bus. Commands require 2 clock cycles, and operations encoding an address (e.g., activate row, read or write column) require two commands. For example, to request a read from an idle chip requires four commands taking 8 clock cycles: Activate-1, Activate-2, Read, CAS-2.

The chip select line (CS) is active-''high''. The first cycle of a command is identified by chip select being high; it is low during the second cycle.

{|class="wikitable" style="text-align:center; border-width:0px;"
|+ LPDDR4 command encoding<ref name="lpddr4">{{Citation |url=http://www.jedec.org/sites/default/files/docs/JESD209-4.pdf |title=JEDEC Standard: Low Power Double Data Rate 4 (LPDDR4) |date=August 2014 |access-date=25 December 2014 |publisher=JEDEC Solid State Technology Association}} Username and password "cypherpunks" will allow download.</ref>{{Rp|151}}
|-
! colspan="6" | First cycle (CS high)
| rowspan="20" style="border-width:0px; background-color:#FFF;" |
! colspan="6" | Second cycle (CS low)
| rowspan="20" style="border-width:0px; background-color:#FFF;" |
! rowspan="2" | Operation
|-
! CA5 || CA4 || CA3 || CA2 || CA1 || CA0
! CA5 || CA4 || CA3 || CA2 || CA1 || CA0
|-
| {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
|colspan=6 bgcolor=lightgrey| — ||align=left| No operation
|-
| {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
| 0 || OP4 || OP3 || OP2 || OP1 || 1 ||align=left| Multi-purpose command
|-
|bgcolor=paleturquoise| AB || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
|colspan=3 bgcolor=lightgrey| — ||bgcolor=paleturquoise| BA2 ||bgcolor=paleturquoise| BA1 ||bgcolor=paleturquoise| BA0 ||align=left| Precharge (AB: all banks)
|-
|bgcolor=paleturquoise| AB || {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
|colspan=3 bgcolor=lightgrey| — ||bgcolor=paleturquoise| BA2 ||bgcolor=paleturquoise| BA1 ||bgcolor=paleturquoise| BA0 ||align=left| Refresh (AB: all banks)
|-
|bgcolor=lightgrey| — || {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
|colspan=6 bgcolor=lightgrey| — ||align=left| Self-refresh entry
|-
|bgcolor=plum| BL || {{yes|'''L'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
| {{maybe|AP}} || C9 ||bgcolor=lightgrey| — ||bgcolor=paleturquoise| BA2 ||bgcolor=paleturquoise| BA1 ||bgcolor=paleturquoise| BA0 ||align=left| Write-1 (+CAS-2)
|-
|bgcolor=lightgrey| — || {{no|'''H'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
|colspan=6 bgcolor=lightgrey| — ||align=left| Self-refresh exit
|-
|bgcolor=plum| 0 || {{yes|'''L'''}} || {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
| {{maybe|AP}} || C9 ||bgcolor=lightgrey| — ||bgcolor=paleturquoise| BA2 ||bgcolor=paleturquoise| BA1 ||bgcolor=paleturquoise| BA0 ||align=left| Masked write-1 (+CAS-2)
|-
|bgcolor=lightgrey| — || {{no|'''H'''}} || {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
|colspan=6 bgcolor=lightgrey| — || {{n/a|Reserved}}
|-
|bgcolor=plum| BL || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}}
| {{maybe|AP}} || C9 ||bgcolor=lightgrey| — ||bgcolor=paleturquoise| BA2 ||bgcolor=paleturquoise| BA1 ||bgcolor=paleturquoise| BA0 ||align=left| Read-1 (+CAS-2)
|-
| C8 || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}}
| C7 || C6 || C5 || C4 || C3 || C2 ||align=left| CAS-2
|-
|colspan=2 bgcolor=lightgrey| — || {{no|'''H'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}}
|colspan=6 bgcolor=lightgrey| — || {{n/a|Reserved}}
|-
| OP7 || {{yes|'''L'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}}
| MA5 || MA4 || MA3 || MA2 || MA1 || MA0 ||rowspan=2 align=left| Mode register write-1 and -2<br/>MA: address, OP: data
|-
| OP6 || {{no|'''H'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}}
| OP5 || OP4 || OP3 || OP2 || OP1 || OP0
|-
|bgcolor=lightgrey| — || {{yes|'''L'''}} || {{no|'''H'''}} || {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}}
| MA5 || MA4 || MA3 || MA2 || MA1 || MA0 ||align=left| Mode register read (+CAS-2)
|-
|bgcolor=lightgrey| — || {{no|'''H'''}} || {{no|'''H'''}} || {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}}
|colspan=6 bgcolor=lightgrey| — || {{n/a|Reserved}}
|--
| R15 || R14 || R13 || R12 || {{yes|'''L'''}} || {{no|'''H'''}}
| R11 || R10 || R16 ||bgcolor=paleturquoise| BA2 ||bgcolor=paleturquoise| BA1 ||bgcolor=paleturquoise| BA0 ||rowspan=2 align=left| Activate-1 and -2
|-
| R9 || R8 || R7 || R6 || {{no|'''H'''}} || {{no|'''H'''}}
| R5 || R4 || R3 || R2 || R1 || R0
|}

The CAS-2 command is used as the second half of all commands that perform a transfer across the data bus, and provides low-order column address bits:

* Read commands must begin on a column address which is a multiple of 4; there is no provision for communicating a non-zero C0 or C1 address bit to the memory.
* Write commands must begin on a column address which is a multiple of 16; C2 and C3 must be zero for a write command.
* Mode register read and some multi-purpose commands must also be followed by a CAS-2 command, however all the column bits must be zero (low).

The burst length can be configured to be 16, 32, or dynamically selectable by the BL bit of read and write operations.

One DMI (data mask/invert) signal is associated with each 8 data lines, and can be used to minimize the number of bits driven high during data transfers. When high, the other 8 bits are complemented by both transmitter and receiver. If a byte contains five or more 1 bits, the DMI signal can be driven high, along with three or fewer data lines. As signal lines are terminated low, this reduces power consumption.

(An alternative usage, where DMI is used to limit the number of data lines which ''toggle'' on each transfer to at most 4, minimises crosstalk. This may be used by the memory controller during writes, but is not supported by the memory devices.)

Data bus inversion can be separately enabled for reads and writes. For masked writes (which have a separate command code), the operation of the DMI signal depends on whether write inversion is enabled.

* If DBI on writes is disabled, a high level on DMI indicates that the corresponding data byte is to be ignored and not written
* If DBI on writes is enabled, a ''low'' level on DMI, combined with a data byte with 5 or more bits set, indicates a data byte to be ignored and not written.

LPDDR4 also includes a mechanism for "targeted row refresh" to avoid corruption due to "[[row hammer]]" on adjacent rows. A special sequence of three activate/precharge sequences specifies the row which was activated more often than a device-specified threshold (200,000 to 700,000 per refresh cycle). Internally, the device refreshes [[Physically based rendering|physically]] adjacent rows rather than the one specified in the activate command.<ref>{{cite web |url=https://patents.google.com/patent/US20140059287| id = US20140059287 | title = Row hammer refresh command |work= Patents |access-date=10 March 2015}}</ref><ref name= lpddr4 />{{Rp |153–54}}

==== LPDDR4X ====
[[Samsung Electronics|Samsung Semiconductor]] proposed an LPDDR4 variant that it called LPDDR4X.<ref>{{Cite conference |url=https://3gltesummit.qualcomm.com/sites/default/files/pdf/3GLTE2015_Samsung-AReza_Memory2.pdf |title= "Memory Need" Gives Birth To "New Memory" |date=16 September 2016 |first=Ashiq |last=Reza |conference=Qualcomm 3G LTE Summit |location=Hong Kong}}</ref>{{Rp|11}} LPDDR4X is identical to LPDDR4 except additional power is saved by reducing the I/O voltage (Vddq) from 1.1&nbsp;V to 0.6&nbsp;V. On 9 January 2017, SK Hynix announced 8 and 16&nbsp;GB LPDDR4X packages.<ref>{{Cite news |url=http://www.anandtech.com/show/11021/sk-hynix-announces-8-gb-lpddr4x4266-dram-packages|title= SK Hynix Announces 8 GB LPDDR4X-4266 DRAM Packages|last=Shilov |first= Anton |access-date= 2017-07-28}}</ref><ref>{{Cite web|url= http://blog.skhynix.com/2006|title= SK하이닉스 세계 최대 용량의 초저전력 모바일 D램 출시|website= Skhynix|language= ko|access-date= 2017-07-28|archive-date= 13 January 2019|archive-url= https://web.archive.org/web/20190113060939/http://blog.skhynix.com/2006|url-status= dead}}</ref> JEDEC published the LPDDR4X standard on 8 March 2017.<ref>{{Cite web |url=https://www.jedec.org/news/pressreleases/jedec-updates-standards-low-power-memory-devices-0|title= JEDEC Updates Standards for Low Power Memory Devices |website= JEDEC |access-date=28 July 2017}}</ref> Aside from the lower voltage, additional improvements include a single-channel die option for smaller applications, new MCP, PoP and IoT packages, and additional definition and timing improvements for the highest 4266 MT/s speed grade.

=== LPDDR5 ===
On 19 February 2019, [[JEDEC]] published the JESD209-5, Standard for Low Power Double Data Rate 5 (LPDDR5).<ref name=lpddr5>{{cite web|url=https://www.jedec.org/news/pressreleases/jedec-updates-standard-low-power-memory-devices-lpddr5|title=JEDEC Updates Standard for Low Power Memory Devices: LPDDR5|work=jedec.org|access-date=19 February 2019}}</ref>

[[Samsung]] announced it had working prototype LPDDR5 chips in July 2018. LPDDR5 introduces the following changes:<ref>{{cite news |title=Samsung Announces First LPDDR5 DRAM Chip, Targets 6.4Gbps Data Rates & 30% Reduced Power |first=Ryan |last=Smith |date=16 July 2018 |journal=[[AnandTech]] |url=https://www.anandtech.com/show/13084/samsung-announces-first-lpddr5-64gbps-data-rates}}</ref>
* Data transfer rate is increased to 6400&nbsp;Mbit/s per pin
* [[Differential signalling|Differential]] clocks are used (3200&nbsp;MHz, DDR)
* Prefetch is ''not'' doubled again, but remains 16''n''
* The number of banks is increased to 16, divided into four [[DDR4]]-like bank groups
* Power-saving improvements:<ref name=lpddr5/>
** Data-Copy and Write-X (all one or all zero) commands to decrease data transfer
** Dynamic frequency and voltage scaling
* A new clocking architecture, where commands use a quarter-speed master clock (CK), while data is transferred using full-speed Write Clock (WCK) & Read Strobe (RDQS) signals which are enabled only when necessary<ref name=lpddr5/>
* One set of full-speed clocks per byte (vs. per 16 bits in LPDDR4)
* Elimination of the Clock Enable (CKE) pin; instead low-power mode is entered by a command over the CA bus, and lasts until the [[chip select]] signal next goes high

AMD Van Gogh, Intel [[Tiger Lake (microprocessor)|Tiger Lake]], [[Apple silicon]] (M1 Pro, M1 Max, M1 Ultra, M2 and A16 Bionic), [[HiSilicon#Kirin 9000 5G/4G & Kirin 9000E|Huawei Kirin 9000]] and [[List of Qualcomm Snapdragon processors#Snapdragon 888/888+ 5G (2021)|Snapdragon 888]] memory controllers support LPDDR5.

The doubling of the transfer rate, and the quarter-speed master clock, results in a master clock which is half the frequency of a similar LPDDR4 clock. The command (CA) bus is widened to 7 bits, and commands are transferred at double data rate, so commands end up being sent at the same rate as LPDDR4.

{|class="wikitable" style="text-align:center; border-width:0px;"
|+ LPDDR5 command encoding<ref>{{Citation |url=https://zhuanlan.zhihu.com/p/578803845 |title=LPDDR5/5X 协议解读（三）WCK operation |date=2022-12-19  |access-date=2023-11-04 |website=[[Zhihu]] |language=zh, en}}</ref><ref>{{Citation |contribution-url=https://picture.iczhiku.com/resource/eetop/sHKLhyJrzATLaBmm.pdf |title=LPDDR5 Workshop |contribution=Commands & New Features |first=Alex (Yeongkee) |last=Chang |date=October 2019 |access-date=2023-11-04}}</ref>
|-
! colspan=7 | ↗ Rising clock ↗
| rowspan=24 style="border-width:0px; background-color:#FFF;" |
! colspan=7 |  	↘ Falling clock ↘
| rowspan=24 style="border-width:0px; background-color:#FFF;" |
! rowspan=2 | Operation
|-
! CA6 || CA5 || CA4 || CA3 || CA2 || CA1 || CA0
! CA6 || CA5 || CA4 || CA3 || CA2 || CA1 || CA0
|-
| {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
|colspan=7 bgcolor=lightgrey| —
|align=left| No operation
|-
| {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
|colspan=7 bgcolor=lightgrey| —
|align=left| Power-down entry
|-
| {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
|colspan=7 {{yes|'''— L —'''}}
|align=left| Read [[FIFO (computing and electronics)|FIFO]]
|-
| {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
|colspan=7 {{yes|'''— L —'''}}
|align=left| Write FIFO
|-
| {{yes|'''L'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
|colspan=7 bgcolor=lightgrey| —
|align=left {{n/a|Reserved}}
|-
| {{no|'''H'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
|colspan=7 {{yes|'''— L —'''}}
|align=left| Read DQ Calibration
|-
| OP7 || {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
| OP6 || OP5 || OP4 || OP3 || OP2 || OP1 || OP0
|align=left| Multi-purpose command
|-
| OP7 || {{yes|'''L'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
| OP6 || OP5 || OP4 || OP3 || OP2 || OP1 || OP0
|align=left| Mode register write 2
|-
| {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
|colspan=7 bgcolor=lightgrey| — ||align=left| Self-refresh exit
|-
| {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
| PD || DSE ||colspan=5 bgcolor=lightgrey| — ||align=left| Self-refresh entry
|-
| {{yes|'''L'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
| MA6 || MA5 || MA4 || MA3 || MA2 || MA1 || MA0
|align=left| Mode register read
|-
| {{no|'''H'''}} || {{yes|'''L'''}} || {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
| MA6 || MA5 || MA4 || MA3 || MA2 || MA1 || MA0
|align=left| Mode register write 1
|-
| {{yes|'''L'''}} || {{no|'''H'''}} || {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
|bgcolor=paleturquoise| AB || SB1 || SB0 || RFM ||bgcolor=paleturquoise| BG0 ||bgcolor=paleturquoise| BA1 ||bgcolor=paleturquoise| BA0
|align=left| Refresh
|-
| {{no|'''H'''}} || {{no|'''H'''}} || {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
|bgcolor=paleturquoise| AB ||colspan=2 bgcolor=lightgrey| — ||bgcolor=paleturquoise| BG1 ||bgcolor=paleturquoise| BG0 ||bgcolor=paleturquoise| BA1 ||bgcolor=paleturquoise| BA0
|align=left| Precharge
|-
| C5 || C4 || C3 || {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
| {{maybe|AP}} || C2 || C1  ||bgcolor=paleturquoise| BG1 ||bgcolor=paleturquoise| BG0 ||bgcolor=paleturquoise| BA1 ||bgcolor=paleturquoise| BA0
|align=left| Write 32
|- {{^|CAS uses double-height cells, to avoid making some columns awkwardly wide}}
| WS_<br/>FS || WS_<br/>RD || WS_<br/>WR || {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}} || {{yes|'''L'''}}
| {{small|WXSB}}<br/>/B3 || {{small|WXSA}} || WRX || DC3 || DC2 || DC1 || DC0
|align=left| Column address select
|-
| C5 || C4 || C3 || C0 || {{yes|'''L'''}} || {{no|'''H'''}} || {{yes|'''L'''}}
| {{maybe|AP}} || C2 || C1  ||bgcolor=paleturquoise| BG1 ||bgcolor=paleturquoise| BG0 ||bgcolor=paleturquoise| BA1 ||bgcolor=paleturquoise| BA0
|align=left| Masked Write
|-
| C5 || C4 || C3 || C0 || {{no|'''H'''}} || {{no|'''H'''}} || {{yes|'''L'''}}
| {{maybe|AP}} || C2 || C1  ||bgcolor=paleturquoise| BG1 ||bgcolor=paleturquoise| BG0 ||bgcolor=paleturquoise| BA1 ||bgcolor=paleturquoise| BA0
|align=left| Write
|-
| C5 || C4 || C3 || C0 || {{yes|'''L'''}} || {{yes|'''L'''}} || {{no|'''H'''}}
| {{maybe|AP}} || C2 || C1  ||bgcolor=paleturquoise| BG1 ||bgcolor=paleturquoise| BG0 ||bgcolor=paleturquoise| BA1 ||bgcolor=paleturquoise| BA0
|align=left| Read
|-
| C5 || C4 || C3 || C0 || {{no|'''H'''}} || {{yes|'''L'''}} || {{no|'''H'''}}
| {{maybe|AP}} || C2 || C1  ||bgcolor=paleturquoise| BG1 ||bgcolor=paleturquoise| BG0 ||bgcolor=paleturquoise| BA1 ||bgcolor=paleturquoise| BA0
|align=left| Read 32
|-
| R10 || R9 || R8 || R7 || {{yes|'''L'''}} || {{no|'''H'''}} || {{no|'''H'''}}
| R6 || R5 || R4 || R3 || R2 || R1 || R0
|align=left| Activate 2
|-
| R17 || R16 || R15 || R14 || {{no|'''H'''}} || {{no|'''H'''}} || {{no|'''H'''}}
| R13 || R12 || R11  ||bgcolor=paleturquoise| BG1 ||bgcolor=paleturquoise| BG0 ||bgcolor=paleturquoise| BA1 ||bgcolor=paleturquoise| BA0
|align=left| Activate 1
|}
{{col-begin}}
{{col-break|width=35%}}
* B''n'' = Burst address bit
* C''n'' = Column address bit
* R''n'' = Column address bit
* BA''n'' = Bank address bit
* BG''n'' = Bank group address bit
* AB = All banks (ignore BG & BA)
* AP = Auto-precharge
{{col-break|width=65%}}
* MA''n'' = Mode register address bit
* OP''n'' = Operation, or mode register data
* WS_''xx'' = WCK synchronization
* WRX = Write X; do not transfer data, but fill with all-zero or all-one
* WXSA, WXSB = Write X select, value to be written
* PD = Power down
* DSE = Deep sleep enable
{{col-end}}
<!-- DC = ???  SB=???  RFM=???-->

Compared to earlier standards, the nomenclature for column addresses has changed. Both LPDDR4 and LPDDR5 allow up to 10 bits of column address, but the names are different. LPDDR4's C0–C9 are renamed B0–B3 and C0–C5. As with LPDDR4, writes must start at a multiple-of-16 address with B0–B3 zero, but reads may request a burst be transferred in a different order by specifying a non-zero value for B3.

As with LPDDR4, to read some data requires 4 commands: two activate commands to select a row, then a CAS and a read command to select a column. Unlike LPDDR4, the CAS command comes ''before'' the read or write command. In fact, it is something of a misnomer, in that it does not select a column at all. Instead, its primary function is to prepare the DRAM to synchronize with the imminent start of the high-speed WCK clock. The WS_FS, WS_RD and WS_WR bits select various timings, with the _RD and _WR options optimized for an immediately following read or write command, while the _FS option starts the clock immediately, and may be followed by multiple reads or writes, accessing multiple banks.

CAS also specifies the "write X" option. If the WRX bit is set, writes do not transfer data, but rather fill the burst with all-zeros or all-ones, under the control of the WXS (write-X select) bit. This takes the same amount of time, but saves energy.

In addition to the usual bursts of 16, there are commands for performing double-length bursts of 32. Reads (but not writes) may specify a starting position within the 32-word aligned burst using the C0 and B3 bits.

==== LPDDR5X ====
On 28 July 2021, JEDEC published the JESD209-5B, Standard for Low Power Double Data Rate 5/5X (LPDDR5/5X)<ref name=lpddr5X>{{cite web|url=https://www.jedec.org/news/pressreleases/jedec-publishes-new-and-updated-standards-low-power-memory-devices-used-5g-and-ai|title=JEDEC Publishes New and Updated Standards for Low Power Memory Devices Used in 5G and AI Applications|work=jedec.org|access-date=28 July 2021}}</ref> with the following changes:
* Speed extension up to 8533&nbsp;Mbit/s
* Signal integrity improvements with tx/rx equalization
* Reliability improvements via the new Adaptive Refresh Management feature

On 9 November 2021, Samsung announced that the company has developed the industry's first LPDDR5X DRAM. Samsung's implementation involves 16-gigabit (2&nbsp;GB) dies, on a [[14 nm process]] node, with modules with up to 32 dies (64&nbsp;GB) in a single package. According to the company, the new modules would use 20% less power than LPDDR5.<ref>{{Cite web|title=Samsung Develops Industry's First LPDDR5X DRAM|date=2021-11-09|url=https://news.samsung.com/global/samsung-develops-industrys-first-lpddr5x-dram|access-date=2021-11-09|website=[[Samsung]].com|language=en}}</ref> According to Andrei Frumusanu of ''[[AnandTech]]'', LPDDR5X in [[System on a chip|SoC]]s and other products was expected for the 2023 generation of devices.<ref>{{Cite web|last=Frumusanu|first=Andrei|title=Samsung Announces First LPDDR5X at 8.5Gbps|url=https://www.anandtech.com/show/17058/samsung-announces-lpddr5x-at-85gbps|date=2021-11-09|access-date=2021-11-09|website=[[Anandtech]].com}}</ref>

On 19 November 2021, Micron announced that Mediatek has validated its LPDDR5X DRAM for Mediatek's Dimensity 9000 5G SoC.<ref>{{Cite web|url=https://investors.micron.com/news-releases/news-release-details/micron-and-mediatek-first-validate-lpddr5x|title = Micron and MediaTek First to Validate LPDDR5X|publisher=Micron Technology}}</ref>

On 25 January 2023 [[SK Hynix]] announced "Low Power Double Data Rate 5 Turbo" (LPDDR5T) chips with a bandwidth of 9.6&nbsp;Gbit/s.<ref>{{cite web |title=SK hynix Develops World's Fastest Mobile DRAM LPDDR5T |url=https://news.skhynix.com/sk-hynix-develops-worlds-fastest-mobile-dram-lpddr5t/ |access-date=12 June 2023 |date=24 January 2023}}</ref> It operates in the ultra-low voltage range of {{val|1.01|-|1.12|u=V}} set by [[JEDEC]]. It has been incorporated into the LPDDR5X standard as LPDDR5X-9600 making "LPDDR5T" a brand name.<ref>{{cite web |last1=Hung |first1=Vuong |title=Jedec Memory for Automotive LPDDRx & UFS |url=https://www.jedec.org/sites/default/files/FINAL_Hung_Vuong_Automotive_forum-memory%20technologies.pdf |website=jedec.org |access-date=18 April 2024 |page=4}}</ref><br>MediaTek Dimensity 9300 and Qualcomm Snapdragon 8 Gen 3 supports LPDDR5T.

On 17 April 2024 [[Samsung Electronics]] announced LPDDR5X-10700 with 25% higher bandwidth, 30% higher capacity and 25% improved power efficiency than previous LPDDR5X generations. This is achieved through a new [[14 nm process|12 nm process]] that allows the chips to be more efficient while also being small enough to fit capacities of up to 32&nbsp;GB in a single package.<ref>{{cite web |title=Samsung Develops Industry's Fastest 10.7Gbps LPDDR5X DRAM, Optimized for AI Applications |url=https://news.samsung.com/global/samsung-develops-industrys-fastest-10-7gbps-lpddr5x-dram-optimized-for-ai-applications |website=Samsung Newsroom |access-date=18 April 2024 |date=17 April 2024}}</ref>

On 16 July 2024 Samsung has completed validation of the industry's fastest LPDDR5X DRAM, capable of operating at speeds up to 10.7&nbsp;Gbit/s, for use in MediaTek's upcoming flagship Dimensity 9400 SoC.<ref name=":0" />

=== LPDDR6 ===
The following standard is under development.<ref>{{cite news
 |title=LPDDR6 LPCAMM2 Pictured and Detailed Courtesy of JEDEC
 |author=TheLostSwede
 |date=23 May 2024
 |journal=TechPowerUp.com
 |url=https://www.techpowerup.com/322754/lpddr6-lpcamm2-pictured-and-detailed-courtesy-of-jedec
}}</ref><ref>{{cite news
 |title=JEDEC Reveals Massive Speed Boosts For Next-Gen DDR6 And LPDDR6 Memory
 |first=Zak |last=Killian
 |date=22 May 2024
 |journal=HotHardware.com
 |url=https://hothardware.com/news/jedec-ddr6-lpddr6-revealed
}}</ref><ref>{{cite news
 |title=Leak suggests that DDR6 development has already started, aiming for 21 GT/s
 |first=Anton |last=Shilov
 |date=23 May 2024
 |journal=TomsHardware.com
 |url=https://www.tomshardware.com/pc-components/dram/leak-suggests-that-ddr6-development-has-already-started-aiming-for-21-gts
}}</ref>
Planned extensions include:
* Speed extension to 8.8–17.6 Gbit/s/pin
* CA bus further narrowed to 4 bits
* Data bus width of 12 bits per channel
* Bursts of 24 transfers × 12 pins = 288 bits:
** 256 data bits, plus
** 16 tag/ECC bits stored by array, plus
** 16 bits for data bus inversion ''or'' link ECC, not stored.
* [[CAMM2]]<ref>{{cite press release
 |title=JEDEC Unveils Plans for DDR5 MRDIMM and LPDDR6 CAMM Standards to Propel High-Performance Computing and AI
 |date=22 July 2024
 |publisher=[[JEDEC]]
 |url=https://www.jedec.org/news/pressreleases/jedec-unveils-plans-ddr5-mrdimm-and-lpddr6-camm-standards-propel-high-performance
}}</ref>

== Notes ==
{{notelist}}

==References==
{{Reflist}}

==External links==
* [https://www.micron.com/products/memory/dram-components/lpddr Micron]
* [https://semiconductor.samsung.com/dram/lpddr/ Samsung]
* [https://web.archive.org/web/20110829044651/http://www.elpida.com/en/products/mobile.html Elpida]
* [http://www.nanya.com/PageEdition1.aspx?Menu_ID=138&lan=en-us&def=230&isPrint=&KeyWords= Nanya] {{Webarchive|url=https://web.archive.org/web/20141021194351/http://www.nanya.com/PageEdition1.aspx?Menu_ID=138&lan=en-us&def=230&isPrint=&KeyWords= |date=21 October 2014 }}
* JEDEC pages: [http://www.jedec.org/standards-documents/docs/jesd209-3c LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3)]

{{DRAM}}
{{Use dmy dates|date=February 2020}}

[[Category:SDRAM]]