View source for EEPROM

{{short description|Computer memory used for small quantities of data}}
{{Distinguish|EPROM}}
{{Memory types}}
[[File:Floating gate transistor-en.svg|thumb|A cross section of legacy [[EPROM]]&nbsp;structure.<br />Upper insulator: {{abbr|ONO|Oxide–nitride–oxide}}<br />Lower&nbsp;insulator:&nbsp;[[Quantum tunnelling|tunnel]]&nbsp;[[Silicon dioxide|oxide]]]]
[[File:AT24C02 EEPROM 1480355 6 7 HDR Enhancer.jpg|thumbnail|[[STMicroelectronics|STMicro]] [http://www.st.com/resource/en/datasheet/m24c02-f.pdf M24C02] [[I²C]] serial type EEPROM]]
[[File:ATMEL048 93C46A SC.jpg|thumbnail|[[Atmel]] [http://ww1.microchip.com/downloads/en/devicedoc/doc0539.pdf AT93C46A] [[Die (integrated circuit)|die]]]]
[[File:Atmel-avr-atusb162-HD.jpg|thumbnail| [http://ww1.microchip.com/downloads/en/DeviceDoc/7707S.pdf AT90USB162] [[microcontroller|MCU]] integrates 512 Byte EEPROM]]

'''EEPROM''' or '''E<sup>2</sup>PROM''' ('''electrically erasable programmable read-only memory''') is a type of [[non-volatile memory]]. It is used in computers, usually integrated in [[microcontrollers]] such as [[smart card]]s and [[remote keyless system]]s, or as a separate chip device, to store relatively small amounts of data by allowing individual bytes to be erased and reprogrammed.

EEPROMs are organized as arrays of [[floating-gate transistor]]s. EEPROMs can be programmed and erased in-circuit, by applying special programming signals. Originally, EEPROMs were limited to single-byte operations, which made them slower, but modern EEPROMs allow multi-byte page operations. An EEPROM has a limited life for erasing and reprogramming, reaching a million operations in modern EEPROMs. In an EEPROM that is frequently reprogrammed, the life of the EEPROM is an important design consideration.

[[Flash memory]] is a type of EEPROM designed for high speed and high density, at the expense of large erase blocks (typically 512&nbsp;bytes or larger) and limited number of write cycles (often 10,000). There is no clear boundary dividing the two, but the term "EEPROM" is generally used to describe non-volatile memory with small erase blocks (as small as one byte) and a long lifetime (typically 1,000,000 cycles). Many past [[microcontrollers]] included both (flash memory for the [[firmware]] and a small EEPROM for parameters), though the trend with modern microcontrollers is to [[Emulation (computing)|emulate]] EEPROM using flash.

As of 2020, flash memory costs much less than byte-programmable EEPROM and is the dominant memory type wherever a system requires a significant amount of non-volatile [[solid-state storage]]. EEPROMs, however, are still used on applications that only require small amounts of storage, like in [[serial presence detect]].<ref>{{cite web |url=https://www.micron.com/-/media/client/global/documents/products/technical-note/dram-modules/tn_04_42.pdf?rev=e5a1537ce3214de5b695f17c340fd023 |title=TN-04-42: Memory Module Serial Presence-Detect |publisher=Micron Technology |date=2002 |access-date=2020-10-11 |archive-date=2022-07-26 |archive-url=https://web.archive.org/web/20220726125258/https://www.micron.com/-/media/client/global/documents/products/technical-note/dram-modules/tn_04_42.pdf |url-status=dead }}</ref><ref>{{cite web |url=https://whatis.techtarget.com/definition/serial-presence-detect-SPD#:~:text=When%20a%20computer%20is%20booted,%2C%20data%20width%2C%20speed%2C%20and |title=serial presence detect (SPD) |website=TechTarget |date=July 2015}}</ref>

==History==
[[File:Flash-Programming.svg|thumb|[[Electric charge|Charging]] mechanism of today's [[NOR gate|NOR-type]] [[Flash memory|FLASH]] [[Memory cell (computing)|memory cell]]. [[Angstrom|Å]] = 10{{Sup|-10}} [[Metre|m]].]]
[[File:Flash erase.svg|thumb|[[Electric discharge|Discharging]] mechanism of today's [[NOR gate|NOR-type]] [[Flash memory|FLASH]] [[Memory cell (computing)|memory cell]]]]

=== Early attempts ===
In the early 1970s, some studies, [[inventions]], and development for electrically re-programmable [[non-volatile memory|non-volatile memories]] were performed by various companies and organizations.

In 1971, early research was presented at ''the 3rd Conference on [[Solid-state electronics|Solid State Devices]], [[Tokyo]]'' in Japan by Yasuo Tarui, Yutaka Hayashi, and Kiyoko Nagai at ''[[Electrotechnical Laboratory]]''; a Japanese national research institute.<ref>
{{cite journal|last1=Tarui|first1=Yasuo|last2=Hayashi|first2=Yutaka|last3=Nagai|first3=Kiyoko|title=Proposal of electrically reprogrammable non-volatile semiconductor memory|journal=Proceedings of the 3rd Conference on Solid State Devices, Tokyo|date=1971-09-01|pages=155{{endash}}162|publisher=The Japan Society of Applied Physics}}
</ref>
They [[Semiconductor device fabrication|fabricated]] an electrically re-programmable non-volatile memory in 1972,<ref name=":0">
{{cite journal|last1=Tarui|first1=Y.|last2=Hayashi|first2=Y.|last3=Nagai|first3=K.|title=Electrically reprogrammable nonvolatile semiconductor memory|journal=IEEE Journal of Solid-State Circuits|date=1972|volume=7|issue=5|pages=369–375|doi=10.1109/JSSC.1972.1052895|issn=0018-9200|bibcode=1972IJSSC...7..369T}}
</ref><ref name="Iizuka-1976">
{{cite journal|last1=Iizuka|first1=H.|last2=Masuoka|first2=F.|last3=Sato|first3=Tai|last4=Ishikawa|first4=M.|title=Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure|journal=IEEE Transactions on Electron Devices|date=1976|volume=23|issue=4|pages=379–387|doi=10.1109/T-ED.1976.18415|issn=0018-9383|bibcode=1976ITED...23..379I|s2cid=30491074}}
</ref><ref>
{{cite journal|last1=Rossler|first1=B.|title=Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell|journal=IEEE Transactions on Electron Devices|date=1977|volume=24|issue=5|pages=606–610|doi=10.1109/T-ED.1977.18788|issn=0018-9383|bibcode=1977ITED...24..606R|s2cid=33203267}}
</ref> and continued this study for more than 10 years.<ref>
{{cite journal|last1=Tarui|first1=Yasuo|last2=Nagai|first2=Kiyoko|last3=Hayashi|first3=Yutaka|title=Nonvolatile Semiconductor Memory|journal=Oyo Buturi|date=1974-07-19|volume=43|issue=10|pages=990{{endash}}1002|doi=10.11470/oubutsu1932.43.990|url=https://www.jstage.jst.go.jp/article/oubutsu1932/43/10/43_10_990/_pdf/-char/en.pdf|issn=2188-2290|url-status=live|archive-url=https://web.archive.org/web/20180312205219/https://www.jstage.jst.go.jp/article/oubutsu1932/43/10/43_10_990/_pdf/-char/en.pdf|archive-date=2018-03-12}}
</ref> However this early memory depended on capacitors to work,<ref name=":0" /> which modern EEPROM lacks.

In 1972 IBM patented an electrically re-programmable non-volatile memory invention.<ref>{{Cite patent|number=US3865652A|title=Method of forming self-aligned field effect transistor and charge-coupled device|gdate=1975-02-11|invent1=Agusta|invent2=Chang|invent3=Joshi|inventor1-first=Benjamin|inventor2-first=Joseph J.|inventor3-first=Madhukar L.|url=https://patents.google.com/patent/US3865652A/}}</ref> Later that year, an avalanche injection type MOS was patented by [[Fujio Masuoka]], the inventor of [[flash memory]], at Toshiba<ref name="Masuoka-1972">
{{cite journal|last1=Masuoka|first1=Fujio|title=Avalanche injection type mos memory|date=31 August 1972|url=https://patents.google.com/patent/US3868187A/en}}
</ref> and IBM patented another later that year.<ref>{{Cite patent|number=US3797000A|title=Non-volatile semiconductor storage device utilizing avalanche injection and extraction of stored information|gdate=1974-03-12|invent1=Agusta|invent2=Chang|inventor1-first=B.|inventor2-first=J.|url=https://patents.google.com/patent/US3797000}}</ref>

In 1974, [[NEC]] patented a electrically erasable carrier injection device.<ref>{{Cite patent|number=US4016588A|title=Non-volatile semiconductor memory device|gdate=1977-04-05|invent1=Ohya|invent2=Kikuchi|inventor1-first=Shuichi|inventor2-first=Masanori|url=https://patents.google.com/patent/US4016588A}}</ref> The next year, NEC applied for the trademark "EEPROM®" with the Japan Patent Office. The trademark was granted in 1978.<ref>
{{cite web|title=EEPROM|url=https://www.tmdn.org/tmview/get-detail?st13=JP501975000139811|website=TMview|url-status=live|archive-url=https://web.archive.org/web/20180310010029/https://www.tmdn.org/tmview/get-detail?st13=JP501975000139811|archive-date=2018-03-10}}
</ref><ref>{{cite web|title=Reg. No.1342184 {{endash}} LIVE {{endash}} REGISTRATION {{endash}} Issued and Active|url=https://www.j-platpat.inpit.go.jp/web/TR/JPT_1342184/1767B48BDBDDD17B2CDA0380D54389D9}}</ref>

The theoretical basis of these devices is [[Avalanche breakdown|avalanche]] [[hot-carrier injection]]. In general, programmable memories, including EPROM, of early 1970s had reliability and endurance problems such as the data retention periods and the number of erase/write cycles.<ref name="Moskowitz 2016">
{{cite book |last1=Moskowitz |first1=Sanford L. |url=https://books.google.com/books?id=FyT3DAAAQBAJ&q="reliability%20problems"+EPROM+1970s&pg=PA187 |title=Advanced Materials Innovation: Managing Global Technology in the 21st century |date=2016 |publisher=John Wiley & Sons |isbn=9781118986097 |language=en}}
</ref>

Most of the major semiconductor manufactures, such as
[[Toshiba]],<ref name="Masuoka-1972" /><ref name="Iizuka-1976" />
[[Sanyo]] (later, [[ON Semiconductor]]),<ref>
{{cite web |publisher=Google Patents |last1=Rai |first1=Yasuki |last2=Sasami |first2=Terutoshi |last3=Hasegawa |first3=Yuzuru |last4=Okazoe |first4=Masaru |date=1973-05-18 |title=Electrically reprogrammable nonvolatile floating gate semi-conductor memory device and method of operation |url=https://patents.google.com/patent/US4004159A/en |url-status=live |archive-url=https://web.archive.org/web/20180503153251/https://patents.google.com/patent/US4004159A/en |archive-date=2018-05-03}}
</ref>
[[IBM]],<ref>
{{cite web |last1=Abbas |first1=Shakir A. |last2=Barile |first2=Conrad A. |last3=Lane |first3=Ralph D. |last4=Liu. |first4=Peter T |date=1973-03-16 |title=US3836992A; Electrically erasable floating gate fet memory cell |url=http://pdfpiw.uspto.gov/.piw?Docid=3836992 |url-status=dead |archive-url=https://web.archive.org/web/20180309182950/http://pdfpiw.uspto.gov/.piw?Docid=3836992 |archive-date=2018-03-09 |publisher=United States Patent and Trademark Office}}
</ref>
[[Intel]],<ref>
{{cite web |last1=Frohman |first1=Bentchkowsky D |date=19 October 1973 |title=Electrically alterable floating gate device and method for altering same |url=https://patents.google.com/patent/US3825946A/en |publisher=Google Patents }}
</ref><ref>
{{cite journal |last1=Chou |first1=Sunlin |date=26 February 1973 |title=Erasable floating gate device |url=https://patents.google.com/patent/US3919711A/en}}
</ref>
[[NEC]] (later, [[Renesas Electronics]]),<ref name="NEC-1974">
{{cite journal |last1=Ohya |first1=Shuichi |last2=Kikuchi |first2=Masanori |date=1974-12-27 |title=Non-volatile semiconductor memory device |url=https://patents.google.com/patent/US4016588A/en}}</ref>
[[Philips]] (later, [[NXP Semiconductors]]),<ref>
{{cite journal |last1=Verwey |first1=J. F. |last2=Kramer |first2=R. P. |date=1974 |title=Atmos—An electrically reprogrammable read-only memory device |journal=IEEE Transactions on Electron Devices |volume=21 |issue=10 |pages=631–636 |bibcode=1974ITED...21..631V |doi=10.1109/T-ED.1974.17981 |issn=0018-9383}}
</ref>
[[Siemens]] (later, [[Infineon Technologies]]),<ref>
{{cite journal |last1=B. |first1=Roessler |last2=R. G. |first2=Mueller |date=1975 |title=Erasable and electrically reprogrammable read-only memory using the N-channel SIMOS one-transistor cell |journal=Siemens Forschungs und Entwicklungsberichte |volume=4 |issue=6 |pages=345–351 |bibcode=1975SiFoE...4..345R}}
</ref>
[[Honeywell]] (later, [[Atmel]]),<ref>
{{cite journal |last1=Jack |first1=S |last2=Huang |first2=T. |date=8 September 1975 |title=Semiconductor memory cell |url=https://patents.google.com/patent/US4051464A/en}}
</ref>
[[Texas Instruments]],<ref>
{{cite journal |last1=Gosney |first1=W. M. |date=1977 |title=DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology |journal=IEEE Transactions on Electron Devices |volume=24 |issue=5 |pages=594–599 |bibcode=1977ITED...24..594G |doi=10.1109/T-ED.1977.18786 |issn=0018-9383 |s2cid=45636024}}
</ref>
studied, invented, and manufactured some electrically re-programmable non-volatile devices until 1977.

=== Modern EEPROM ===
The first EEPROM that used [[Field electron emission#Fowler–Nordheim tunneling|Fowler-Nordheim tunnelling]] to erase data was invented by Bernward and patented by [[Siemens]] in 1974.<ref>{{Cite patent|number=GB1517925A|title=Storage field effect transistors|gdate=1978-07-19|url=https://patents.google.com/patent/GB1517925A/en}}</ref> In February 1977, Israeli-American [[Eli Harari|Eliyahou Harari]] at [[Hughes Aircraft Company]] patented in the US a modern EEPROM technology, based on Fowler-Nordheim tunnelling through a thin [[silicon dioxide]] layer between the [[Floating-gate MOSFET|floating-gate]] and the [[wafer (electronics)|wafer]].
Hughes went on to produce this new EEPROM devices.<ref>{{cite web |url=http://archive.computerhistory.org/resources/access/text/2012/03/102745933-05-01-acc.pdf |title= 1027459330501acc.pdf |access-date=2015-02-05 |url-status=live |archive-url=http://archive.wikiwix.com/cache/20150207004103/http://archive.computerhistory.org/resources/access/text/2012/03/102745933-05-01-acc.pdf |archive-date=2015-02-07 }}</ref>

In May 1977, some important research result was disclosed by [[Fairchild Camera and Instrument|Fairchild]] and [[Siemens]]. They used ''SONOS'' ([[polysilicon]]-[[Silicon oxynitride|oxynitride]]-[[nitride]]-[[oxide]]-[[silicon]]) structure with thickness of silicon dioxide less than 30 [[Ångström|Å]], and ''SIMOS'' (stacked-gate [[Hot-carrier injection|injection]] [[MOSFET|MOS]]) structure, respectively, for using [[Field electron emission#Fowler–Nordheim tunneling|''Fowler-Nordheim tunnelling'']] [[hot-carrier injection]].<ref>
{{cite journal|last1=Chen|first1=P. C. Y.|title=Threshold-alterable Si-gate MOS devices|journal=IEEE Transactions on Electron Devices|date=May 1977|volume=24|issue=5|pages=584–586|doi=10.1109/T-ED.1977.18783|issn=0018-9383|bibcode=1977ITED...24..584C|s2cid=25586393}}
</ref><ref>
{{cite journal|last1=Rossler|first1=B.|title=Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell|journal=IEEE Transactions on Electron Devices|date=May 1977|volume=24|issue=5|pages=606–610|doi=10.1109/T-ED.1977.18788|issn=0018-9383|bibcode=1977ITED...24..606R|s2cid=33203267}}
</ref>

Around 1976 to 1978, Intel's team, including [[George Perlegos]], made some inventions to improve this tunneling E<sup>2</sup>PROM technology.<ref>
{{cite web|last1=Simko|first1=Richard T.|title=Electrically programmable and electrically erasable MOS memory cell|url=https://patents.google.com/patent/US4119995A/en|date=17 March 1977}}
</ref><ref>
{{cite web|last1=Frohman-Bentchkowsky|first1=Dov|last2=Mar|first2=Jerry|last3=Perlegos|first3=George|last4=Johnson|first4=William S.|title=Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same|url=https://patents.google.com/patent/US4203158A/en|date=15 December 1978}}
</ref>
In 1978, they developed a 16K (2K word × 8) bit ''Intel 2816'' chip with a thin [[silicon dioxide]] layer, which was less than 200 [[Ångström|Å]].<ref>
{{cite book|last1=Dummer|first1=G. W. A.|title=Electronic Inventions and Discoveries: Electronics from Its Earliest Beginnings to the Present Day|date=2013|publisher=Elsevier|isbn=9781483145211|url=https://books.google.com/books?id=PbYgBQAAQBAJ&q=Intel+FLOTOX&pg=PA212|language=en}}
</ref>
In 1980, this structure was publicly introduced as ''FLOTOX''; [[Floating-gate MOSFET|floating gate]] [[Tunnel junction|tunnel]] [[oxide]].<ref>
{{cite book|last1=Johnson|first1=W.|last2=Perlegos|first2=G.|last3=Renninger|first3=A.|last4=Kuhn|first4=G.|last5=Ranganath|first5=T.|title=1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |chapter=A 16Kb electrically erasable nonvolatile memory |date=1980|volume=XXIII|pages=152–153|doi=10.1109/ISSCC.1980.1156030|s2cid=44313709}}
</ref>
The ''FLOTOX'' structure improved reliability of erase/write cycles per byte up to 10,000 times.<ref>
{{cite book|last1=Euzent|first1=B.|last2=Boruta|first2=N.|last3=Lee|first3=J.|last4=Jenq|first4=C.|chapter=Reliability Aspects of a Floating Gate E2 PROM |title=19th International Reliability Physics Symposium|date=1981|pages=11–16|doi=10.1109/IRPS.1981.362965|s2cid=41116025|quote=The Intel 2816 uses the FLOTOX structure, which has been discussed in detail in the literaturel. Basically, it uses an oxide of less than 200A thick between the floating polysilicon gate and the N+ region as shown in Figure 1.}}
</ref>
But this device required additional 20{{endash}}22V V<sub>PP</sub> bias voltage supply for byte erase, except for 5V read operations.<ref>
{{cite book|title=2816A-2 PDF Datasheet - Intel Corporation - Datasheets360.com|date=October 1983|publisher=Intel|url=http://www.datasheets360.com/pdf/3161437977278813752}}
</ref>{{rp|5{{hyphen}}86}}
In 1981, Perlegos and 2 other members left Intel to form [[Atmel#Founding and 1980s growth|Seeq Technology]],<ref>
{{cite web|url=http://www.antiquetech.com/?page_id=900|title=Seeq Technology » AntiqueTech|url-status=live|archive-url=https://web.archive.org/web/20141002212230/http://www.antiquetech.com/?page_id=900|archive-date=2014-10-02}}</ref>
which used on-device [[charge pump]]s to supply the high voltages necessary for programming E<sup>2</sup>PROMs.
In 1984, Perlogos left Seeq Technology to found [[Atmel]], then Seeq Technology was acquired by Atmel.<ref>{{Cite journal
 |last        = Rostky
 |first       = George
 |title       = Remembering the PROM knights of Intel
 |journal     = EE Times
 |date        = July 2, 2002
 |url         = http://www.eetimes.com/issue/fp/showArticle.jhtml;?articleID=18307418
 |access-date  = 2007-02-08
 |url-status     = live
 |archive-url  = https://web.archive.org/web/20070929104409/http://www.eetimes.com/issue/fp/showArticle.jhtml;?articleID=18307418
 |archive-date = September 29, 2007
}}</ref><ref>
{{cite book|title=Atmel AT28C16 datasheet|date=October 1998|edition=0540B|url=http://cva.stanford.edu/classes/cs99s/datasheets/at28c16.pdf|url-status=live|archive-url=https://web.archive.org/web/20170829005334/http://cva.stanford.edu/classes/cs99s/datasheets/at28c16.pdf|archive-date=2017-08-29}}
</ref>

Electrically alterable read-only memory (EAROM) is a type of EEPROM that can be modified one or a few [[bit]]s at a time.<ref>{{cite book | url=https://books.google.com/books?id=ocjJE4KtZq4C&dq=Electrically+alterable+read-only+memory+%28EAROM%29&pg=PA130 | title=Ciarcia's Circuit Cellar | isbn=978-0-07-010963-6 | last1=Ciarcia | first1=Steve | date=1981 | publisher=Circuit Cellar }}</ref> Writing is a very slow process and again needs higher voltage (usually around 12 [[Volt|V]]) than is used for read access. EAROMs are intended for applications that require infrequent and only partial rewriting.

=={{anchor|FLOTOX}}Theoretical basis of FLOTOX structure==

As is described in former section, old EEPROMs are based on [[avalanche breakdown]]-based [[hot-carrier injection]] with high [[breakdown voltage|reverse breakdown voltage]]. But ''FLOTOX'' theoretical basis is [[Field electron emission#Fowler–Nordheim tunneling|Fowler–Nordheim tunneling]] [[hot-carrier injection]] through a thin [[silicon dioxide]] layer between the [[Floating-gate MOSFET|floating gate]] and the wafer. In other words, it uses a [[tunnel junction]].<ref name="Gutmann-2001">
{{cite journal |last1=Gutmann |first1=Peter |title=Data Remanence in Semiconductor Devices |journal=10th USENIX SECURITY SYMPOSIUM |date=2001-08-15 |pages=39–54 |url=http://static.usenix.org/legacy/events/sec01/full_papers/gutmann/gutmann_html/#_Ref513619292 |publisher=IBM T. J. Watson Research Center |url-status=live |archive-url=https://web.archive.org/web/20161012131700/http://static.usenix.org/legacy/events/sec01/full_papers/gutmann/gutmann_html/#_Ref513619292 |archive-date=2016-10-12}}
</ref>

Theoretical basis of the physical phenomenon itself is the same as today's [[flash memory]]. But each FLOTOX structure is in conjunction with another read-control transistor because the floating gate itself is just programming and erasing one data bit.<ref>
{{cite web |last1=Janwadkar |first1=Sudhanshu |title=Fabrication of Floating Gate MOS (FLOTOX) |url=https://www.slideshare.net/shudhanshu29/fabrication-of-floating-gate-mos-flotox |website=www.slideshare.net |date=2017-10-24}}
</ref>

Intel's FLOTOX device structure improved EEPROM reliability, in other words, the endurance of the write and erase cycles, and the data retention period. A material of study for [[single-event upset|single-event effect]] about FLOTOX is available.<ref>
{{cite web |last1=Koga |first1=R. |last2=Tran |first2=V. |last3=George |first3=J. |last4=Crawford |first4=K. |last5=Crain |first5=S. |last6=Zakrzewski |first6=M. |last7=Yu |first7=P. |title=SEE Sensitivities of Selected Advanced Flash and First-In-First-Out Memories |url=http://www.ti.com/pdfs/hirel/space/V3690SEE.pdf |publisher=The Aerospace Corporation |url-status=live |archive-url=https://web.archive.org/web/20180314042641/http://www.ti.com/pdfs/hirel/space/V3690SEE.pdf |archive-date=2018-03-14}}
</ref>

Today, an academic explanation of the FLOTOX device structure can be found in several sources.<ref>{{cite book |last1=Fuller |first1=Dr. Lynn |title=CMOS Process Variations EEPROM Fabrication Technology |date=2012-02-22 |publisher=Microelectronic Engineering, Rochester Institute of Technology |url=https://people.rit.edu/lffeee/EEPROM }}{{Dead link|date=September 2024 |bot=InternetArchiveBot |fix-attempted=yes }}</ref><ref>
{{cite book |last1=Groeseneken |first1=G. |last2=Maes |first2=H. E. |last3=VanHoudt |first3=J. |last4=Witters |first4=J. S. |title=Basics of Nonvolatile Semiconductor Memory Devices |citeseerx=10.1.1.111.9431}}</ref><ref>
{{cite web |last1=Bergemont |first1=Albert |last2=Chi |first2=Min-Hwa |title=US Patent 5856222: Method of fabricating a high density EEPROM cell |url=https://patents.google.com/patent/US5856222A/en |website=patents.google.com |publisher=National Semiconductor Corp. |date=1997-05-05}}
</ref>

==Today's EEPROM structure==

Nowadays, EEPROM is used for embedded [[microcontrollers]] as well as standard EEPROM products.
EEPROM still requires a 2-transistor structure per bit to erase a dedicated byte in the memory, while [[flash memory]] has 1 transistor per bit to erase a region of the memory.<ref name="Skorobogatov 2017">
{{cite conference |last=Skorobogatov |first=Sergei |title=2017 Euromicro Conference on Digital System Design (DSD) |chapter=How Microprobing Can Attack Encrypted Memory  |date=2017 |location=Vienna |pages=244–251 |doi=10.1109/DSD.2017.69 |chapter-url=https://www.cl.cam.ac.uk/~sps32/ahsa2017_prob.pdf#page=2 |isbn=978-1-5386-2146-2}}</ref>

==Security protections==
[[File:Sim Chip.jpg|thumbnail|Inside of a [[Subscriber identity module|SIM card]]]]
Because EEPROM technology is used for some security gadgets, such as credit cards, SIM cards, key-less entry, etc., some devices have security protection mechanisms, such as copy-protection.<ref name="Skorobogatov 2017"/><ref>
{{cite web|title=Breaking copy protection in microcontrollers|url=https://www.cl.cam.ac.uk/~sps32/mcu_lock.html|website=www.cl.cam.ac.uk|url-status=live|archive-url=https://web.archive.org/web/20171022043128/http://www.cl.cam.ac.uk/~sps32/mcu_lock.html|archive-date=2017-10-22}}
</ref>

==Electrical interface==
EEPROM devices use a serial or parallel interface for data input/output.

===Serial bus devices===
The common serial interfaces are [[Serial Peripheral Interface Bus|SPI]], [[I²C]], [[Microwire]], [[UNI/O]], and [[1-Wire]]. These use from one to four device pins and allow devices to use packages with eight pins or less.

A typical EEPROM serial protocol consists of three phases: [[Opcode|OP-code phase]], address phase and data phase. The OP-code is usually the first 8 bits input to the serial input pin of the EEPROM device (or with most I²C devices, is implicit); followed by 8 to 24 bits of addressing, depending on the depth of the device, then the read or write data.

Each EEPROM device typically has its own set of OP-code instructions mapped to different functions. Common operations on [[Serial Peripheral Interface Bus|SPI]] EEPROM devices are:
* Write enable (WRENAL)
* Write disable (WRDI)
* Read status register (RDSR)
* Write status register (WRSR)
* Read data (READ)
* Write data (WRITE)

Other operations supported by some EEPROM devices are:
* Program
* Sector erase
* Chip erase commands

===Parallel bus devices===
Parallel EEPROM devices typically have an 8-bit data bus and an address bus wide enough to cover the complete memory. Most devices have chip select and write protect pins. Some [[microcontroller]]s also have integrated parallel EEPROM.

Operation of a parallel EEPROM is simple and fast when compared to serial EEPROM, but these devices are larger due to the higher pin count (28 pins or more) and have been decreasing in popularity in favor of serial EEPROM or flash.

===Other devices===
EEPROM memory is used to enable features in other types of products that are not strictly memory products. Products such as [[real-time clock]]s, digital [[potentiometer]]s, digital [[Silicon bandgap temperature sensor|temperature sensor]]s, among others, may have small amounts of EEPROM to store calibration information or other data that needs to be available in the event of power loss.
It was also used on [[video game cartridge]]s to save game progress and configurations, before the usage of external and internal flash memories.

==Failure modes==
There are two limitations of stored information: endurance and data retention.

During rewrites, the gate oxide in the [[floating-gate transistor]]s gradually accumulates trapped electrons. The electric field of the trapped electrons adds to the electrons in the floating gate, lowering the window between threshold voltages for zeros vs ones. After sufficient number of rewrite cycles, the difference becomes too small to be recognizable, the cell is stuck in programmed state, and endurance failure occurs. The manufacturers usually specify the maximum number of rewrites being 1 million or more.<ref>{{cite web|url=http://www.rohm.com/products/lsi/eeprom/faq.html|title=Frequently Asked Questions -ROHM Semiconductor|url-status=live|archive-url=https://web.archive.org/web/20110219060902/http://www.rohm.com/products/lsi/eeprom/faq.html|archive-date=2011-02-19}}</ref>

During storage, the electrons injected into the floating gate may drift through the insulator, especially at increased temperature, and cause charge loss, reverting the cell into erased state. The manufacturers usually guarantee data retention of 10 years or more.<ref>System Integration - From Transistor Design to Large Scale Integrated Circuits</ref>

==Related types==
[[Flash memory]] is a later form of EEPROM. In the industry, there is a convention to reserve the term EEPROM to byte-wise erasable memories compared to block-wise erasable flash memories. EEPROM occupies more die area than flash memory for the same capacity, because each cell usually needs a read, a write, and an erase [[transistor]], while flash memory  erase circuits are shared by large blocks of cells (often 512×8).

Newer non-volatile memory technologies such as [[Ferroelectric RAM|FeRAM]] and [[Magnetoresistive RAM|MRAM]] are slowly replacing EEPROMs in some applications, but are expected to remain a small fraction of the EEPROM market for the foreseeable future.

===Comparison with EPROM and EEPROM/flash===
The difference between [[EPROM]] and EEPROM lies in the way that the memory programs and erases. EEPROM can be programmed and erased electrically using [[field electron emission]] (more commonly known in the industry as "Fowler–Nordheim tunneling").

EPROMs can't be erased electrically and are programmed by [[hot-carrier injection]] onto the floating gate. Erase is by an [[ultraviolet]] light source, although in practice many EPROMs are encapsulated in plastic that is opaque to UV light, making them "one-time programmable".

Most NOR flash memory is a hybrid style—programming is through [[hot-carrier injection]] and erase is through [[Field electron emission#Fowler–Nordheim tunneling|Fowler–Nordheim tunneling]].

{| class="wikitable"
|- class="hintergrundfarbe6"
! Type
! Inject electrons onto gate<br />(mostly interpreted as bit=0)
! Duration
! Remove electrons from gate<br />(mostly interpreted as bit=1)
! Duration/mode
|-
| EEPROM || field electron emission || 0.1—5 ms, bytewise || field electron emission || 0.1—5 ms, blockwise
|-
| NOR flash memory || hot-carrier injection || 0.01—1 ms || field electron emission || 0.01—1 ms, blockwise
|-
| EPROM  || hot-carrier injection || 3—50 ms, bytewise || ultraviolet light <400&nbsp;nm || 5–30 minutes, whole chip
|-
|}

==See also==
* [[Avalanche breakdown]]
* [[DataFlash]]
* [[EPROM]]
* {{slink|Field electron emission|Fowler–Nordheim tunneling}}
* [[Flash memory]]
* [[Floating-gate MOSFET]]
* [[Intel HEX]] – file format
* [[Programmer (hardware)]]
* [[Quantum tunnelling]]
* [[SREC (file format)|SREC]] – file format
* [[Tunnel junction]]
* [[Read-mostly memory]] (RMM)

==References==
{{Reflist}}

==External links==
* [http://static.usenix.org/legacy/events/sec01/full_papers/gutmann/gutmann_html/ Gutmann (2001) papaer: "Data Remanence in Semiconductor Devices" {{!}} USENIX]

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