View source for ECC memory

{{short description|Self-correcting computer data storage}}
[[File:Micron PC2700 DDR ECC REG.JPG|300px|thumb|ECC [[DIMM]]s typically have nine memory chips on each side, one more than usually found on non-ECC DIMMs (some modules may have 5 or 18).<ref>{{cite web | url = http://www.admin-magazine.com/Articles/RAM-Revealed | title = RAM Revealed | access-date = October 20, 2014 | author = Werner Fischer | website = ADMIN Magazine }}</ref>]]

'''Error correction code memory''' ('''ECC memory''') is a type of [[computer data storage]] that uses an [[error correction code]]{{efn|Most ECC memory uses a [[SECDED]] code.|name=SECDED}} (ECC) to detect and correct ''n''-bit [[data corruption]] which occurs in memory.

Typically, ECC memory maintains a memory system immune to single-bit errors: the data that is read from each [[Word (computer architecture)|word]] is always the same as the data that had been written to it, even if one of the bits actually stored has been flipped to the wrong state. Most non-ECC memory cannot detect errors, although some non-ECC memory with parity support allows detection but not correction.

ECC memory is used in most computers where data corruption cannot be tolerated, like industrial control applications, critical databases, and infrastructural memory caches.

== Concept ==

Error correction codes protect against undetected data corruption and are used in computers where such corruption is unacceptable, examples being scientific and financial computing applications, or in [[server (hardware)|database and file server]]s. ECC can also reduce the number of crashes in multi-user server applications and maximum-availability systems.

Electrical or magnetic interference inside a computer system can cause a single bit of [[dynamic random-access memory]] (DRAM) to spontaneously flip to the opposite state. It was initially thought that this was mainly due to [[alpha particle]]s emitted by contaminants in chip packaging material, but research has shown that the majority of one-off [[soft error]]s in DRAM chips occur as a result of [[background radiation]], chiefly [[neutron]]s from [[cosmic ray]] secondaries, which may change the contents of one or more [[Memory cell (computing)|memory cells]] or interfere with the circuitry used to read or write to them.<ref name="Boeing1" /> Hence, the error rates increase rapidly with rising altitude; for example, compared to sea level, the rate of [[neutron flux]] is 3.5 times higher at 1.5&nbsp;km and 300 times higher at 10–12&nbsp;km (the cruising altitude of commercial airplanes).<ref name="ieee-tpds">"[https://dx.doi.org/10.1109/TPDS.2015.2426179 A Survey of Techniques for Modeling and Improving Reliability of Computing Systems]", IEEE TPDS, 2015.</ref> As a result, systems operating at high altitudes require special provisions for reliability.

As an example, the spacecraft ''[[Cassini–Huygens]]'', launched in 1997, contained two identical flight recorders, each with 2.5 gigabits of memory in the form of arrays of commercial DRAM chips. Due to built-in [[error detection and correction|EDAC]] functionality, the spacecraft's engineering telemetry reported the number of (correctable) single-bit-per-word errors and (uncorrectable) double-bit-per-word errors. During the first 2.5 years of flight, the spacecraft reported a nearly constant single-bit error rate of about 280 errors per day. However, on November&nbsp;6, 1997, during the first month in space, the number of errors increased by more than a factor of four on that single day. This was attributed to a [[solar particle event]] that had been detected by the satellite [[GOES&nbsp;9]].<ref name="Auto7P-1" />

There was some concern that as DRAM density increases further, and thus the components on chips get smaller, while operating voltages continue to fall, DRAM chips will be affected by such radiation more frequently, since lower-energy particles will be able to change a memory cell's state.<ref name="ieee-tpds" /> On the other hand, smaller cells make smaller targets, and moves to technologies such as [[Silicon on insulator|SOI]] may make individual cells less susceptible and so counteract, or even reverse, this trend. Recent studies<ref name="Borucki1" /> show that single-event upsets due to cosmic radiation have been dropping dramatically with process geometry, and previous concerns over increasing bit cell error rates are unfounded.

== Research ==
Work published between 2007 and 2009 showed widely varying error rates with over 7 orders of magnitude difference, ranging from {{val|e=−10|u=error/(bit·h)}}, roughly one bit error per hour per gigabyte of memory, to {{val|e=−17|u=error/(bit·h)}}, roughly one bit error per millennium per gigabyte of memory.<ref name="Borucki1" /><ref name="Schroeder1" /><ref name="Xin1" /> A large-scale study based on [[Google]]'s very large number of servers was presented at the SIGMETRICS/Performance&nbsp;'09 conference.<ref name="Schroeder1" /> The actual error rate found was several orders of magnitude higher than the previous small-scale or laboratory studies, with between 25,000 ({{val|2.5|e=−11|u=error/(bit·h)}}) and 70,000 ({{val|7.0|e=−11|u=error/(bit·h)}}, or 1 bit error per gigabyte of RAM per 1.8 hours) errors per billion device hours per megabit. More than 8% of DIMM memory modules were affected by errors per year.

The consequence of a memory error is system-dependent. In systems without ECC, an error can lead either to a crash or to corruption of data; in large-scale production sites, memory errors are one of the most-common hardware causes of machine crashes.<ref name="Schroeder1" /> Memory errors can cause security vulnerabilities.<ref name="Schroeder1" /> A memory error can have no consequences if it changes a bit which neither causes observable malfunctioning nor affects data used in calculations or saved. A 2010 simulation study showed that, for a web browser, only a small fraction of memory errors caused data corruption, although, as many memory errors are intermittent and correlated, the effects of memory errors were greater than would be expected for independent soft errors.<ref>{{cite web |url=http://www.cs.rochester.edu/~kshen/papers/usenix2010-li.pdf |title=A Realistic Evaluation of Memory Hardware Errors and Software System Susceptibility |work=Usenix Annual Tech Conference 2010 |author1=Li, Huang |author2=Shen, Chu |year=2010}}</ref>

Some tests conclude that the isolation of [[DRAM]] memory cells can be circumvented by unintended side effects of specially crafted accesses to adjacent cells. Thus, accessing data stored in DRAM causes memory cells to leak their charges and interact electrically, as a result of high cell density in modern memory, altering the content of nearby memory rows that actually were not addressed in the original memory access. This effect is known as [[row hammer]], and it has also been used in some [[privilege escalation]] computer security [[Exploit (computer security)|exploits]].<ref>{{cite web
 | url = http://users.ece.cmu.edu/~yoonguk/papers/kim-isca14.pdf
 | title = Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors
 | date = 2014-06-24 | access-date = 2015-03-10
 | author1 = Yoongu Kim | author2 = Ross Daly | author3 = Jeremie Kim
 | author4 = Chris Fallin | author5 = Ji Hye Lee | author6 = Donghyuk Lee
 | author7 = Chris Wilkerson | author8 = Konrad Lai | author9 = Onur Mutlu
 | publisher = [[IEEE]] | website = ece.cmu.edu
 }}</ref><ref>{{cite web
 | url = https://arstechnica.com/security/2015/03/cutting-edge-hack-gives-super-user-status-by-exploiting-dram-weakness/
 | title = Cutting-edge hack gives super user status by exploiting DRAM weakness
 | date = 2015-03-10 | access-date = 2015-03-10
 | author = Dan Goodin | publisher = [[Ars Technica]]
}}</ref>

An example of a single-bit error that would be ignored by a system with no error-checking, would halt a machine with parity checking or be invisibly corrected by ECC: a single bit is stuck at 1 due to a faulty chip, or becomes changed to 1 due to background or cosmic radiation; a spreadsheet storing numbers in ASCII format is loaded, and the character "8" (decimal value 56 in the ASCII encoding) is stored in the byte that contains the stuck bit at its lowest bit position; then, a change is made to the spreadsheet and it is saved. As a result, the "8" (0011 100'''0''' binary) has silently become a "9" (0011 100'''1''').

== Solutions ==
Several approaches have been developed to deal with unwanted bit-flips, including immunity-aware programming, [[RAM parity]] memory, and [[Error detection and correction|ECC]] memory.

This problem can be mitigated by using DRAM modules that include extra memory bits and memory controllers that exploit these bits. These extra bits are used to record [[RAM parity|parity]] or to use an [[error-correcting code]] (ECC). Parity allows the detection of all single-bit errors (actually, any odd number of wrong bits). The most-common error correcting code, a [[single-error correction and double-error detection]] (SECDED) [[Hamming code]], allows a single-bit error to be corrected and (in the usual configuration, with an extra parity bit) double-bit errors to be detected. [[Chipkill]] ECC is a more effective version that also corrects for multiple bit errors, including the loss of an entire memory chip.

== Implementations ==
[[File:Cromemco 512MSU error correcting S-100 memory storage unit.jpg|thumb|In 1982 this 512&nbsp;KB memory board from [[Cromemco]] used 22 bits of storage per 16-bit word to perform single-bit error correction.]]
[[Seymour Cray]] famously said "[[Doctrine of parity|parity is for farmers]]" when asked why he left this out of the [[CDC&nbsp;6600]].<ref name="Bell1" /> Later, [[Parity bit#History|he included]] parity in the [[CDC&nbsp;7600]], which caused pundits to remark that "apparently a lot of farmers buy computers". The original [[IBM&nbsp;PC]] and all PCs until the early 1990s used parity checking.<ref name="Auto7P-2" /> Later ones mostly did not.

An ECC-capable memory controller can generally{{efn|name=SECDED}} detect and correct errors of a single bit per [[Word (computer architecture)|word]]{{efn|While 72-bit word with 64 data bits and 8 checking bits are common, ECC is also used with smaller and larger sizes.}} (the unit of [[Computer bus|bus]] transfer), and detect (but not correct) errors of two bits per word. The [[BIOS]] in some computers, when matched with operating systems such as some versions of [[Linux]], [[BSD]], and [[Windows]] ([[Windows 2000]] and later<ref>{{Cite web |last=DOMARS |title=<code>!mca</code> |url=https://docs.microsoft.com/en-us/windows-hardware/drivers/debugger/-mca |access-date=2021-03-27 |website=Microsoft Learn |language=en-us}}</ref>), allows counting of detected and corrected memory errors, in part to help identify failing memory modules before the problem becomes catastrophic.

Some DRAM chips include "internal" on-chip error-correction circuits, which allow systems with non-ECC memory controllers to still gain most of the benefits of ECC memory.<ref name="johnston">A. H. Johnston. [http://trs-new.jpl.nasa.gov/dspace/bitstream/2014/13431/1/01-2369.pdf "Space Radiation Effects in Advanced Flash Memories"]. {{webarchive|url=https://web.archive.org/web/20160304220536/http://trs-new.jpl.nasa.gov/dspace/bitstream/2014/13431/1/01-2369.pdf|date=2016-03-04}}. NASA Electronic Parts and Packaging Program (NEPP). 2001.</ref><ref>{{cite web |title=ECC DRAM |url=http://www.intelligentmemory.com/ECC-DRAM/ |archive-url=https://web.archive.org/web/20190212175122/https://www.intelligentmemory.com/ECC-DRAM/ |archive-date=2019-02-12 |access-date=2021-06-12 |website=Intelligent Memory}}</ref> In some systems, a similar effect may be achieved by using [[EOS memory]] modules.

[[Error detection and correction]] depends on an expectation of the kinds of errors that occur. Implicitly, it is assumed that the failure of each bit in a word of memory is independent, resulting in improbability of two simultaneous errors. This used to be the case when memory chips were one-bit wide, what was typical in the first half of the 1980s; later developments moved many bits into the same chip. This weakness is addressed by various technologies, including [[IBM]]'s [[Chipkill]], [[Sun Microsystems]]' [[Extended ECC]], [[Hewlett-Packard]]'s [[Chipspare]], and [[Intel]]'s [[Single Device Data Correction]] (SDDC).

[[Dynamic random-access memory|DRAM]] memory may provide increased protection against [[soft error]]s by relying on error-correcting codes. Such [[Dynamic random-access memory#Error detection and correction|error-correcting memory]], known as ''ECC'' or ''EDAC-protected'' memory, is particularly desirable for highly fault-tolerant applications, such as servers, as well as deep-space applications due to increased [[cosmic ray|radiation]]. Some systems also "[[Memory scrubbing|scrub]]" the memory, by periodically reading all addresses and writing back corrected versions if necessary to remove soft errors.

[[Forward error correction#Interleaving|Interleaving]] allows distribution of the effect of a single cosmic ray, potentially upsetting multiple physically neighboring bits across multiple words by associating neighboring bits to different words. As long as a [[single-event upset]] (SEU) does not exceed the error threshold (e.g., a single error) in any particular word between accesses, it can be corrected (e.g., by a single-bit error-correcting code), and an effectively error-free memory system may be maintained.<ref name="apmcsta1" />

Error-correcting memory controllers traditionally use [[Hamming code]]s, although some use [[triple modular redundancy]] (TMR). The latter is preferred because its hardware is faster than that of Hamming error-correction scheme.<ref name="apmcsta1" /> Space satellite systems often use TMR,<ref name="Auto7P-3" /><ref name="Auto7P-4" /><ref name="Auto7P-5" /> although satellite RAM usually uses Hamming error correction.<ref name="Auto7P-6" />

Many early implementations of ECC memory mask correctable errors, acting "as if" the error never occurred, and only report uncorrectable errors. Modern implementations log both correctable errors (CE) and uncorrectable errors (UE). Some people proactively replace memory modules that exhibit high error rates, in order to reduce the likelihood of uncorrectable error events.<ref>
Doug Thompson, Mauro Carvalho Chehab.
[https://www.kernel.org/doc/Documentation/edac.txt "EDAC – Error Detection And Correction"]. {{webarchive|url=https://web.archive.org/web/20090905174616/http://www.kernel.org/doc/Documentation/edac.txt |date=2009-09-05 }}.
2005–2009.
"The 'edac' kernel module goal is to detect and report errors that occur within the computer system running under linux."
</ref>

Many ECC memory systems use an "external" EDAC circuit between the CPU and the memory. A few systems with ECC memory use both internal and external EDAC systems; the external EDAC system should be designed to correct certain errors that the internal EDAC system is unable to correct.<ref name="johnston" /> Modern desktop and server CPUs integrate the EDAC circuit into the CPU,<ref name="AMD-762" /> even before the shift toward CPU-integrated memory controllers, which are related to the [[Non-uniform memory access|NUMA]] architecture. CPU integration enables a zero-penalty EDAC system during error-free operation.

As of 2009, the most-common error-correction codes use Hamming or Hsiao codes that provide single-bit error correction and double-bit error detection (SEC-DED). Other error-correction codes have been proposed for protecting memory{{snd}} double-bit error correcting and triple-bit error detecting (DEC-TED) codes, single-nibble error correcting and double-nibble error detecting (SNC-DND) codes, [[Reed–Solomon error correction]] codes, etc. However, in practice, multi-bit correction is usually implemented by interleaving multiple SEC-DED codes.<ref name="yoon">Doe Hyun Yoon; Mattan Erez. [http://users.ece.utexas.edu/~merez/mme_isca09.pdf "Memory Mapped ECC: Low-Cost Error Protection for Last Level Caches"]. 2009. p.&nbsp;3.</ref><ref>Daniele Rossi; Nicola Timoncini; Michael Spica; [[Cecilia Metra]].
[http://www.date-conference.com/proceedings/PAPERS/2011/DATE11/PDFFILES/12.5_3.PDF "Error Correcting Code Analysis for Cache Memory High Reliability and Performance"]. {{Webarchive|url=https://web.archive.org/web/20150203093300/http://www.date-conference.com/proceedings/PAPERS/2011/DATE11/PDFFILES/12.5_3.PDF |date=2015-02-03 }}.</ref>

Early research attempted to minimize the area and delay overheads of ECC circuits. Hamming first demonstrated that SEC-DED codes were possible with one particular check matrix. Hsiao showed that an alternative matrix with odd-weight columns provides SEC-DED capability with less hardware area and shorter delay than traditional Hamming SEC-DED codes.<ref>M. Y. Hsiao. [http://www.cs.berkeley.edu/~culler/cs252-s02/papers/hsiao70.pdf "A Class of Optimal Minimum Odd-weight-column SEC-DED Codes"]. 1970.</ref> More recent research also attempts to minimize power in addition to minimizing area and delay.<ref>Shalini Ghosh; Sugato Basu; and Nur A. Touba. [https://hostdb.ece.utexas.edu/~touba/research/jlpe05.pdf "Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits"]. {{Webarchive|url=https://web.archive.org/web/20150203100831/https://hostdb.ece.utexas.edu/~touba/research/jlpe05.pdf |date=2015-02-03 }}. P.&nbsp;2, 4.</ref><ref>Chris Wilkerson; Alaa R. Alameldeen; Zeshan Chishti; Wei Wu; Dinesh Somasekhar; Shih-lien Lu. [http://dl.acm.org/citation.cfm?id=1815973 "Reducing cache power with low-cost, multi-bit error-correcting codes"]. {{doi | 10.1145/1816038.1815973}}.</ref>

== Cache ==
Many CPUs use error-correction codes in the [[CPU cache|on-chip cache]], including the Intel [[Itanium]], [[Xeon]], [[Intel Core|Core]] and [[Pentium]] (since [[P6 microarchitecture]])<ref>
Intel Corporation.
[http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/xeon-e7-family-ras-server-paper.pdf "Intel Xeon Processor E7 Family: Reliability, Availability, and Serviceability"].
2011.
p. 12.
</ref><ref>{{Cite web|title=Bios and Cache |url=https://www.custom-build-computers.com/Bios-and-Cache.html|access-date=2021-03-27|website=www.custom-build-computers.com}}</ref> processors, the AMD [[Athlon]], [[Opteron]], all [[Zen (microarchitecture)|Zen]]-<ref>{{Cite web|url=https://en.wikichip.org/wiki/amd/microarchitectures/zen#Memory_Hierarchy|title=AMD Zen microarchitecture&nbsp;— Memory Hierarchy|website=WikiChip|access-date=15 October 2018}}</ref> and [[Zen+]]-based<ref>{{Cite web|url=https://en.wikichip.org/wiki/amd/microarchitectures/zen%2B#Memory_Hierarchy|title=AMD Zen+ microarchitecture&nbsp;— Memory Hierarchy|website=WikiChip|access-date=15 October 2018}}</ref> processors ([[Epyc|EPYC]], [[EPYC Embedded]], [[Ryzen]] and [[Ryzen Threadripper]]), and the DEC Alpha 21264.<ref name="yoon"/><ref>
Jangwoo Kim; Nikos Hardavellas; Ken Mai; Babak Falsafi; James C. Hoe.
[http://www.ece.cmu.edu/~truss/papers/micro07-multibit.pdf "Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding"].
2007.
p. 2.
</ref>

{{As of|2006}}, EDC/ECC and ECC/ECC are the two most-common cache error-protection techniques used in commercial microprocessors.  The EDC/ECC technique uses an error-detecting code (EDC) in the level 1 cache.  If an error is detected, data is recovered from ECC-protected level 2 cache.  The ECC/ECC technique uses an ECC-protected level 1 cache and an ECC-protected level 2 cache.<ref>
Nathan N. Sadler and Daniel J. Sorin.
[http://people.ee.duke.edu/~sorin/papers/iccd06_perc.pdf "Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache"].
2006.
p. 1.
</ref> CPUs that use the EDC/ECC technique always [[Cache (computing)#Writing policies|write-through]] all STOREs to the level 2 cache, so that when an error is detected during a read from the level 1 data cache, a copy of that data can be recovered from the level 2 cache.

== Registered memory ==
{{Main article|Registered memory}}

Registered, or buffered, memory is not the same as ECC; the technologies perform different functions. It is usual for memory used in servers to be both registered, to allow many memory modules to be used without electrical problems, and ECC, for data integrity.

== Advantages and disadvantages ==
{{Advice|date=January 2025}}
{{Speculation|date=January 2025}}

Ultimately, there is a trade-off between protection against unusual loss of data and a higher cost.

ECC memory usually{{vague|date=January 2025}} costs more than{{When|date=January 2025}} non-ECC memory, due to additional hardware required for producing ECC memory modules{{Citation Needed|date=January 2025}}, and due to lower production volumes of ECC memory and associated system hardware{{Citation needed|date=January 2025|reason=questionable, since most RAM these days probably is for cloud and other server use cases}}{{When|date=January 2025}}. Motherboards, [[chipset]]s and processors that support ECC may also be more expensive{{Vague|date=January 2025}}.

ECC support varies among motherboard manufacturers, so ECC memory may simply not be recognized by an ECC-incompatible motherboard. Most {{Vague|reason=which market? which CPU type?|date=January 2025}}{{When|date=January 2025|reason=obviously very time-dependent claim}} [[motherboard]]s and processors for less critical applications are not designed to support ECC. Some ECC-enabled boards and processors are able to support unbuffered (unregistered) ECC, but will also work with non-ECC memory; system firmware enables ECC functionality if ECC memory is installed.

ECC may lower memory performance by around 2–3 percent on some systems, depending on the application and implementation, due to the additional time needed for ECC memory controllers to perform error checking.<ref name="Auto7P-9" /> However, modern systems integrate ECC testing into the CPU, generating no additional delay to memory accesses as long as no errors are detected.<ref name="AMD-762">{{cite web |url=http://support.amd.com/us/ChipsetMotherboard_TechDocs/24462.pdf |title=AMD-762™ System Controller Software/BIOS Design Guide, p. 179}}</ref><ref>[http://forum.buildyourown.org.uk/topic.asp?ARCHIVE=true&TOPIC_ID=16274 Benchmark of AMD-762/Athlon platform with and without ECC]. {{webarchive|url=https://web.archive.org/web/20130615195425/http://forum.buildyourown.org.uk/topic.asp?ARCHIVE=true&TOPIC_ID=16274 |date=2013-06-15 }}.</ref><ref name="ECCploit">{{cite web | url = https://www.vusec.net/projects/eccploit/ | title = ECCploit: ECC Memory Vulnerable to Rowhammer Attacks After All | date = 12 November 2018 | publisher = Systems and Network Security Group at VU Amsterdam | access-date = 2018-11-22}}</ref> 

{{Off topic|date=January 2025}}
This is not the case for '''in-band ECC''', which stores tables used for protection in a reserved region of main system memory,<ref>{{cite patent |country=US |number=20190332469A1 |title=Address range based in-band memory error-correcting code protection module with syndrome buffer |inventor=Amir A. RADJAI, Nagi Aboulenein, Steve L. GEIGER, Satyajit A. JADHAV, Bezan J. KAPADIA, Vivek Kozhikkottu, Rashmi LAKKUR SUBRAMANYAM, Srithar Rames, James M. Shehadi, Jason D. VAN DYKEN |assignee=[[Intel]] |pridate=2019-07-05 |pubdate=2019-10-31 |status=abandoned}}</ref><ref>{{cite patent|country=US | number=11768731B2 |title=System and method for transparent register data error detection and correction via a communication bus |invent1=Hartlieb, Heimo |invent2=Heiling, Christian |assignee=[[Infineon Technologies]] |pridate=2019-05-03 |pubdate=2020-11-05 |status=patent}}</ref> supported by [[Intel]] for [[Chromebook]]s,<!-- p.2 Setup Notes: The In-Band ECC Option --> which showed little impact on [[web browsing]] and productivity tasks, but caused up to a 25% reduction in [[video game|gaming]] and [[video editing]] benchmarks.<!-- p.3-6 --><ref name="anandtech_18732">{{cite web |url=https://www.anandtech.com/show/18732/asrock-industrial-nucs-box1360pd4-review-raptor-lakep-ecc/2 |title=ASRock Industrial NUCS BOX-1360P/D4 Review: Raptor Lake-P Impresses, plus Surprise ECC |author=Ganesh T S |pages=2–6 |date=2023-01-29 |accessdate=2024-01-29}}</ref>

ECC supporting memory may contribute to additional power consumption due to error-correcting circuitry.{{Citation needed|date=January 2025}}

== Notes ==
{{notelist}}

== References ==
{{reflist|30em|refs=
<ref name="Boeing1">[https://web.archive.org/web/20131021190327/http://pdf.yuri.se/files/art/2.pdf Single Event Upset at Ground Level, Eugene Normand, Member, IEEE, Boeing Defense & Space Group, Seattle, WA 98124-2499]</ref>
<ref name="Borucki1">Borucki, "Comparison of Accelerated DRAM Soft Error Rates Measured at Component and System Level", 46th Annual International Reliability Physics Symposium, Phoenix, 2008, pp.&nbsp;482–487</ref>
<ref name="Auto7P-1">[https://trs.jpl.nasa.gov/bitstream/handle/2014/15831/00-1594.pdf?sequence=1 Gary M. Swift and Steven M. Guertin. "In-Flight Observations of Multiple-Bit Upset in DRAMs". Jet Propulsion Laboratory]</ref>
<ref name="Schroeder1">
*{{cite journal |url=http://www.cs.toronto.edu/~bianca/papers/sigmetrics09.pdf |doi=10.1145/2492101.1555372 |first1=Bianca |last1=Schroeder |author1-link=Bianca Schroeder |first2=Eduardo |last2=Pinheiro |first3=Wolf-Dietrich |last3=Weber |title=DRAM errors in the wild: A large-scale field study |journal=  ACM SIGMETRICS Performance Evaluation Review|volume=37 |number=1 |publisher=ACM |year=2009 |pages=193–204 |isbn=978-1-60558-511-6 }}
*{{cite news |author=Robin Harris |date=October 4, 2009 |title=DRAM error rates: Nightmare on DIMM street |url=https://www.zdnet.com/article/dram-error-rates-nightmare-on-dimm-street/ |work=ZDNet}}</ref>
<ref name="Xin1">{{cite web|url=http://www.ece.rochester.edu/~xinli/usenix07/|title=A Memory Soft Error Measurement on Production Systems|access-date=2011-06-27|archive-url=https://web.archive.org/web/20170214005146/http://www.ece.rochester.edu/~xinli/usenix07/|archive-date=2017-02-14|url-status=dead}}</ref>
<ref name="Bell1">{{cite web | url = http://research.microsoft.com/~GBell/craytalk/sld047.htm | title = CDC 6600 | publisher = Microsoft Research | access-date = 2011-11-23 }}</ref>
<ref name="Auto7P-2">{{cite web | url = http://www.pcguide.com/ref/ram/errChecking-c.html | title = Parity Checking | publisher = Pcguide.com | date = 2001-04-17 | access-date = 2011-11-23 }}</ref>
<ref name="apmcsta1">{{cite web | title = Using StrongArm SA-1110 in the On-Board Computer of Nanosatellite | publisher = Tsinghua Space Center, Tsinghua University, Beijing | access-date = 2009-02-16 | url = http://www.apmcsta.org/File/doc/Conferences/6th%20meeting/Chen%20Zhenyu.doc | url-status = dead | archive-url = https://web.archive.org/web/20111002152735/http://www.apmcsta.org/File/doc/Conferences/6th%20meeting/Chen%20Zhenyu.doc | archive-date = 2011-10-02 }}<!-- I wish I had a better reference --></ref>
<ref name="Auto7P-3">{{cite web | url = http://mae.pennnet.com/Articles/Article_Display.cfm?ARTICLE_ID=111934 | archive-url = https://archive.today/20120714031724/http://mae.pennnet.com/Articles/Article_Display.cfm?ARTICLE_ID=111934 | url-status = dead | archive-date = 2012-07-14 | title = Actel engineers use triple-module redundancy in new rad-hard FPGA | publisher = Military & Aerospace Electronics | access-date = 2009-02-16 }}</ref>
<ref name="Auto7P-4">{{cite web | url = http://klabs.org/richcontent/Papers/Synopses/nsrec94.htm | title = SEU Hardening of Field Programmable Gate Arrays (FPGAs) For Space Applications and Device Characterization | publisher = Klabs.org | date = 2010-02-03 | access-date = 2011-11-23 | url-status = dead | archive-url = https://web.archive.org/web/20111125185602/http://klabs.org/richcontent/Papers/Synopses/nsrec94.htm | archive-date = 2011-11-25 }}</ref>
<ref name="Auto7P-5">{{cite web | url = http://www.techfocusmedia.net/fpgajournal/feature_articles/20040803_space.htm | title = FPGAs in Space | publisher = Techfocusmedia.net | access-date = 2011-11-23 }}{{dead link|date=September 2017 |bot=InternetArchiveBot |fix-attempted=yes }}</ref>
<ref name="Auto7P-6">{{cite web | url = http://radhome.gsfc.nasa.gov/radhome/papers/aspen.htm | archive-url = https://web.archive.org/web/20010304133002/http://radhome.gsfc.nasa.gov/radhome/papers/aspen.htm | url-status = dead | archive-date = 2001-03-04 | title = Commercial Microelectronics Technologies for Applications in the Satellite Radiation Environment | publisher = Radhome.gsfc.nasa.gov | access-date = 2011-11-23 }}</ref>
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}}

== External links ==
* [http://pdos.csail.mit.edu/papers/softecc:ddopson-meng/softecc_ddopson-meng.pdf SoftECC: A System for Software Memory Integrity Checking]
* [http://www.fiala.me/pubs/papers/libsdc11.pdf A Tunable, Software-based DRAM Error Detection and Correction Library for HPC]
* [http://www.fiala.me/pubs/papers/sc12-redmpi.pdf Detection and Correction of Silent Data Corruption for Large-Scale High-Performance Computing]
* [http://www.smartm.com/files/salesLiterature/dram/smart_whitepaper_sbe.pdf Single-Bit Errors: A Memory Module Supplier's perspective on cause, impact and detection]
* [https://web.archive.org/web/20131228061309/http://cache-www.intel.com/cd/00/00/46/78/467819_467819.pdf Intel Xeon Processor E3 - 1200 Product Family Memory Configuration Guide]
* [https://www.phoronix.com/scan.php?page=news_item&px=Linus-Torvalds-ECC Linus Torvalds On The Importance Of ECC RAM, Calls Out Intel's "Bad Policies" Over ECC]

{{Primary storage technologies}}

[[Category:Computer memory]]
[[Category:Fault-tolerant computer systems]]