View source for Direct Media Interface

{{Short description|Intel bus for connecting CPU and I/O chipset}}
{{distinguish|Desktop Management Interface}}
{{More citations needed|date=January 2014}}
{{Infobox computer hardware bus
| name        = DMI
| fullname    = Direct Media Interface
| invent-date = 
| invent-name = [[Intel]]
| super-name  = 
| super-date  = 
| replaces    = [[Intel Hub Architecture]]
| width       = 
| speed       = {{Unbulleted list
  | v1.0 at 2&nbsp;Gbit/s 2.5 GT/s (×4 1&nbsp;GB/s)
  | v2.0 at 4&nbsp;Gbit/s 5 GT/s (×4 2&nbsp;GB/s)
  | v3.0 at 8 GT/s (×4 4&nbsp;GB/s)
  | v4.0 at 16 GT/s (×8 16&nbsp;GB/s)}}
| style       = s
}}
In [[computing]], '''Direct Media Interface''' ('''DMI''') is [[Intel]]'s proprietary link between the [[Northbridge (computing)|northbridge]] (or [[CPU]]) and [[Southbridge (computing)|southbridge]] (e.g. [[Platform Controller Hub]] family) chipset on a computer [[motherboard]].<ref>{{Cite web |title=What Is the Direct Media Interface (DMI) of Intel Processors? |url=https://www.intel.com/content/www/in/en/support/articles/000094185/processors.html |access-date=2023-06-05 |website=Intel |language=en}}</ref> It was first used between the 9xx chipsets and the [[I/O Controller Hub|ICH6]], released in 2004.<ref name=":0">{{Cite journal |date=February 17, 2005 |title=Second-Generation Intel Centrino TM Mobile Technology |url=https://www.intel.com/content/dam/www/public/us/en/documents/research/2005-vol09-iss-1-intel-technology-journal.pdf |journal=Intel Technology Journal |language=en |volume=9 |issue=1 |doi=10.1535/itj.0901 |issn=1535-864X}}</ref>{{Rp|page=1}} Previous Intel chipsets had used the [[Intel Hub Architecture]] to perform the same function, and server chipsets use a similar interface called ''Enterprise Southbridge Interface'' (ESI).<ref>{{cite web
 | url = https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/5520-5500-chipset-ioh-datasheet.pdf
 | title = Intel 5520 Chipset and Intel 5500 Chipset Datasheet
 | date = March 2009 | access-date = 2014-11-06
 | publisher = [[Intel]] }}</ref> While the "DMI" name dates back to ICH6, [[Vendor lock-in|Intel mandates]] specific combinations of compatible devices, so the presence of a DMI does not guarantee by itself that a particular northbridge&ndash;southbridge combination is allowed.
[[File:Intel_X99_chipset_(vectorized).svg|thumb|[[Intel X99]] motherboard diagram. The DMI bus is visible between CPU and PCH.]]
DMI is essentially [[PCI Express]], using multiple lanes and [[differential signaling]] to form a point-to-point link. Most implementations use a ×8 or ×4 link, while some mobile systems (e.g. 915GMS, 945GMS/GSE/GU and the [[Intel Atom|Atom]] N450) use a ×2 link, halving the bandwidth. The original implementation provides 10&nbsp;Gbit/s (1&nbsp;GB/s) in each direction using a ×4 link. The DMI provides support for concurrent traffic and [[Isochronous timing|isochronous data transfer]] capabilities.{{R|name=:0|page=3}}<ref>{{Cite web |title=Direct Media Interface (DMI) - 1.0 - ID:721073 {{!}} Intel NUC 12 Extreme / Pro X |url=https://edc.intel.com/content/www/kr/ko/publications/specification-nuc12dcm-nuc12edb/direct-media-interface-dmi/ |access-date=2023-06-05 |website=edc.intel.com}}</ref>

DMI replaced FSB ([[front-side bus|Front-Side Bus]]) which was eliminated in 2009.<ref>{{cite web | url=https://www.guru3d.com/review/core-i7-975-review/page-4/ | title=Core i7 975 review (Page 4) | date=2 June 2009 }}</ref>

==Versions==
'''DMI 1.0''', introduced in 2004 with a data transfer rate of 1&nbsp;GB/s with a ×4 link.

'''DMI 2.0''', introduced in 2011, doubles the data transfer rate to 2&nbsp;GB/s with a ×4 link. It is used to link an Intel [[CPU]] with the Intel [[Platform Controller Hub]] (PCH), which supersedes the historic implementation of a separate northbridge and southbridge.<ref>{{Cite web
 | url = https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core-desktop-vol-1-datasheet.pdf
 | title = Desktop 3rd Generation Intel Core Processor Family, Desktop Intel Pentium Processor Family, and Desktop Intel Celeron Processor Family: Datasheet - Volume 1 of 2
 | work = External Design Specification (EDS)
 | date = November 2013 | access-date = 2014-01-28
 | publisher = [[Intel]] }}</ref>{{rp|14}}

'''DMI 3.0''', released in August 2015, allows the 8&nbsp;[[Gigatransfer|GT]]/s transfer rate per lane, for a total of four lanes and 3.93&nbsp;GB/s for the CPU&ndash;PCH link. It is used by two-chip variants of the Intel [[Skylake (microarchitecture)|Skylake]] microprocessors, which are used in conjunction with [[Intel 100 Series chipsets]];<ref>{{cite web
 | url = https://www.anandtech.com/show/9483/intel-skylake-review-6700k-6600k-ddr4-ddr3-ipc-6th-generation/3
 | title = The Skylake CPU Architecture – The Intel 6th Gen Skylake Review: Core i7-6700K and i5-6600K Tested
 | date = 2015-08-05 | access-date = 2015-08-06
 | author = Ian Cutress | publisher = [[AnandTech]]
}}</ref><ref>{{cite web
 | url = https://www.anandtech.com/show/9485/intel-skylake-z170-motherboards-asrock-asus-gigabyte-msi-ecs-evga-supermicro
 | title = Intel Skylake Z170 Motherboards: A Quick Look at 55+ New Products
 | date = 2015-08-05 | access-date = 2015-08-06
 | author = Ian Cutress | publisher = [[AnandTech]]
}}</ref> some low power (Skylake-U onwards) and ultra low power (Skylake-Y onwards) mobile Intel processors have the PCH integrated into the physical package as a separate die, referred to as '''OPI''' (On Package DMI interconnect Interface)<ref>{{cite web
 | url = https://www.anandtech.com/show/10303/choosing-the-right-ssd-for-a-skylakeu-system
 | title = Choosing the Right SSD for a Skylake-U System
 | date = 2016-05-09 | access-date = 2016-11-16
 | author = Ganesh T S | publisher = [[AnandTech]]
}}</ref> and effectively following the [[system on a chip]] (SoC) design layout.<ref>{{cite web
 | url = http://www.cpu-world.com/news_2014/2014062601_More_details_on_Skylake_processors.html
 | title = More details on Skylake processors
 | date = 2014-06-26 | access-date = 2014-07-01
 | author = Gennadiy Shvets | website = cpu-world.com
}}</ref>
On 9 March 2015, Intel announced the Broadwell-based Xeon&nbsp;D as its first enterprise platform to fully incorporate the PCH in an SoC configuration.<ref>{{cite web|url=http://www.anandtech.com/show/9070/intel-xeon-d-launched-14nm-broadwell-soc-for-enterprise|title=Intel Xeon D Launched: 14nm Broadwell SoC for Enterprise|last1=Cutress |first1=Ian |date=9 March 2015|website=AnandTech|access-date=18 June 2015}}</ref>

In 2021, with the release of 500 series chipsets, Intel increased the amount of DMI 3.0 lanes from four to eight, doubling the bandwidth.<ref>{{Cite web|url=https://www.anandtech.com/show/16495/intel-rocket-lake-14nm-review-11900k-11700k-11600k/2|title = Intel Rocket Lake (14nm) Review: Core i9-11900K, Core i7-11700K, and Core i5-11600K}}</ref>

'''DMI 4.0''', released on November 4, 2021 with 600 series chipsets, doubles the bandwidth each lane provides and is two times faster when compared to DMI 3.0. The number of DMI 4.0 lanes depends on chipset model used.<ref>{{cite web |title=Intel 600 Series chipsets |url=https://ark.intel.com/content/www/us/en/ark/products/series/218828/intel-600-series-desktop-chipsets.html |website=Intel Ark |access-date=3 April 2022}}</ref>

==Implementations==
2005 [[Centrino|Centrino mobile platform]].{{R|name=:0|page=3}} At the time DMI linked the [[Northbridge (computing)|GMCH]] and [[I/O Controller Hub]].{{R|name=:0|page=3}}

Northbridge devices supporting a northbridge DMI are the Intel 915-series, 925-series, 945-series, 955-series, 965-series, 975-series, G31/33, [[Intel P35|P35]], [[Intel X38|X38]], [[Intel X48|X48]], [[Intel P45|P45]] and [[Intel X58|X58]].{{citation needed|date=May 2019}}

Processors supporting a northbridge DMI and, therefore, not using a separate northbridge, are the [[Intel Atom]], [[Intel Core&nbsp;i3]], [[Intel Core&nbsp;i5]], and [[Intel Core&nbsp;i7]] (8xx, 7xx and 6xx, but not 9xx). Processors supporting a northbridge DMI&nbsp;2.0 and, therefore not using a separate northbridge, are the 2000, 3000, 4000, and 5000 series of the [[Intel Core&nbsp;i3]], [[Intel Core i5|Core&nbsp;i5]] and [[Intel Core i7|Core&nbsp;i7]].

Southbridge devices supporting a southbridge DMI are the ICH6, ICH7, ICH8, ICH9, [[ICH10]], NM10, [[Intel P55|P55]], H55, H57, Q57, PM55, HM55, HM57, QM57 and QS57.{{citation needed|date=May 2019}}

PCH devices supporting DMI&nbsp;2.0 are the Intel B65, H61, H67, P67, Q65, Q67, Z68, HM65, HM67, QM67, QS67, B75, H77, Q75, Q77, Z75, Z77, [[Intel X79|X79]], HM75, HM76, HM77, QM77, QS77, UM77, [[LGA 1150|H81, B85, Q85, Q87, H87, Z87, H97, Z97, C222, C224, C226]], [[Intel X99|X99]], H110,<ref>{{cite web|url=http://ark.intel.com/products/90590/Intel-GL82H110-PCH|title=Intel H110 Chipset (Intel GL82H110 PCH)|work=Intel ARK (Product Specs)|access-date=28 January 2016}}</ref> and H310.<ref>{{Cite news|url=https://ark.intel.com/products/133348/Intel-H310-Chipset|title=Intel H310 Chipset Product Specifications|work=Intel ARK (Product Specs)|access-date=2018-07-22}}</ref>

PCH devices supporting DMI&nbsp;3.0 are the Intel&nbsp;Z170, H170, HM170, Q170, QM170, Q150, B150, C236, CM236, C232, and C620.<ref>{{cite web|url=http://ark.intel.com/products/90591/Intel-GL82Z170-PCH|title=Intel Z170 Chipset (Intel GL82Z170 PCH)|work=Intel ARK (Product Specs)|access-date=28 January 2016}}</ref><ref>{{cite web|url=http://ark.intel.com/products/90595/Intel-GL82H170-PCH|title=Intel H170 Chipset (Intel GL82H170 PCH)|work=Intel ARK (Product Specs)|access-date=28 January 2016}}</ref><ref>{{cite web|url=http://ark.intel.com/products/90584/Intel-GL82HM170-PCH|title=Mobile Intel HM170 Chipset (Intel GL82HM170 PCH)|work=Intel ARK (Product Specs)|access-date=28 January 2016}}</ref><ref>{{cite web|url=http://ark.intel.com/products/90587/Intel-GL82Q170-PCH|title=Intel Q170 Chipset (Intel GL82Q170 PCH)|work=Intel ARK (Product Specs)|access-date=28 January 2016}}</ref><ref>{{cite web|url=http://ark.intel.com/products/90583/Intel-GL82QM170-PCH|title=Mobile Intel QM170 Chipset (Intel GL82QM170 PCH)|work=Intel ARK (Product Specs)|access-date=28 January 2016}}</ref><ref>{{cite web|url=http://ark.intel.com/products/90588/Intel-GL82Q150-PCH|title=Intel Q150 Chipset (Intel GL82Q150 PCH)|work=Intel ARK (Product Specs)|access-date=28 January 2016}}</ref><ref>{{cite web|url=http://ark.intel.com/products/90592/Intel-GL82B150-PCH|title=Intel B150 Chipset (Intel GL82B150 PCH)|work=Intel ARK (Product Specs)|access-date=28 January 2016}}</ref><ref>{{cite web|url=http://ark.intel.com/products/90594/Intel-GL82C236-PCH|title=Intel C236 Chipset (Intel GL82C236 PCH)|work=Intel ARK (Product Specs)|access-date=28 January 2016}}</ref><ref>{{cite web|url=http://ark.intel.com/products/90593/Intel-GL82CM236-PCH|title=Mobile Intel CM236 Chipset (Intel GL82CM236 PCH)|work=Intel ARK (Product Specs)|access-date=28 January 2016}}</ref><ref>{{cite web|url=http://ark.intel.com/products/90578/Intel-GL82C232-PCH|title=Intel C232 Chipset (Intel GL82C232 PCH)|work=Intel ARK (Product Specs)|access-date=28 January 2016}}</ref> The [[Kaby Lake|Intel 200 series]], B360,<ref>{{Cite news|url=https://ark.intel.com/products/133332/Intel-B360-Chipset|title=Intel B360 Chipset Product Specifications|work=Intel ARK (Product Specs)|access-date=2018-07-22}}</ref> H370,<ref>{{Cite news|url=https://ark.intel.com/products/133284/Intel-H370-Chipset|title=Intel H370 Chipset Product Specifications|work=Intel ARK (Product Specs)|access-date=2018-07-22}}</ref> Q370,<ref>{{Cite news|url=https://ark.intel.com/products/133282/Intel-Q370-Chipset|title=Intel Q370 Chipset Product Specifications|work=Intel ARK (Product Specs)|access-date=2018-07-22}}</ref> Z370,<ref>{{Cite news|url=https://ark.intel.com/products/125903/Intel-Z370-Chipset|title=Intel Z370 Chipset Product Specifications|work=Intel ARK (Product Specs)|access-date=2018-07-22}}</ref> Z390,<ref>{{Cite news|url=https://ark.intel.com/products/133293/Intel-Z390-Chipset|title=Intel Z390 Chipset Product Specifications|work=Intel ARK (Product Specs)|access-date=2018-07-22}}</ref> C246,<ref>{{Cite news|url=https://ark.intel.com/products/147326/Intel-C246-chipset|title=Intel C246 Chipset Product Specifications|work=Intel ARK (Product Specs)|access-date=2018-07-22}}</ref> and [[Comet Lake|Intel 400 series]] chipsets also support DMI 3.0.

PCH devices supporting DMI 4.0 are the Intel 600 and 700 Series chipsets.<ref>{{cite web |title=Intel 600 Series chipsets |url=https://ark.intel.com/content/www/us/en/ark/products/series/218828/intel-600-series-desktop-chipsets.html |website=Intel Ark |access-date=3 April 2022}}</ref><ref>{{Cite web |title=Intel 700 Series Chipsets |url=https://ark.intel.com/content/www/us/en/ark/products/series/229717/intel-700-series-desktop-chipsets.html |access-date=11 October 2022 |website=Intel Ark}}</ref>

==See also==
* {{Annotated link|Front-side bus}}
* [[List of interface bit rates]]

==References==
{{Reflist|30em}}
{{Intel}}
{{Computer bus|state=collapsed}}

[[Category:Intel products]]
[[Category:Computer buses]]
[[Category:Serial buses]]