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{{short description|Method for converting signals between digital and analog}}
{{Redirect|Sigma delta|the sorority|Sigma Delta}}
{{Use American English|date=November 2021}}

[[File:Delta-Sigma Modulation ADC and DAC.svg|thumb|400x400px|Figure&nbsp;1: Full process of a 1{{Sup|st}}-order synchronous ΔΣ [[Analog-to-digital converter|ADC]] (top) and ΔΣ [[Digital-to-analog converter|DAC]] (bottom). Each contains a ΔΣ modulation [[negative feedback loop]] (the curly bracket) which outputs a new <span style="font-family:Noto Sans;">ΔΣM</span> result on each clock cycle, which is fed back for computing the next <span style="font-family:Noto Sans;">ΔΣM</span> result. The full conversion process for each typically includes post-[[Filter (signal processing)|filtering]] for demodulation and pre-filtering to remove [[Aliasing|aliases]] and noise. Analog is green. Digital is blue. The DDC (Digital-to-Digital Converter) requantizes its input from a high bit depth to a low bit depth. ]]
[[Image:Pulse-density modulation 1 period.gif|thumb|330x330px|1-bit synchronous delta-sigma modulation (blue) of a sine wave (red)]]
{{Modulation techniques}}

'''Delta-sigma''' ('''ΔΣ'''; or '''sigma-delta''', '''ΣΔ''') modulation is an [[oversampling]] method for encoding [[signals]] into low [[Audio bit depth|bit depth]] [[Digital signal (signal processing)|digital signals]] at a very high [[sampling frequency|sample-frequency]] as part of the process of delta-sigma [[analog-to-digital converter]]s (ADCs) and [[digital-to-analog converter]]s (DACs). Delta-sigma modulation achieves high [[Audio quality|quality]] by utilizing a [[negative feedback]] loop during quantization to the lower bit depth that continuously corrects [[quantization error]]s and moves quantization noise to higher frequencies well above the original signal's [[Bandwidth (signal processing)|bandwidth]]. Subsequent [[low-pass filtering]] for [[demodulation]] easily removes this high frequency noise and [[time average]]s to achieve high accuracy in amplitude, which can be ultimately encoded as [[pulse-code modulation]] (PCM).

Both ADCs and DACs can employ delta-sigma modulation. A delta-sigma ADC (e.g. Figure&nbsp;1 top) encodes an [[analog signal]] using high-frequency delta-sigma modulation and then applies a [[digital filter]] to demodulate it to a high-bit digital output at a lower sampling-frequency. A delta-sigma DAC (e.g. Figure&nbsp;1 bottom) encodes a high-resolution digital input signal into a lower-resolution but higher sample-frequency signal that may then be mapped to [[voltage]]s and smoothed with an analog filter for demodulation. In both cases, the temporary use of a low bit depth signal at a higher sampling frequency simplifies circuit design and takes advantage of the efficiency and high accuracy in time of [[digital electronics]].

Primarily because of its cost efficiency and reduced circuit complexity, this technique has found increasing use in modern electronic components such as DACs, ADCs, [[frequency synthesizer]]s, [[switched-mode power supplies]] and [[motor controller]]s.<ref>{{citation |url=https://www.numerix-dsp.com/appnotes/APR8-sigma-delta.pdf |title=Principles of Sigma-Delta Modulation for Analog-to-Digital Converters |publisher=Motorola |access-date=2017-09-01 |author=Sangil Park}}</ref> The coarsely-quantized output of a delta-sigma ADC is occasionally used directly in signal processing or as a representation for signal storage (e.g., [[Super Audio CD]] stores the raw output of a 1-bit delta-sigma modulator).

While this article focuses on [[Synchronous circuit|synchronous]] modulation, which requires a precise clock for quantization, [[Asynchronous circuit|asynchronous]] delta-sigma modulation instead runs without a clock.

== Motivation ==
When transmitting an analog signal directly, all [[Noise (electronics)|noise]] in the system and transmission is added to the analog signal, reducing its quality. [[Digitizing]] it enables noise-free transmission, storage, and processing. There are many methods of digitization.

In Nyquist-rate ADCs, an analog signal is [[Sampling (signal processing)|sampled]] at a relatively low sampling frequency just above its [[Nyquist rate]] (twice the signal's highest frequency) and [[Quantization (signal processing)|quantized]] by a multi-level quantizer to produce a multi-bit [[digital signal]]. Such higher-bit methods seek accuracy in amplitude directly, but require extremely precise components and so may suffer from poor linearity.

=== Advantages of oversampling ===
Oversampling converters instead produce a lower [[Audio bit depth|bit depth]] result at a much higher sampling frequency. This can achieve comparable quality by taking advantage of:

* Higher accuracy in time (afforded by high-speed digital circuits and highly accurate [[Crystal oscillator|clocks]]).
* Higher linearity afforded by low-bit ADCs and DACs (for instance, a 1-bit DAC that only outputs two values of a precise high voltage and a precise low voltage is perfectly linear, in principle).
* [[Noise shaping]]: moving noise to higher frequencies above the signal of interest, so they can be easily removed with [[low-pass filtering]].
* Reduced steepness requirement for the analog low-pass [[anti-aliasing filter]]s. High-order filters with a flat passband cost more to make in the analog domain than in the digital domain.

==== Frequency/resolution tradeoff ====
Another key aspect given by oversampling is the frequency/resolution tradeoff. The decimation filter put after the modulator not only filters the whole sampled signal in the band of interest (cutting the noise at higher frequencies), but also reduces the sampling rate, and hence the representable frequency range, of the signal, while increasing the sample amplitude resolution. This improvement in amplitude resolution is obtained by a sort of ''averaging'' of the higher-data-rate bitstream.

=== Improvement over delta modulation ===
[[Delta modulation]] is an earlier related low-bit oversampling method that also uses [[negative feedback]], but only encodes the [[derivative]] of the signal (its ''delta'') rather than its [[amplitude]]. The result is a stream of [[Mark and space|marks and spaces]] representing up or down of the signal's movement, which must be [[Integral|integrated]] to reconstruct the signal's amplitude. Delta modulation has several drawbacks. The differentiation alters the signal's spectrum by amplifying high-frequency noise, attenuating low-frequencies,<ref name=":5" /> and dropping the [[Direct current|DC]] component. This makes its dynamic range and [[signal-to-noise ratio]] (SNR) inversely proportional to signal frequency. Delta modulation suffers from [[Delta modulation#Slope overload|slope overload]] if signals move too fast. And it is susceptible to transmission disturbances that result in [[cumulative error]].

Delta-sigma modulation rearranges the [[integrator]] and quantizer of a delta modulator so that the output carries information corresponding to the amplitude of the input signal instead of just its derivative.<ref>{{Cite journal |last1=Inose |first1=H. |last2=Yasuda |first2=Y. |date=1963-11-01 |title=A unity bit coding method by negative feedback |url=https://ieeexplore.ieee.org/document/1444552 |journal=[[Proceedings of the IEEE]] |volume=51 |issue=11 |pages=1524–1535 |doi=10.1109/PROC.1963.2622 |issn=1558-2256 |via=[[IEEE Xplore]]|url-access=subscription }}</ref> This also has the benefit of incorporating desirable noise shaping into the conversion process, to deliberately move [[quantization noise]] to frequencies higher than the signal. Since the accumulated error signal is lowpass filtered by the delta-sigma modulator's integrator before being quantized, the subsequent negative feedback of its quantized result effectively subtracts the low-frequency components of the quantization noise while leaving the higher frequency components of the noise.

=== 1-bit delta-sigma modulation is pulse-density modulation ===
In the specific case of a single-bit synchronous ΔΣ ADC, an analog voltage signal is effectively converted into a pulse frequency, or pulse density, which can be understood as [[pulse-density modulation]] (PDM). A sequence of positive and negative pulses, representing bits at a known fixed rate, is very easy to generate, transmit, and accurately regenerate at the receiver, given only that the timing and sign of the pulses can be recovered. Given such a sequence of pulses from a delta-sigma modulator, the original waveform can be reconstructed with adequate precision.

The use of PDM as a signal representation is an alternative to PCM. Alternatively, the high-frequency PDM can later be [[downsampled]] through decimation and requantized to convert it into a multi-bit PCM code at a lower sampling frequency closer to the Nyquist rate of the frequency band of interest.

== History and variations ==
The seminal<ref name=":0">{{Cite web |last=Wooley |first=Bruce A. |date=2012-03-22 |title=The Evolution of Oversampling Analog-to-Digital Converters |url=https://r6.ieee.org/scv-sscs/wp-content/uploads/sites/80/2012/06/Oversampling-Wooley_SCV-ver2.pdf |url-status=live |archive-url=https://web.archive.org/web/20230628235029/https://r6.ieee.org/scv-sscs/wp-content/uploads/sites/80/2012/06/Oversampling-Wooley_SCV-ver2.pdf |archive-date=2023-06-28 |access-date=2023-06-28 |website=[[IEEE]] }}</ref> paper combining feedback with oversampling to achieve delta modulation was by F.&nbsp;de&nbsp;Jager of [[Philips Research Laboratories]] in 1952.<ref>F. de Jager, "Delta modulation, a method of PCM transmission using the 1-unit code," Philips Res. Rep., vol. 7, pp. 442–466, 1952.</ref>
[[File:Patent-US3192371-Brahm-Feedback-integrating-system-fig-1.png|thumb|"Feedback Integrating System" by Charles B Brahm: The entire top half of its Fig 1 is a delta-sigma modulator. Box #10 is a two-input [[integrator]]. The 4-bit analog-to-digital quantizer uses designations "S" (sign), "1", "2", and "4" for each bit. Each "F" stands for [[Flip-flop (electronics)|flip-flop]] and each "G" is a gate, controlled by the 110 kHz oscillator.]]
The principle of improving the resolution of a coarse quantizer by use of feedback, which is the basic principle of delta-sigma conversion, was first described in a 1954-filed patent by [[C. Chapin Cutler]] of [[Bell Labs]].<ref>{{cite patent |url=https://patents.google.com/patent/US2927962A/en |country=US |number=2967962 |title=Transmission systems employing quantization |inventor-first=Cassius C. |inventor-surname=Cutler |status=patent |pridate=April 26, 1954 |gdate=March 8, 1960}}</ref> It was not named as such until a 1962 paper<ref name="Inose" /> by Inose et al. of [[University of Tokyo]], which came up with the idea of adding a filter in the forward path of the delta modulator.<ref>{{Cite book |date=2001 |title=Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers: Chapter 4: Continuous-time sigma-delta modulation |chapter=Continuous-time sigma-delta modulation |series=The International Series in Engineering and Computer Science |volume=634 |pages=29–71 |chapter-url=https://link.springer.com/chapter/10.1007/0-306-48004-2_3 |url-status=live |archive-url=https://web.archive.org/web/20230629030428/https://link.springer.com/chapter/10.1007/0-306-48004-2_3 |archive-date=2023-06-29 |access-date=2023-06-28 |publisher=[[Springer Publishing]] |doi=10.1007/0-306-48004-2_3 |isbn=9780306480041 }}</ref>{{NoteTag|The delta-sigma configuration as described by Inose et al. in 1962 was devised to solve problems in the accurate transmission of analog signals. In that application it was the pulse stream that was transmitted and the original analog signal recovered with a lowpass filter after the received pulses had been reformed. This low pass filter performed the summation function associated with Σ. The highly mathematical treatment of transmission errors was introduced by them and is appropriate when applied to the pulse stream but these errors are lost in the accumulation process associated with Σ.}} However, Charles B Brahm of [[United Aircraft Corp.|United Aircraft Corp]]<ref>{{Cite web |title=Charles Brahm Obituary (1926 - 2021) - Hartford, CT - Hartford Courant |url=https://www.legacy.com/us/obituaries/hartfordcourant/name/charles-brahm-obituary?id=6645002 |access-date=2024-03-16 |website=Legacy.com}}</ref> in 1961 filed a patent "Feedback integrating system"<ref>{{Cite patent|number=US3192371A|title=Feedback integrating system|gdate=1965-06-29|invent1=Brahm|inventor1-first=Charles B.|url=https://patents.google.com/patent/US3192371A/en}}</ref> with a feedback loop containing an integrator with multi-bit quantization shown in its Fig 1.<ref name=":5">{{Cite journal |last=Razavi |first=Behzad |date=2016-06-21 |title=A Circuit for all Seasons: The Delta-Sigma Modulator |url=https://www.seas.ucla.edu/brweb/papers/Journals/BRSpring16DeltaSigma.pdf |url-status=live |archive-url=https://web.archive.org/web/20240209051709/https://www.seas.ucla.edu/brweb/papers/Journals/BRSpring16DeltaSigma.pdf |archive-date=2024-02-09 |access-date=2024-03-16 |journal=IEEE Solid-State Circuits Magazine |volume=8 |issue=2 |pages=10–15 |doi=10.1109/MSSC.2016.2543061}}</ref>

Wooley's "The Evolution of Oversampling Analog-to-Digital Converters"<ref name=":0" /> gives more history and references to relevant patents. Some avenues of variation (which may be applied in different combinations) are the modulator's order, the quantizer's bit depth, the manner of decimation, and the oversampling ratio.

=== Higher-order modulator ===
[[File:2nd order delta-sigma modulation loop.svg|thumb|333x333px|Figure&nbsp;2: Noise-feedback 2{{Sup|nd}}-order ΔΣ modulator ADC.]]
Noise of the quantizer can be further shaped by replacing the quantizer itself with another ΔΣ modulator. This creates a 2{{Sup|nd}}-order modulator, which can be rearranged in a cascaded fashion (Figure&nbsp;2).<ref name=":5" /> This process can be repeated to increase the order even more.

While 1{{Sup|st}}-order modulators are unconditionally stable, stability analysis must be performed for higher-order noise-feedback modulators. Alternatively, noise-feedforward configurations are always stable and have simpler analysis.<ref name=":3" />{{sup|§6.1}}

=== Multi-bit quantizer ===
The modulator can also be classified by the bit depth of its quantizer. A quantizer that distinguishes between ''N-levels'' is called a ''log<sub>2</sub>N'' bit quantizer. For example, a simple comparator has 2 levels and so is 1 bit quantizer; a 3-level quantizer is called a ''1.5'' bit quantizer; a 4-level quantizer is a 2-bit quantizer; a 5-level quantizer is called a ''2.5-bit'' quantizer.<ref name=":2">
[http://www.faqs.org/patents/app/20090072897 Sigma-delta class-D amplifier and control method for a sigma-delta class-D amplifier] by Jwin-Yen Guo and Teng-Hung Chang</ref> Higher bit quantizers inherently produce less quantization noise.

One criticism of 1-bit quantization is that adequate amounts of [[dither]] cannot be used in the feedback loop, so distortion can be heard under some conditions (more discussion at {{Slink|Direct Stream Digital|DSD vs. PCM}}).<ref>{{Cite web |last1=Lipschitz |first1=Stanley P. |last2=Vanderkooy |first2=John |date=2000-09-22 |title=Why Professional 1-Bit Sigma-Delta Conversion is a Bad Idea |url=http://peufeu.free.fr/audio/extremist_dac/files/1-Bit-Is-Bad.pdf |url-status=dead |archive-url=https://web.archive.org/web/20221102075257/http://peufeu.free.fr/audio/extremist_dac/files/1-Bit-Is-Bad.pdf |archive-date=2022-11-02}}</ref><ref>{{Cite web |last1=Lipshitz |first1=Stanley P. |last2=Vanderkooy |first2=John |date=2001-05-12 |title=Why 1-Bit Sigma-Delta Conversion is Unsuitable for High-Quality Applications |url=https://sjeng.org/ftp/SACD.pdf |url-status=live |archive-url=https://web.archive.org/web/20230430093353/https://sjeng.org/ftp/SACD.pdf |archive-date=2023-04-30 |access-date=2023-08-28}}</ref>

=== Subsequent decimation ===
Decimation is strongly associated with delta-sigma modulation, but is distinct and outside the scope of this article. The original 1962 paper didn't describe decimation. Oversampled data in the early days was sent as is. The proposal to [[Decimation (signal processing)|decimate]] oversampled delta-sigma data using [[digital filter]]ing before converting it into [[PCM]] audio was made by D.&nbsp;J.&nbsp;Goodman at Bell Labs in 1969,<ref name="analog">{{cite web |title=Data Converter Architectures: Chapter 3 |url=https://www.analog.com/media/en/training-seminars/design-handbooks/Data-Conversion-Handbook/Chapter3.pdf |access-date=October 27, 2018}}</ref> to reduce the ΔΣ signal from its high sampling rate while increasing its bit depth. Decimation may be done in a separate chip on the receiving end of the delta-sigma bit stream, sometimes by a dedicated module inside of a [[microcontroller]],<ref>{{Cite web |date=March 2018 |title=AN4990: Getting started with sigma-delta digital interface on applicable STM32 microcontrollers |url=https://www.st.com/resource/en/application_note/an4990-getting-started-with-sigmadelta-digital-interface-on-applicable-stm32-microcontrollers-stmicroelectronics.pdf |url-status=live |archive-url=https://web.archive.org/web/20220120133847/https://www.st.com/resource/en/application_note/an4990-getting-started-with-sigmadelta-digital-interface-on-applicable-stm32-microcontrollers-stmicroelectronics.pdf |archive-date=2022-01-20 |access-date=2023-09-03 |website=[[STMicroelectronics]]}}</ref> which is useful for interfacing with PDM [[MEMS microphone]]s,<ref>{{Cite web |last=Kite |first=Thomas |date=2012 |title=Understanding PDM Digital Audio |url=https://users.ece.utexas.edu/~bevans/courses/rtdsp/lectures/10_Data_Conversion/AP_Understanding_PDM_Digital_Audio.pdf |url-status=live |archive-url=https://web.archive.org/web/20230630230333/http://users.ece.utexas.edu/~bevans/courses/rtdsp/lectures/10_Data_Conversion/AP_Understanding_PDM_Digital_Audio.pdf |archive-date=2023-06-30 |access-date=2023-08-24}}</ref> though many ΔΣ ADC [[integrated circuits]] include decimation. Some microcontrollers even incorporate both the modulator and decimator.<ref>{{Cite web |date=2014 |title=MSP430i2xx Family |url=https://www.ti.com/lit/ug/slau335a/slau335a.pdf |url-status=live |archive-url=https://web.archive.org/web/20221015021911/https://www.ti.com/lit/ug/slau335a/slau335a.pdf |archive-date=2022-10-15 |access-date=2023-09-03 |website=[[Texas Instruments]]}}</ref>

Decimation filters most commonly used for ΔΣ ADCs, in order of increasing complexity and quality, are:

# [[Boxcar function|Boxcar moving average filter]] ([[simple moving average]] or [[Sinc filter#Frequency-domain sinc|sinc-in-frequency]] or sinc{{Sup|1}} filter): This is the easiest digital filter and retains a sharp step response, but is mediocre at separating frequency bands<ref>{{Cite book |last=Smith |first=Steven W. |title=The Scientist and Engineer's Guide to Digital Signal Processing |date=1999 |publisher=California Technical Pub |isbn=978-0-9660176-4-9 |edition=2nd |location=San Diego, Calif |chapter=Chapter 15: Moving Average Filters |chapter-url=https://www.analog.com/media/en/technical-documentation/dsp-book/dsp_book_Ch15.pdf }}</ref> and suffers from [[intermodulation distortion]]. The filter can be implemented by simply counting how many samples during a larger sampling interval are high. The 1974 paper from another Bell Labs researcher, J.&nbsp;C.&nbsp;Candy, "A Use of Limit Cycle Oscillations to Obtain Robust Analog-to-Digital Converters"<ref>{{Cite journal |last=Candy |first=J. |date=1974 |title=A Use of Limit Cycle Oscillations to Obtain Robust Analog-to-Digital Converters |url=https://ieeexplore.ieee.org/document/1092194 |journal=IEEE Transactions on Communications |volume=22 |issue=3 |pages=298–305 |doi=10.1109/TCOM.1974.1092194 |issn=1558-0857|url-access=subscription }}</ref> was one of the early examples of this.
# [[Cascaded integrator–comb filter]]s: These are called sinc{{Sup|N}} filters, equivalent to cascading the above sinc{{Sup|1}} filter N times and rearranging the order of operations for computational efficiency. Lower N filters are simpler, settle faster, and have less attenuation in the baseband, while higher N filters are slightly more complex and settle slower and have more droop in the passband, but better attenuate undesired high frequency noise. Compensation filters can however be applied to counteract undesired passband attenuation.<ref>{{Cite web |date=2007 |title=AN-455: Understanding CIC Compensation Filters |url=https://cdrdv2-public.intel.com/653906/an455.pdf |url-status=live |archive-url=https://web.archive.org/web/20230405082512/https://cdrdv2-public.intel.com/653906/an455.pdf |archive-date=2023-04-05 |access-date=2024-01-03 |website=[[Altera]]}}</ref> Sinc{{Sup|N}} filters are appropriate for decimating sigma delta modulation down to four times the Nyquist rate.<ref>{{Cite journal |last=Candy |first=J.C. |date=1986 |title=Decimation for Sigma Delta Modulation |url=https://ieeexplore.ieee.org/document/1096432 |access-date=2024-01-03 |journal=IEEE Transactions on Communications|volume=34 |pages=72–76 |doi=10.1109/TCOM.1986.1096432 |url-access=subscription }}</ref> The height of the first sideload is -13·N&nbsp;dB and the height of successive lobes fall off gradually, but only the areas around the nulls will alias into the low frequency band of interest; for instance when downsampling by 8, the largest ''aliased'' high frequency component may be -16&nbsp;dB below the peak of the band of interest with a sinc{{Sup|1}} filter but -40&nbsp;dB below for a sinc{{Sup|3}} filter, and if only interested in a narrower bandwidth, even fewer high frequency components will alias into it (see Figures 7–9 of Lyons article).<ref>{{Cite web |last=Lyons |first=Rick |date=2020-03-26 |title=A Beginner's Guide To Cascaded Integrator-Comb (CIC) Filters |url=https://www.dsprelated.com/showarticle/1337.php |url-status=live |archive-url=https://web.archive.org/web/20231022122431/https://www.dsprelated.com/showarticle/1337.php |archive-date=2023-10-22 |access-date=2024-01-03 |website=dsprelated.com}}</ref>
# Windowed [[Sinc filter|sinc-in-time (brick-wall in frequency) filters]]: Although the [[sinc function]]'s [[Support (mathematics)|infinite support]] prevents it from being [[Sinc filter#Unrealizable|realizable in finite time]], the sinc function can instead be [[Window function|windowed]] to realize [[finite impulse response]] filters. This approximated filter design, while maintaining ''almost no'' attenuation of the lower-frequency band of interest, still removes ''almost all'' undesired high-frequency noise. The downside is poor performance in the time domain (e.g. [[step response]] overshoot and ripple), higher delay (i.e. their [[convolution]] time is inversely proportional to their cutoff transition steepness), and higher computational requirements.<ref>{{Cite book |last=Smith |first=Steven W. |title=The Scientist & Engineer's Guide to Digital Signal Processing |date=1999 |publisher=California Technical Pub |isbn=978-0-9660176-4-9 |edition=2nd |location=San Diego, Calif |chapter=Chapter 16: Windowed-Sinc Filters |chapter-url=https://www.analog.com/media/en/technical-documentation/dsp-book/dsp_book_Ch16.pdf }}</ref> They are the [[de facto standard]] for [[high fidelity]] digital audio converters.

=== Other loop filters ===
Most commercial ΔΣ modulators use integrators as the loop filter, because as low-pass filters they push quantization noise up in frequency, which is useful for baseband signals. But a ΔΣ modulator's filter does not necessarily need to be a low-pass filter. If a [[band-pass filter]] is used instead, then quantization noise is moved up and down in frequency away from the filter's pass-band, so a subsequent pass-band decimation filter will result in a ΔΣ ADC with a bandpass characteristic.<ref>{{Cite web |last=Bryant |first=James M. |title=ADCs for DSP Applications |url=https://www.analog.com/media/en/training-seminars/design-handbooks/MixedSignal_Sect3.pdf |url-status=live |archive-url=https://web.archive.org/web/20240726045442/https://www.analog.com/media/en/training-seminars/design-handbooks/MixedSignal_Sect3.pdf |archive-date=2024-07-26 |website=[[Analog Devices]] |page=3.18}}</ref>

== Reduction of baseband noise by increasing oversampling ratio and ΔΣM order ==

[[File:Delta sigma.png|thumb|Figure&nbsp;3: Top: a sine wave input overlaid with its synchronous ΔΣ representation made using a high oversampling ratio. Middle: filtering the ΔΣ representation produces an approximation of the original sine wave. Bottom: residual error of the ΔΣ ADC, with and without adding [[dither]] noise.|319x319px]]

When a signal is quantized, the resulting signal can be approximated by addition of [[white noise]] with approximately equal intensity across the entire spectrum. In reality, the quantization noise is, of course, not independent of the signal and this dependence results in [[limit cycles]] and is the source of idle tones and pattern noise in delta-sigma converters. However, adding [[dithering]] noise (Figure&nbsp;3) reduces such [[distortion]] by making quantization noise more random.

ΔΣ ADCs reduce the amount of this noise in the [[baseband]] by spreading it out and shaping it so it is mostly in higher frequencies. It can then be easily filtered out with inexpensive digital filters, without high-precision analog circuits needed by Nyquist ADCs.

=== Oversampling to spread out quantization noise ===

Quantization noise in the baseband frequency range (from [[DC bias|DC]] to <math>2f_0</math>) may be reduced by increasing the oversampling ratio (OSR) defined by

:<math>\mathrm{OSR}\,=\,\frac{f_s}{2f_0} = 2^d</math>

where <math>f_\mathrm{s}</math> is the sampling frequency and <math>2f_0</math> is the Nyquist rate (the minimum sampling rate needed to avoid aliasing, which is twice the original signal's maximum frequency <math>f_0</math>). Since oversampling is typically done in powers of two, <math>d</math> represents how many times OSR is doubled.

[[File:DeltaSigmaNoise.svg|thumb|320px|right|Figure&nbsp;4: Noise shaping curves and noise spectrum in 1{{Sup|st}}, 2{{Sup|nd}}, and 3{{Sup|rd}}-order ΔΣ modulators.]]

As illustrated in Figure&nbsp;4, the total amount of quantization noise is the same both in a Nyquist converter (yellow + green areas) and in an oversampling converter (blue + green areas). But oversampling converters distribute that noise over a much wider frequency range. The benefit is that the total amount of noise in the frequency band of interest is dramatically smaller for oversampling converters (just the small green area), than for a Nyquist converter (yellow + green total area).

=== Noise shaping ===
Figure&nbsp;4 shows how ΔΣ modulation [[noise shaping|shapes noise]] to further reduce the amount of quantization noise in the baseband in exchange for increasing noise at higher frequencies (where it can be easily filtered out). The curves of higher-order ΔΣ modulators achieve even greater reduction of noise in the baseband.

These curves are derived using mathematical tools called the [[Laplace transform]] (for [[continuous-time signal]]s, e.g. in an ADC's modulation loop) or the [[Z-transform]] (for [[discrete-time signal]]s, e.g. in a DAC's modulation loop). These transforms are useful for converting harder math from the [[time domain]] into simpler math in the [[Complex number|complex]] [[frequency domain]] of the [[complex variable]] <math>\text{s} = \sigma + j \omega</math> (in the Laplace domain) or <math>\text{z} = A e^{j\phi}</math> (in the z-domain).

==== Analysis of ΔΣ ADC modulation loop in Laplace domain ====
Figure&nbsp;5 represents the 1{{Sup|st}}-order ΔΣ ADC modulation loop (from Figure&nbsp;1) as a continuous-time [[linear time-invariant system]] in the Laplace domain with the equation:

[[File:Delta-sigma modulation loop model with quantization noise.svg|thumb|Figure&nbsp;5: ΔΣ modulation loop in Laplace domain. Integration is multiplication by <math>\tfrac{1}\text{s}</math> and quantization is approximated by adding noise.|270x270px]]

<math display="block">[ \text{in} (\text{s}) - \Delta \Sigma \text{M} (\text{s}) ] \cdot \frac{1}{\text{s}} + \text{noise} (\text{s}) = \Delta \Sigma \text{M} (\text{s}) \, .</math>

The [[Laplace transform#Properties and theorems|Laplace transform of integration]] of a function of time corresponds to simply multiplication by <math>\tfrac{1}\text{s}</math> in Laplace notation. The integrator is assumed to be an ideal integrator to keep the math simple, but a [[Op amp integrator|real integrator]] (or similar filter) may have a more complicated expression.

The process of quantization is approximated as addition with a quantization error noise source. The noise is often assumed to be white and independent of the signal, though as {{slink|quantization (signal processing)|Additive noise model}} explains that is not always a valid assumption (particularly for low-bit quantization).

Since the system and Laplace transform are linear, the total behavior of this system can be analyzed by separating how it affects the input from how it affects the noise:<ref name=":3" />{{sup|§6}}

<math display="block">\Delta \Sigma \text{M}_{\text{total}} (\text{s}) = \Delta \Sigma \text{M}_\text{in} (\text{s}) + \Delta \Sigma \text{M}_\text{noise} (\text{s}) \, .</math>

===== Low-pass filter on input =====
To understand how the system affect the input signal only, the noise is temporarily imagined to be 0:

<math display="block">[\text{in}(\text{s})-\Delta \Sigma \text{M}_\text{in} (\text{s})] \cdot \frac{1}\text{s} + 0 = \Delta \Sigma \text{M}_\text{in} (\text{s}) \, ,</math>

which can be rearranged to yield the following [[transfer function]]:

<math display="block">\frac{\Delta \Sigma \text{M}_\text{in} (\text{s})}{\text{in}(\text{s})} = \frac{\tfrac{1}{\text{s}}}{1 + \tfrac{1}\text{s}} = \frac{1}{\text{s}+1} \, .</math>

This transfer function has a single [[Pole–zero plot|pole]] at <math>\text{s} = \text{-1}</math> in the [[complex plane]], so it effectively acts as a 1{{Sup|st}}-order low-pass filter on the input signal. (Note: its [[cutoff frequency]] could be adjusted as desired by including multiplication by a constant in the loop).

===== High-pass filter on noise =====
To understand how the system affects the noise only, the input instead is temporarily imagined to be 0:

<math display="block">[0 - \Delta \Sigma \text{M}_\text{noise} (\text{s}) ] \cdot \frac{1}\text{s} + \text{noise}(\text{s}) = \Delta \Sigma \text{M}_\text{noise} (\text{s}) \, ,</math>

which can be rearranged to yield the following transfer function:

<math display="block">\frac{\Delta \Sigma \text{M}_\text{noise} (\text{s})}{\text{noise}(\text{s})} = \frac{1}{1 + \tfrac{1}\text{s}} = \frac{s}{\text{s}+1} \, .</math>

This transfer function has a single zero at <math>\text{s} = 0</math> and a single pole at <math>\text{s} = \text{-1},</math> so the system effectively acts as a high-pass filter on the noise that starts at 0 at [[DC bias|DC]], then gradually rises until it reaches the cutoff frequency, and then levels off.

==== Analysis of synchronous ΔΣ modulation loop in z-domain ====
The synchronous ΔΣ DAC's modulation loop (Figure&nbsp;6) meanwhile is in discrete-time and so its analysis is in the z-domain. It is very similar to the above analysis in Laplace domain and produces similar curves. Note: many sources<ref name=":3" />{{sup|§6.1}}<ref name=":4" /><ref>{{Cite web |last=Reiss |first=Joshua D. |date=2008 |title=UNDERSTANDING SIGMA–DELTA MODULATION: The Solved and Unsolved Issues |url=https://www.eecs.qmul.ac.uk/~josh/documents/2008/Reiss-JAES-UnderstandingSigmaDeltaModulation-SolvedandUnsolvedIssues.pdf |url-status=live |archive-url=https://web.archive.org/web/20230901062957/http://www.eecs.qmul.ac.uk/~josh/documents/2008/Reiss-JAES-UnderstandingSigmaDeltaModulation-SolvedandUnsolvedIssues.pdf |archive-date=2023-09-01 |access-date=2023-09-01 |series=J. Audio Eng. Soc., Vol. 56, No. 1/2, 2008 January/February}}</ref> also analyze a ΔΣ ADC's modulation loop in the z-domain, which implicitly treats the continuous analog input as a discrete-time signal. This may be a valid approximation provided that the input signal is already bandlimited and can be assumed to be not changing on time scales higher than the sampling rate. It is particularly appropriate when the modulator is implemented as a [[switched capacitor]] circuit, which work by transferring charge between capacitors in clocked time steps.
[[File:Delta-sigma modulation in z-domain.svg|thumb|265x265px|Figure&nbsp;6: ΔΣ modulation loop in the z-domain.]]
Integration in discrete-time can be an [[Accumulator (computing)|accumulator]] which repeatedly sums its input <math>x[n]</math> with the previous result of its summation <math>y[n] = x[n] + y[n-1].</math> This is represented in the z-domain by feeding back a summing node's output <math>y(\text{z})</math> though a 1-clock cycle delay stage (notated as <math>\text{z}^\text{-1}</math>) into another input of the summing node, yielding {{No break|<math>y(\text{z}) = x(\text{z}) + y(\text{z})\cdot\text{z}^\text{-1}</math>.}} Its transfer function <math>\tfrac{1}{1-\text{z}^\text{-1}}</math> is often used to label integrators in block diagrams.

In a ΔΣ DAC, the quantizer may be called a ''requantizer'' or a ''digital-to-digital converter'' (DDC), because its input is already digital and quantized but is simply reducing from a higher bit depth to a lower bit depth digital signal. This is represented in the z-domain by another <math>\text{z}^\text{-1}</math> delay stage in series with adding quantization noise. (Note: some sources may have swapped ordering of the <math>\text{z}^\text{-1}</math> and additive noise stages.)

The modulator's z-domain equation arranged like Figure&nbsp;6 is:<math display="block">[\text{in}(\text{z}) - \Delta\Sigma\text{M}(\text{z})] \cdot \frac{1}{1-\text{z}^\text{-1}} \cdot \text{z}^\text{-1} + \text{noise}(\text{z}) = \Delta\Sigma\text{M}(\text{z}) \, ,</math>which can be rearranged to express the output in terms of the input and noise:<math display="block">\Delta\Sigma\text{M}(\text{z}) = \text{in}(\text{z}) \cdot \text{z}^\text{-1} + \text{noise}(\text{z}) \cdot (1 - \text{z}^\text{-1}) \, .</math>The input simply comes out of the system delayed by one clock cycle. The noise term's multiplication by <math>(1 - \text{z}^\text{-1})</math> represents a ''first difference backward'' filter (which has a single pole at the origin and a single zero at <math>\text{z}{=}1</math>) and thus high-pass filters the noise.

==== Higher order modulators ====

Without getting into the mathematical details,<ref name=":4" />{{Sup|(equations 8-11)}} cascading <math>\Theta</math> integrators to create an {{Nowrap|<math>\Theta^\text{th}</math>-order}} modulator results in:<math display="block">\Delta\Sigma\text{M}_\Theta(\text{z}) = \text{in}(\text{z}) \cdot \text{z}^\text{-1} + \text{noise}(\text{z}) \cdot (1 - \text{z}^\text{-1})^\Theta \, .</math>Since this ''first difference backwards'' filter is now raised to the power <math>\Theta</math> it will have a steeper noise shaping curve, for improved properties of greater attenuation in the baseband, so a dramatically larger portion of the noise is above the baseband and can be easily filtered by an ideal low-pass filter.

==== Theoretical effective number of bits ====
The theoretical SNR in [[decibels]] (dB) for a sinusoid input travelling through a {{Nowrap|<math>\Theta^\text{th}</math>-order}} modulator with a <math>2^d</math> OSR (and followed by an ideal low-pass decimation filter) can be mathematically derived to be approximately:<ref name=":4">{{Cite web |last=Van Ess |first=Dave |title=Signals From Noise: Calculating Delta-Sigma SNRs |url=https://www.ieee.li/pdf/essay/calculating_delta-sigma_snr.pdf |url-status=live |archive-url=https://web.archive.org/web/20230806002159/https://ieee.li/pdf/essay/calculating_delta-sigma_snr.pdf |archive-date=2023-08-06 |access-date=2023-08-22}}</ref>{{Sup|(equations 12-21)}}

<math display="block">\text{SNR}_\text{dB} \approx 3.01 \cdot (2 \cdot \Theta + 1) \cdot d - 9.36 \cdot \Theta - 2.76 \, .</math>The theoretical [[effective number of bits]] (ENOB) resolution is thus improved by <math display="inline">\Theta + \tfrac{1}{2}</math> bits when doubling the OSR (incrementing <math>d</math>), and by <math display="inline">d - \tfrac{3}{2}</math> bits when incrementing the order. For comparison, oversampling a Nyquist ADC (without any noise shaping) only improves its ENOB by <math>\tfrac{1}{2}</math> bits for every doubling of the OSR,<ref>{{Cite web |last1=Brown |first1=Ryan |last2=Singh |first2=Sameer |date=2016 |title=Application Report: General Oversampling of MSP ADCs for Higher Resolution |url=https://www.ti.com/lit/an/slaa694a/slaa694a.pdf |url-status=live |archive-url=https://web.archive.org/web/20220901080743/https://www.ti.com/lit/an/slaa694a/slaa694a.pdf |archive-date=2022-09-01 |access-date=2023-09-01 |website=[[Texas Instruments]]}}</ref> which is only {{Fraction|1|3}} of the ENOB growth rate of a 1{{Sup|st}}-order ΔΣM.
{| class="wikitable"
|+Theoretical SNR and ENOB versus delta-sigma modulation order and oversampling ratio (OSR)
! rowspan="2" |
! colspan="5" |Oversampling ratio
! rowspan="2" |each OSR
doubling
|-
!2{{Superscript|4}} OSR
!2{{Superscript|5}} OSR
!2{{Superscript|6}} OSR
!2{{Superscript|7}} OSR
!2{{Superscript|8}} OSR
|-
|{{Right|1{{sup|st}}-order:}}
|{{shade|100|24}} dB
{{Fraction|3|3|4}} bits
|{{shade|96|33}} dB
{{Fraction|5|1|4}} bits
|{{shade|92|42}} dB
{{Fraction|6|3|4}} bits
|{{shade|88|51}} dB
{{Fraction|8|1|4}} bits
|{{shade|84|60}} dB
{{Fraction|9|3|4}} bits
| +{{Fraction|1|1|2}} bits
|-
|{{Right|2{{Sup|nd}}-order:}}
|{{shade|93|39}} dB
{{Fraction|6|1|4}} bits
|{{shade|87|54}} dB
{{Fraction|8|3|4}} bits
|{{shade|80|69}} dB
{{Fraction|11|1|4}} bits
|{{shade|74|84}} dB
{{Fraction|13|3|4}} bits
|{{shade|67|99}} dB
{{Fraction|16|1|4}} bits
| +{{Fraction|2|1|2}} bits
|-
|{{Right|3{{Sup|rd}}-order:}}
|{{shade|87|53}} dB
{{Fraction|8|3|4}} bits
|{{shade|78|75}} dB
{{Fraction|12|1|4}} bits
|{{shade|69|96}} dB
{{Fraction|15|3|4}} bits
|{{shade|60|117}} dB
{{Fraction|19|1|4}} bits
|{{shade|50|138}} dB
{{Fraction|22|3|4}} bits
| +{{Fraction|3|1|2}} bits
|-
|{{Right|4{{Sup|th}}-order:}}
|{{shade|81|68}} dB
{{Fraction|11|1|4}} bits
|{{shade|69|95}} dB
{{Fraction|15|3|4}} bits
|{{shade|62|112}} dB
{{Fraction|20|1|4}} bits
|{{shade|46|149}} dB
{{Fraction|24|3|4}} bits
|{{shade|33|177}} dB
{{Fraction|29|1|2}} bits
| +{{Fraction|4|1|2}} bits
|-
|{{Right|5{{Sup|th}}-order:}}
|{{shade|74|83}} dB
{{Fraction|13|1|2}} bits
|{{shade|60|116}} dB
19 bits
|{{shade|46|149}} dB
{{Fraction|24|1|2}} bits
|{{shade|31|182}} dB
30 bits
|{{shade|17|215}} dB
{{Fraction|35|1|2}} bits
| +{{Fraction|5|1|2}} bits
|-
|{{Right|6{{Sup|th}}-order:}}
|{{shade|67|99}} dB
16 bits
|{{shade|51|137}} dB
{{Fraction|22|1|2}} bits
|{{shade|34|176}} dB
29 bits
|{{shade|17|215}} dB
{{Fraction|35|1|2}} bits
|{{shade|0|254}} dB
42 bits
| +{{Fraction|6|1|2}} bits
|-
|{{Right|each additional order:}}
| +{{Fraction|2|1|2}} bits
| +{{Fraction|3|1|2}} bits
| +{{Fraction|4|1|2}} bits
| +{{Fraction|5|1|2}} bits
| +{{Fraction|6|1|2}} bits
|
|}
These datapoints are theoretical. In practice, circuits inevitably experience other noise sources that limit resolution, making the higher-resolution cells impractical.

== Relationship to delta modulation ==
[[File:FromDtoDS raster.png|thumb|500px|right|Figure&nbsp;7: Derivation of delta-sigma from [[delta modulation]]]]

Delta-sigma modulation is related to [[delta modulation]] by the following steps (Figure&nbsp;7):<ref name=":3" />{{sup|§6}}
# Start with a block diagram of a delta modulator/demodulator.
# The [[Integral#Linearity|linearity property of integration]], <math display="inline"> \int a + \int b = \int (a + b)</math>, makes it possible to move the integrator from the demodulator to be before the summation.
# Again, the linearity property of integration allows the two integrators to be combined and a delta-sigma modulator/demodulator block diagram is obtained.
If [[Quantization (signal processing)|quantization]] were [[Homogeneous function|homogeneous]] (e.g., if it were [[linear]]), the above would be a sufficient derivation of their hypothetical equivalence. But because the quantizer is ''not'' homogeneous, delta-sigma is ''inspired'' by delta modulation, but the two are distinct in operation.

From the first block diagram in Figure&nbsp;7, the integrator in the feedback path can be removed if the feedback is taken directly from the input of the low-pass filter. Hence, for delta modulation of input signal {{Math|v<sub>in</sub>}}, the low-pass filter sees the signal
:<math> \int \operatorname{Quantize}\left( \text{v}_\text{in} - \text{v}_{\text{feedback}_\Delta} \right) dt .\,</math>
However, delta-sigma modulation of the same input signal places at the low-pass filter
:<math> \operatorname{Quantize}\left( \int \left( \text{v}_\text{in} - \text{v}_{\text{feedback}_{\Delta\Sigma}} \right) dt \right).\,</math>
In other words, doing delta-sigma modulation instead of delta modulation has effectively swapped the ordering of the integrator and quantizer operations. The net effect is a simpler implementation that has the profound added benefit of shaping the quantization noise to be mostly in frequencies above the signals of interest. This effect becomes more dramatic with increased [[oversampling]], which allows for quantization noise to be somewhat programmable. On the other hand, delta modulation shapes both noise and signal equally.

Additionally, the quantizer (e.g., [[comparator]]) used in delta modulation has a small output representing a small step up and down the quantized approximation of the input while the quantizer used in delta-sigma must take values ''outside'' of the range of the input signal.

In general, delta-sigma has some advantages versus delta modulation:
* The structure is simplified as
** only one integrator is needed,
** the demodulator can be a simple linear filter (e.g., RC or LC filter) to reconstruct the signal, and
** the quantizer (e.g., comparator) can have full-scale outputs.
* The quantized value is the integral of the difference signal, which
** makes it less sensitive to the rate of change of the signal, and
** helps capture low frequency and DC components.

==Analog-to-digital conversion example==
{{Multiple image
| image1            = Simple Circuit for Delta-Sigma Modulation.svg
| image2            = Simulation of Delta-Sigma Modulator.png
| direction         = vertical
| total_width       = 500
| caption1          = Figure 8a: Schematic of simple delta-sigma converter.
| caption2          = Figure 8b: Simulated scope view of key voltage signals over time. Each minor vertical division is 1 μs, which corresponds to a sampling event of the 1 MHz clock.
}}

Delta-sigma ADCs vary in complexity. The below circuit focuses on a simple 1st-order, 2-level quantization synchronous delta-sigma ADC without decimation.

=== Simplified circuit example ===
To ease understanding, a simple [[circuit schematic]] (Figure&nbsp;8a) using ideal elements is [[Circuit simulation|simulated]] (Figure&nbsp;8b voltages). It is functionally the same Analog-to-Digital ΔΣ modulation loop in Figure&nbsp;1 (note: the 2-input inverting integrator combines the summing junction and integrator and produces a negative feedback result, and the flip-flop combines the sampled quantizer and conveniently naturally functions as a 1-bit DAC too).

The 20&nbsp;kHz input [[sine wave]] '''{{font color|#1d9100|s(t)}}''' is converted to a 1-bit PDM digital result '''{{font color|#8c9100|Q(t)}}'''. 20&nbsp;kHz is used as an example because that is considered the upper [[Hearing range|limit of human hearing]].

This circuit can be laid out on a [[breadboard]] with inexpensive discrete components (note some variations use different biasing and use simpler [[RC circuit|RC low-pass filters]] for integration instead of [[op amps]]).<ref>{{Cite web |date=2021-01-09 |title=Activity: Delta - Sigma Modulator [Analog Devices Wiki] |url=https://wiki.analog.com/university/courses/electronics/electronics-lab-17 |url-status=live |archive-url=https://web.archive.org/web/20230401204844/https://wiki.analog.com/university/courses/electronics/electronics-lab-17 |archive-date=2023-04-01 |access-date=2023-07-01 |website=[[Analog Devices]]}}</ref><ref name=":1">{{Cite web |last=Ellsworth |first=Jeri |author-link=Jeri Ellsworth |date=2012-11-05 |title=One Bit ADC - Short Circuits |url=https://www.youtube.com/watch?v=DTCtx9eNHXE |access-date=2023-06-29 |website=[[YouTube]] |language=en-US}}</ref>

For simplicity, the [[D flip-flop]] is powered by dual supply voltages of V<sub>DD</sub> = +1&nbsp;V and V<sub>SS</sub> = -1&nbsp;V, so its binary output '''{{font color|#8c9100|Q(t)}}''' is either +1&nbsp;V or -1&nbsp;V.

==== 2-input inverting integrator ====
The 2-input inverting [[op amp integrator]] combines '''{{font color|#1d9100|s(t)}}''' with '''{{font color|#8c9100|Q(t)}}''' to produce '''{{font color|#bf0404||Ɛ(t)}}''':<math display="block"> \varepsilon(t) = -\frac{1}{RC}\int (s(t) + Q(t)) dt .</math>The Greek letter [[epsilon]] is used because '''{{font color|#bf0404||Ɛ(t)}}''' contains the accumulated [[round-off error|error]] that is repeatedly corrected by the feedback mechanism. While both its inputs '''{{font color|#1d9100|s(t)}}''' and '''{{font color|#8c9100|Q(t)}}''' vary between -1 and 1 volts, '''{{font color|#bf0404||Ɛ(t)}}''' instead only varies by a couple ''millivolts'' about 0&nbsp;V.

Because of the integrator's ''negative'' sign, when '''{{font color|#bf0404||Ɛ(t)}}''' next gets sampled to produce '''{{font color|#8c9100|Q(t)}}''', the +'''{{font color|#8c9100|Q(t)}}''' in this integral actually represents ''negative'' feedback from the previous clock cycle.

==== Quantizer and sampler flip-flop ====
An ideal [[D flip-flop]] samples '''{{font color|#bf0404||Ɛ(t)}}''' at the clock rate of 1&nbsp;[[MHz]]. The scope view (Figure&nbsp;8b) has a minor division equal to the [[sampling period]] of 1&nbsp;μs, so every minor division corresponds to a sampling event. Since the flip-flop is assumed to be ideal, it treats any input voltage greater than 0&nbsp;V as logical high and any input voltage smaller than 0&nbsp;V as logical low, no matter how close it is to 0&nbsp;V (ignoring issues of sample-and-hold time violations and [[Metastability (electronics)|metastability]]).

Whenever a sampling event occurs:

* if '''{{font color|#bf0404||Ɛ(t)}}''' is above the 0&nbsp;V threshold, then '''{{font color|#8c9100|Q(t)}}''' will go high (+1&nbsp;V), or
* if '''{{font color|#bf0404||Ɛ(t)}}''' is below the 0&nbsp;V threshold, then '''{{font color|#8c9100|Q(t)}}''' will go low (-1&nbsp;V).

'''{{font color|#8c9100|Q(t)}}''' is sent out as the resulting PDM output and also fed back to the 2-input inverting integrator.

==== Demodulation ====
The rightmost integrator performs digital-to-analog conversion on '''{{font color|#8c9100|Q(t)}}''' to produce a demodulated analog output '''{{font color|#00a6ff|r(t)}}''', which reconstructs the original sine wave input as piece-wise linear diagonal segments. Although '''{{font color|#00a6ff|r(t)}}''' appears coarse at this 50x oversampling rate, '''{{font color|#00a6ff|r(t)}}''' can be low-pass filtered to isolate the original signal. As the sampling rate is increased relative to the input signal's maximum frequency, '''{{font color|#00a6ff|r(t)}}''' will more closely approximate the original input '''{{font color|#1d9100|s(t)}}'''.

==Digital-to-analog conversion==

It is worth noting that if no decimation ever took place, the digital representation from a 1-bit delta-sigma modulator is simply a [[Pulse-density modulation#Digital-to-analog conversion|PDM signal, which can easily be converted to analog]] using a [[low-pass filter]], as simple as a [[RC circuit|resistor and capacitor]].<ref name=":1" />

However, in general, a delta-sigma DAC converts a [[Discrete time and continuous time#Discrete time|discrete time series]] signal of [[digital samples]] at a high bit depth into a low-bit-depth (often 1-bit) signal, usually at a much higher sampling rate. That delta-modulated signal can then be accurately converted into analog (since lower bit-depth DACs are easier to be highly-linear), which then goes through inexpensive low-pass filtering in the analog domain to remove the high-frequency quantization noise inherent to the delta-sigma modulation process.

=== Upsampling ===
{{Main|Upsampling#Interpolation filter design}}

As the [[discrete Fourier transform]] and [[discrete-time Fourier transform]] articles explain, a periodically sampled signal inherently contains multiple higher frequency copies or ''images'' of the signal. It is often desirable to remove these higher-frequency images prior to performing the actual delta-sigma modulation stage, in order to ease requirements on the eventual analog low-pass filter. This can be done by [[Upsampling#Interpolation filter design|upsampling using an interpolation filter]] and is often the first step prior to performing delta-sigma modulation in DACs. Upsampling is strongly associated with delta-sigma DACs but not strictly part of the actual delta-sigma modulation stage (similar to how decimation is strongly associated with delta-sigma ADCs but not strictly part of delta-sigma modulation either), and the details are out of the scope of this article.

=== Digital-to-digital delta-sigma modulation ===
The modulation loop in Figure&nbsp;6 in {{Slink|2=Noise shaping|nopage=y}} can easily be laid out with basic digital elements of a subtractor for the difference, an [[Accumulator (computing)|accumulator]] for the integrator, and a lower-bit [[Register (computer)|register]] for the quantization, which carries over the most-significant bit(s) from the integrator to be the feedback for the next cycle.

=== Multi-stage noise shaping ===
This simple 1{{Sup|st}}-order modulation can be improved by cascading two or more overflowing accumulators, each of which is equivalent to a 1{{Sup|st}}-order delta-sigma modulator. The resulting multi-stage noise shaping (MASH)<ref>{{Cite web |title=15-25 MHZ Fractional-N Synthesizer |url=http://www.aholme.co.uk/Frac2/Mash.htm}}</ref> structure has a steeper noise shaping property, so is commonly used in digital audio. The carry outputs are combined through summations and delays to produce a binary output, the width of which depends on the number of stages (order) of the MASH. Besides its noise-shaping function, it has two more attractive properties:
* simple to implement in hardware; only common digital blocks such as [[Accumulator (computing)|accumulators]], [[Adder (electronics)|adders]], and [[D flip-flop]]s are required
* unconditionally stable (there are no feedback loops outside the accumulators)

== Naming ==
The technique was first presented in the early 1960s by professor Yasuhiko Yasuda while he was a student at [[the University of Tokyo]].<ref>{{Cite web |title=発見と発明のデジタル博物館卓越研究データベース・電気・情報通信関連・研究情報(登録番号671) |url=https://dbnst.nii.ac.jp/pro/detail/671 |url-status=dead |archive-url=https://web.archive.org/web/20220408192822/https://dbnst.nii.ac.jp/pro/detail/671 |archive-date=2022-04-08}}</ref><ref name=":3">{{citation |author=Sangil Park |url=http://digitalsignallabs.com/SigmaDelta.pdf |archive-url=https://web.archive.org/web/20060621221221/http://digitalsignallabs.com/SigmaDelta.pdf |archive-date=2006-06-21 |title=Principles of sigma-delta modulation for analog-to-digital converters |publisher=Motorola}}</ref> The name ''delta-sigma'' comes directly from the presence of a delta modulator and an integrator, as firstly introduced by Inose et al. in their patent{{Clarification needed|reason=Did Yasuda or Inose file a patent on this? They did call it this in their 1962 paper, though, but I can't find that they have a patent on this. Or could it be in the Japanese patent system? Maybe this should be changed to say "as described in their 1962 paper."|date=July 2023}} application.<ref name="Inose">{{Cite journal |last1=Inose |first1=H. |last2=Yasuda |first2=Y. |last3=Murakami |first3=J. |date=1962-05-06 |title=A Telemetering System by Code Modulation - Δ- ΣModulation |url=https://ieeexplore.ieee.org/document/5008839 |journal=IRE Transactions on Space Electronics and Telemetry |publication-date=1962-09-01 |volume=SET-8 |issue=3 |pages=204–209 |doi=10.1109/IRET-SET.1962.5008839 |s2cid=51647729 |issn=2331-1657 |via=[[IEEE Xplore]]|url-access=subscription }}</ref> That is, the name comes from integrating or ''summing'' '''differences''', which, in mathematics, are operations usually associated with Greek letters [[sigma]] and [[delta (letter)|delta]] respectively.

In the 1970s, [[Bell Labs]] engineers used the terms ''sigma-delta'' because the precedent was to name variations on delta modulation with adjectives preceding ''delta'', and an [[Analog Devices]] magazine editor justified in 1990 that the functional hierarchy is ''sigma-delta'', because it computes the integral of a difference.<ref>{{Cite web |last=Sheingold |first=Dan |date=1990 |title=Editor's Notes: Σ-∆ or ∆-Σ? |url=https://www.analog.com/media/en/analog-dialogue/volume-24/number-2/articles/volume24-number2.pdf |url-status=live |archive-url=https://web.archive.org/web/20230629011911/https://www.analog.com/media/en/analog-dialogue/volume-24/number-2/articles/volume24-number2.pdf |archive-date=2023-06-29 |access-date=2023-06-28 |website=[[Analog Devices]]}}</ref>

Both names ''sigma-delta'' and ''delta-sigma'' are frequently used.

== Asynchronous delta-sigma modulation ==
[[File:Sigma-delta_PWM.svg|thumb|350x350px|Figure 9: 1-bit asynchronous ΔΣ modulation produces a PWM output (blue in bottom plot) which is subtracted from the input signal (green in top plot) to form an error signal (blue in top plot). This error is integrated (magenta in middle plot). When the integral of the error exceeds the limits (the upper and lower grey lines in middle plot), the PWM output changes state.]]
Kikkert and Miller published a continuous-time variant called Asynchronous Delta Sigma Modulation (ADSM or ASDM) in 1975 which uses either a [[Schmitt trigger]] (i.e. a comparator with [[hysteresis]]) or (as the paper argues is equivalent) a comparator with fixed delay.<ref>{{Cite journal |last1=Kikkert |first1=C. J. |last2=Miller |first2=D. J. |date=1975-04-01 |title=Asynchronous Delta Sigma Modulation |url=https://www.researchgate.net/publication/243767842 |journal=Proceedings of the IREE Australia |volume=36 |issue=4 |pages=83–88}}</ref>

In the example in Figure 9, when the integral of the error exceeds its limits, the output changes state, producing a [[Pulse-width modulation|pulse-width modulated]] (PWM) output wave.

Amplitude information is converted, without quantization noise, into time information of the output PWM.<ref>{{Cite book |last=Stork |first=Milan |chapter=Asynchronous sigma-delta modulator and fast demodulator |date=2015 |title=2015 25th International Conference Radioelektronika (RADIOELEKTRONIKA) |chapter-url=https://ieeexplore.ieee.org/document/7129003 |pages=180–183 |doi=10.1109/RADIOELEK.2015.7129003|isbn=978-1-4799-8117-5 }}</ref> To convert this continuous time PWM to discrete time, the PWM may be sampled by a time-to-digital converter, whose limited resolution adds noise which can be shaped by feeding it back.<ref>{{Cite web |last=Wei |first=Chen |date=2014 |title=Asynchronous Sigma Delta Modulators for Data Conversion - Ph.D. Thesis |url=https://spiral.imperial.ac.uk/bitstream/10044/1/23651/3/Wei-C-2014-PhD-Thesis.pdf |url-status=live |archive-url=https://web.archive.org/web/20200710101157/https://spiral.imperial.ac.uk/bitstream/10044/1/23651/3/Wei-C-2014-PhD-Thesis.pdf |archive-date=2020-07-10 |access-date=2024-03-16 |website=[[Imperial College of London]] |page=88}}</ref>

== See also ==
* [[Pulse-width modulation]]
* [[Continuously variable slope delta modulation]]
* [[Class-D amplifier]] (sometimes<ref name=":2" /> use delta-sigma modulation)

==Notes==
{{NoteFoot}}

==References==
{{Reflist}}

==Further reading==
*{{cite web |title=ADC Architectures III: Sigma-Delta ADC Basics |author=Walt Kester |url=http://www.analog.com/static/imported-files/tutorials/MT-022.pdf |publisher=Analog Devices |date=October 2008 |access-date=2010-11-02}}
*{{cite book |author=R. Jacob Baker |title=CMOS Mixed-Signal Circuit Design |url=http://CMOSedu.com/ |edition=2nd |publisher=Wiley-IEEE |isbn=978-0-470-29026-2 |year=2009}}
*{{cite book|author1=R. Schreier |author2=G. Temes |title=Understanding Delta-Sigma Data Converters|year=2005|publisher=Wiley |isbn=978-0-471-46585-0}}
*{{cite book|author1=S. Norsworthy |author2=R. Schreier |author3=G. Temes |title=Delta-Sigma Data Converters|year=1997|publisher=Wiley |isbn=978-0-7803-1045-2}}
*{{cite book|author1=J. Candy |author2=G. Temes |title=Oversampling Delta-sigma Data Converters|year=1992|publisher=Wiley |isbn=978-0-87942-285-1}}
*{{Cite thesis |last=Chen |first=Wei |title=Asynchronous sigma delta modulators for data conversion |date=2013 |access-date=2024-01-19 |degree=PhD |publisher=[[Imperial College London]] |url=https://core.ac.uk/download/pdf/76989701.pdf |doi=10.25560/23651 }}

== External links ==
* [http://www.cs.tut.fi/sgn/arg/rosti/1-bit/ 1-bit A/D and D/A Converters] {{Webarchive|url=https://web.archive.org/web/20210225050239/http://www.cs.tut.fi/sgn/arg/rosti/1-bit/ |date=2021-02-25 }}
* [http://www.embedded.com/design/configurable-systems/4006431/Sigma-delta-techniques-extend-DAC-resolution Sigma-delta techniques extend DAC resolution] article by Tim Wescott 2004-06-23
* [https://www.eetimes.com/tutorial-on-designing-delta-sigma-modulators-part-1/# Tutorial on Designing Delta-Sigma Modulators: Part I] and [https://www.eetimes.com/tutorial-on-designing-delta-sigma-modulators-part-2/# Part II] by Mingliang (Michael) Liu
* [http://eecs.oregonstate.edu/research/members/temes/pubs.html Gabor Temes' Publications]
* [http://electronjunkie.wordpress.com/tag/sigma-delta-modulation/ Sigma-Delta Modulation Primer Part II] Contains Block diagrams, code, and simple explanations
* [http://www.circuitdesign.info/blog/2008/09/example-simulink-model-scripts/ Example Simulink model & scripts for continuous-time sigma-delta ADC] Contains example matlab code and Simulink model
* [http://www-cis.stanford.edu/icl/wooley-grp/projects.html Bruce Wooley's Delta-Sigma Converter Projects]
* [http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html An Introduction to Delta Sigma Converters] (which covers both ADCs and DACs sigma-delta)
* [http://www.maxim-ic.com/appnotes.cfm/an_pk/1870/CMP/WP-10 Demystifying Sigma-Delta ADCs]. This in-depth article covers the theory behind a Delta-Sigma analog-to-digital converter.
* [https://web.archive.org/web/20061129090709/http://www.digitalsignallabs.com/presentation.pdf One-Bit Delta Sigma D/A Conversion Part I: Theory] article by Randy Yates presented at the 2004 comp.dsp conference
* [http://www.aholme.co.uk/Frac2/Mash.htm MASH (Multi-stAge noise SHaping) structure] with both theory and a block-level implementation of a MASH
* [http://www.circuitdesign.info/blog/2008/11/continuous-time-sigma-delta-adc-noise-shaping-filter-circuit-architectures-2/ Continuous time sigma-delta ADC noise shaping filter circuit architectures] discusses architectural trade-offs for continuous-time sigma-delta noise-shaping filters
* [https://www.cardinalpeak.com/delta-sigma-converters-modulation Delta Sigma Converters: Modulation] – intuitive motivation for why a delta-sigma modulator works
* [https://www.researchgate.net/publication/268357058_DIGITAL_ACCELEROMETER_WITH_FEEDBACK_CONTROL_USING_SIGMA_DELTA_MODULATION Digital accelerometer with feedback control using sigma-delta modulation]
* [https://www.analog.com/en/design-center/interactive-design-tools/sigma-delta-adc-tutorial.html Analog Devices Sigma-Delta ADC tutorial (interactive)]

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[[Category:Digital signal processing]]

[[fr:Convertisseur analogique-numérique#Convertisseur Sigma Delta]]